1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor/monitor.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 /* #define DEBUG_AHCI */ 37 38 #ifdef DEBUG_AHCI 39 #define DPRINTF(port, fmt, ...) \ 40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(port, fmt, ...) do {} while(0) 44 #endif 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s,int port,int slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 53 { 54 uint32_t val; 55 AHCIPortRegs *pr; 56 pr = &s->dev[port].port_regs; 57 58 switch (offset) { 59 case PORT_LST_ADDR: 60 val = pr->lst_addr; 61 break; 62 case PORT_LST_ADDR_HI: 63 val = pr->lst_addr_hi; 64 break; 65 case PORT_FIS_ADDR: 66 val = pr->fis_addr; 67 break; 68 case PORT_FIS_ADDR_HI: 69 val = pr->fis_addr_hi; 70 break; 71 case PORT_IRQ_STAT: 72 val = pr->irq_stat; 73 break; 74 case PORT_IRQ_MASK: 75 val = pr->irq_mask; 76 break; 77 case PORT_CMD: 78 val = pr->cmd; 79 break; 80 case PORT_TFDATA: 81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 82 s->dev[port].port.ifs[0].status; 83 break; 84 case PORT_SIG: 85 val = pr->sig; 86 break; 87 case PORT_SCR_STAT: 88 if (s->dev[port].port.ifs[0].bs) { 89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 91 } else { 92 val = SATA_SCR_SSTATUS_DET_NODEV; 93 } 94 break; 95 case PORT_SCR_CTL: 96 val = pr->scr_ctl; 97 break; 98 case PORT_SCR_ERR: 99 val = pr->scr_err; 100 break; 101 case PORT_SCR_ACT: 102 pr->scr_act &= ~s->dev[port].finished; 103 s->dev[port].finished = 0; 104 val = pr->scr_act; 105 break; 106 case PORT_CMD_ISSUE: 107 val = pr->cmd_issue; 108 break; 109 case PORT_RESERVED: 110 default: 111 val = 0; 112 } 113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 114 return val; 115 116 } 117 118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 119 { 120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 121 PCIDevice *pci_dev = 122 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 123 124 DPRINTF(0, "raise irq\n"); 125 126 if (pci_dev && msi_enabled(pci_dev)) { 127 msi_notify(pci_dev, 0); 128 } else { 129 qemu_irq_raise(s->irq); 130 } 131 } 132 133 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 134 { 135 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 136 PCIDevice *pci_dev = 137 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 138 139 DPRINTF(0, "lower irq\n"); 140 141 if (!pci_dev || !msi_enabled(pci_dev)) { 142 qemu_irq_lower(s->irq); 143 } 144 } 145 146 static void ahci_check_irq(AHCIState *s) 147 { 148 int i; 149 150 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 151 152 s->control_regs.irqstatus = 0; 153 for (i = 0; i < s->ports; i++) { 154 AHCIPortRegs *pr = &s->dev[i].port_regs; 155 if (pr->irq_stat & pr->irq_mask) { 156 s->control_regs.irqstatus |= (1 << i); 157 } 158 } 159 160 if (s->control_regs.irqstatus && 161 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 162 ahci_irq_raise(s, NULL); 163 } else { 164 ahci_irq_lower(s, NULL); 165 } 166 } 167 168 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 169 int irq_type) 170 { 171 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 172 irq_type, d->port_regs.irq_mask & irq_type); 173 174 d->port_regs.irq_stat |= irq_type; 175 ahci_check_irq(s); 176 } 177 178 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 179 uint32_t wanted) 180 { 181 hwaddr len = wanted; 182 183 if (*ptr) { 184 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 185 } 186 187 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); 188 if (len < wanted) { 189 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 190 *ptr = NULL; 191 } 192 } 193 194 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 195 { 196 AHCIPortRegs *pr = &s->dev[port].port_regs; 197 198 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 199 switch (offset) { 200 case PORT_LST_ADDR: 201 pr->lst_addr = val; 202 map_page(s->as, &s->dev[port].lst, 203 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 204 s->dev[port].cur_cmd = NULL; 205 break; 206 case PORT_LST_ADDR_HI: 207 pr->lst_addr_hi = val; 208 map_page(s->as, &s->dev[port].lst, 209 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 210 s->dev[port].cur_cmd = NULL; 211 break; 212 case PORT_FIS_ADDR: 213 pr->fis_addr = val; 214 map_page(s->as, &s->dev[port].res_fis, 215 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 216 break; 217 case PORT_FIS_ADDR_HI: 218 pr->fis_addr_hi = val; 219 map_page(s->as, &s->dev[port].res_fis, 220 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 221 break; 222 case PORT_IRQ_STAT: 223 pr->irq_stat &= ~val; 224 ahci_check_irq(s); 225 break; 226 case PORT_IRQ_MASK: 227 pr->irq_mask = val & 0xfdc000ff; 228 ahci_check_irq(s); 229 break; 230 case PORT_CMD: 231 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 232 233 if (pr->cmd & PORT_CMD_START) { 234 pr->cmd |= PORT_CMD_LIST_ON; 235 } 236 237 if (pr->cmd & PORT_CMD_FIS_RX) { 238 pr->cmd |= PORT_CMD_FIS_ON; 239 } 240 241 /* XXX usually the FIS would be pending on the bus here and 242 issuing deferred until the OS enables FIS receival. 243 Instead, we only submit it once - which works in most 244 cases, but is a hack. */ 245 if ((pr->cmd & PORT_CMD_FIS_ON) && 246 !s->dev[port].init_d2h_sent) { 247 ahci_init_d2h(&s->dev[port]); 248 s->dev[port].init_d2h_sent = true; 249 } 250 251 check_cmd(s, port); 252 break; 253 case PORT_TFDATA: 254 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 255 s->dev[port].port.ifs[0].status = val & 0xff; 256 break; 257 case PORT_SIG: 258 pr->sig = val; 259 break; 260 case PORT_SCR_STAT: 261 pr->scr_stat = val; 262 break; 263 case PORT_SCR_CTL: 264 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 265 ((val & AHCI_SCR_SCTL_DET) == 0)) { 266 ahci_reset_port(s, port); 267 } 268 pr->scr_ctl = val; 269 break; 270 case PORT_SCR_ERR: 271 pr->scr_err &= ~val; 272 break; 273 case PORT_SCR_ACT: 274 /* RW1 */ 275 pr->scr_act |= val; 276 break; 277 case PORT_CMD_ISSUE: 278 pr->cmd_issue |= val; 279 check_cmd(s, port); 280 break; 281 default: 282 break; 283 } 284 } 285 286 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 287 unsigned size) 288 { 289 AHCIState *s = opaque; 290 uint32_t val = 0; 291 292 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 293 switch (addr) { 294 case HOST_CAP: 295 val = s->control_regs.cap; 296 break; 297 case HOST_CTL: 298 val = s->control_regs.ghc; 299 break; 300 case HOST_IRQ_STAT: 301 val = s->control_regs.irqstatus; 302 break; 303 case HOST_PORTS_IMPL: 304 val = s->control_regs.impl; 305 break; 306 case HOST_VERSION: 307 val = s->control_regs.version; 308 break; 309 } 310 311 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 312 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 313 (addr < (AHCI_PORT_REGS_START_ADDR + 314 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 315 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 316 addr & AHCI_PORT_ADDR_OFFSET_MASK); 317 } 318 319 return val; 320 } 321 322 323 324 static void ahci_mem_write(void *opaque, hwaddr addr, 325 uint64_t val, unsigned size) 326 { 327 AHCIState *s = opaque; 328 329 /* Only aligned reads are allowed on AHCI */ 330 if (addr & 3) { 331 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 332 TARGET_FMT_plx "\n", addr); 333 return; 334 } 335 336 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 337 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 338 339 switch (addr) { 340 case HOST_CAP: /* R/WO, RO */ 341 /* FIXME handle R/WO */ 342 break; 343 case HOST_CTL: /* R/W */ 344 if (val & HOST_CTL_RESET) { 345 DPRINTF(-1, "HBA Reset\n"); 346 ahci_reset(s); 347 } else { 348 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 349 ahci_check_irq(s); 350 } 351 break; 352 case HOST_IRQ_STAT: /* R/WC, RO */ 353 s->control_regs.irqstatus &= ~val; 354 ahci_check_irq(s); 355 break; 356 case HOST_PORTS_IMPL: /* R/WO, RO */ 357 /* FIXME handle R/WO */ 358 break; 359 case HOST_VERSION: /* RO */ 360 /* FIXME report write? */ 361 break; 362 default: 363 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 364 } 365 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 366 (addr < (AHCI_PORT_REGS_START_ADDR + 367 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 368 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 369 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 370 } 371 372 } 373 374 static const MemoryRegionOps ahci_mem_ops = { 375 .read = ahci_mem_read, 376 .write = ahci_mem_write, 377 .endianness = DEVICE_LITTLE_ENDIAN, 378 }; 379 380 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 381 unsigned size) 382 { 383 AHCIState *s = opaque; 384 385 if (addr == s->idp_offset) { 386 /* index register */ 387 return s->idp_index; 388 } else if (addr == s->idp_offset + 4) { 389 /* data register - do memory read at location selected by index */ 390 return ahci_mem_read(opaque, s->idp_index, size); 391 } else { 392 return 0; 393 } 394 } 395 396 static void ahci_idp_write(void *opaque, hwaddr addr, 397 uint64_t val, unsigned size) 398 { 399 AHCIState *s = opaque; 400 401 if (addr == s->idp_offset) { 402 /* index register - mask off reserved bits */ 403 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 404 } else if (addr == s->idp_offset + 4) { 405 /* data register - do memory write at location selected by index */ 406 ahci_mem_write(opaque, s->idp_index, val, size); 407 } 408 } 409 410 static const MemoryRegionOps ahci_idp_ops = { 411 .read = ahci_idp_read, 412 .write = ahci_idp_write, 413 .endianness = DEVICE_LITTLE_ENDIAN, 414 }; 415 416 417 static void ahci_reg_init(AHCIState *s) 418 { 419 int i; 420 421 s->control_regs.cap = (s->ports - 1) | 422 (AHCI_NUM_COMMAND_SLOTS << 8) | 423 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 424 HOST_CAP_NCQ | HOST_CAP_AHCI; 425 426 s->control_regs.impl = (1 << s->ports) - 1; 427 428 s->control_regs.version = AHCI_VERSION_1_0; 429 430 for (i = 0; i < s->ports; i++) { 431 s->dev[i].port_state = STATE_RUN; 432 } 433 } 434 435 static void check_cmd(AHCIState *s, int port) 436 { 437 AHCIPortRegs *pr = &s->dev[port].port_regs; 438 int slot; 439 440 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 441 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 442 if ((pr->cmd_issue & (1U << slot)) && 443 !handle_cmd(s, port, slot)) { 444 pr->cmd_issue &= ~(1U << slot); 445 } 446 } 447 } 448 } 449 450 static void ahci_check_cmd_bh(void *opaque) 451 { 452 AHCIDevice *ad = opaque; 453 454 qemu_bh_delete(ad->check_bh); 455 ad->check_bh = NULL; 456 457 if ((ad->busy_slot != -1) && 458 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 459 /* no longer busy */ 460 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 461 ad->busy_slot = -1; 462 } 463 464 check_cmd(ad->hba, ad->port_no); 465 } 466 467 static void ahci_init_d2h(AHCIDevice *ad) 468 { 469 uint8_t init_fis[20]; 470 IDEState *ide_state = &ad->port.ifs[0]; 471 472 memset(init_fis, 0, sizeof(init_fis)); 473 474 init_fis[4] = 1; 475 init_fis[12] = 1; 476 477 if (ide_state->drive_kind == IDE_CD) { 478 init_fis[5] = ide_state->lcyl; 479 init_fis[6] = ide_state->hcyl; 480 } 481 482 ahci_write_fis_d2h(ad, init_fis); 483 } 484 485 static void ahci_reset_port(AHCIState *s, int port) 486 { 487 AHCIDevice *d = &s->dev[port]; 488 AHCIPortRegs *pr = &d->port_regs; 489 IDEState *ide_state = &d->port.ifs[0]; 490 int i; 491 492 DPRINTF(port, "reset port\n"); 493 494 ide_bus_reset(&d->port); 495 ide_state->ncq_queues = AHCI_MAX_CMDS; 496 497 pr->scr_stat = 0; 498 pr->scr_err = 0; 499 pr->scr_act = 0; 500 d->busy_slot = -1; 501 d->init_d2h_sent = false; 502 503 ide_state = &s->dev[port].port.ifs[0]; 504 if (!ide_state->bs) { 505 return; 506 } 507 508 /* reset ncq queue */ 509 for (i = 0; i < AHCI_MAX_CMDS; i++) { 510 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 511 if (!ncq_tfs->used) { 512 continue; 513 } 514 515 if (ncq_tfs->aiocb) { 516 bdrv_aio_cancel(ncq_tfs->aiocb); 517 ncq_tfs->aiocb = NULL; 518 } 519 520 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 521 if (!ncq_tfs->used) { 522 continue; 523 } 524 525 qemu_sglist_destroy(&ncq_tfs->sglist); 526 ncq_tfs->used = 0; 527 } 528 529 s->dev[port].port_state = STATE_RUN; 530 if (!ide_state->bs) { 531 s->dev[port].port_regs.sig = 0; 532 ide_state->status = SEEK_STAT | WRERR_STAT; 533 } else if (ide_state->drive_kind == IDE_CD) { 534 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 535 ide_state->lcyl = 0x14; 536 ide_state->hcyl = 0xeb; 537 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 538 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 539 } else { 540 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 541 ide_state->status = SEEK_STAT | WRERR_STAT; 542 } 543 544 ide_state->error = 1; 545 ahci_init_d2h(d); 546 } 547 548 static void debug_print_fis(uint8_t *fis, int cmd_len) 549 { 550 #ifdef DEBUG_AHCI 551 int i; 552 553 fprintf(stderr, "fis:"); 554 for (i = 0; i < cmd_len; i++) { 555 if ((i & 0xf) == 0) { 556 fprintf(stderr, "\n%02x:",i); 557 } 558 fprintf(stderr, "%02x ",fis[i]); 559 } 560 fprintf(stderr, "\n"); 561 #endif 562 } 563 564 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 565 { 566 AHCIPortRegs *pr = &s->dev[port].port_regs; 567 IDEState *ide_state; 568 uint8_t *sdb_fis; 569 570 if (!s->dev[port].res_fis || 571 !(pr->cmd & PORT_CMD_FIS_RX)) { 572 return; 573 } 574 575 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 576 ide_state = &s->dev[port].port.ifs[0]; 577 578 /* clear memory */ 579 *(uint32_t*)sdb_fis = 0; 580 581 /* write values */ 582 sdb_fis[0] = ide_state->error; 583 sdb_fis[2] = ide_state->status & 0x77; 584 s->dev[port].finished |= finished; 585 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 586 587 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_SDB_FIS); 588 } 589 590 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) 591 { 592 AHCIPortRegs *pr = &ad->port_regs; 593 uint8_t *pio_fis, *cmd_fis; 594 uint64_t tbl_addr; 595 dma_addr_t cmd_len = 0x80; 596 597 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 598 return; 599 } 600 601 /* map cmd_fis */ 602 tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 603 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 604 DMA_DIRECTION_TO_DEVICE); 605 606 if (cmd_fis == NULL) { 607 DPRINTF(ad->port_no, "dma_memory_map failed in ahci_write_fis_pio"); 608 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR); 609 return; 610 } 611 612 if (cmd_len != 0x80) { 613 DPRINTF(ad->port_no, 614 "dma_memory_map mapped too few bytes in ahci_write_fis_pio"); 615 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 616 DMA_DIRECTION_TO_DEVICE, cmd_len); 617 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR); 618 return; 619 } 620 621 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 622 623 pio_fis[0] = 0x5f; 624 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 625 pio_fis[2] = ad->port.ifs[0].status; 626 pio_fis[3] = ad->port.ifs[0].error; 627 628 pio_fis[4] = cmd_fis[4]; 629 pio_fis[5] = cmd_fis[5]; 630 pio_fis[6] = cmd_fis[6]; 631 pio_fis[7] = cmd_fis[7]; 632 pio_fis[8] = cmd_fis[8]; 633 pio_fis[9] = cmd_fis[9]; 634 pio_fis[10] = cmd_fis[10]; 635 pio_fis[11] = cmd_fis[11]; 636 pio_fis[12] = cmd_fis[12]; 637 pio_fis[13] = cmd_fis[13]; 638 pio_fis[14] = 0; 639 pio_fis[15] = ad->port.ifs[0].status; 640 pio_fis[16] = len & 255; 641 pio_fis[17] = len >> 8; 642 pio_fis[18] = 0; 643 pio_fis[19] = 0; 644 645 if (pio_fis[2] & ERR_STAT) { 646 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 647 } 648 649 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS); 650 651 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 652 DMA_DIRECTION_TO_DEVICE, cmd_len); 653 } 654 655 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 656 { 657 AHCIPortRegs *pr = &ad->port_regs; 658 uint8_t *d2h_fis; 659 int i; 660 dma_addr_t cmd_len = 0x80; 661 int cmd_mapped = 0; 662 663 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 664 return; 665 } 666 667 if (!cmd_fis) { 668 /* map cmd_fis */ 669 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 670 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 671 DMA_DIRECTION_TO_DEVICE); 672 cmd_mapped = 1; 673 } 674 675 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 676 677 d2h_fis[0] = 0x34; 678 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 679 d2h_fis[2] = ad->port.ifs[0].status; 680 d2h_fis[3] = ad->port.ifs[0].error; 681 682 d2h_fis[4] = cmd_fis[4]; 683 d2h_fis[5] = cmd_fis[5]; 684 d2h_fis[6] = cmd_fis[6]; 685 d2h_fis[7] = cmd_fis[7]; 686 d2h_fis[8] = cmd_fis[8]; 687 d2h_fis[9] = cmd_fis[9]; 688 d2h_fis[10] = cmd_fis[10]; 689 d2h_fis[11] = cmd_fis[11]; 690 d2h_fis[12] = cmd_fis[12]; 691 d2h_fis[13] = cmd_fis[13]; 692 for (i = 14; i < 20; i++) { 693 d2h_fis[i] = 0; 694 } 695 696 if (d2h_fis[2] & ERR_STAT) { 697 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 698 } 699 700 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 701 702 if (cmd_mapped) { 703 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 704 DMA_DIRECTION_TO_DEVICE, cmd_len); 705 } 706 } 707 708 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 709 { 710 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 711 } 712 713 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset) 714 { 715 AHCICmdHdr *cmd = ad->cur_cmd; 716 uint32_t opts = le32_to_cpu(cmd->opts); 717 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 718 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 719 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 720 dma_addr_t real_prdt_len = prdt_len; 721 uint8_t *prdt; 722 int i; 723 int r = 0; 724 int sum = 0; 725 int off_idx = -1; 726 int off_pos = -1; 727 int tbl_entry_size; 728 IDEBus *bus = &ad->port; 729 BusState *qbus = BUS(bus); 730 731 if (!sglist_alloc_hint) { 732 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 733 return -1; 734 } 735 736 /* map PRDT */ 737 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 738 DMA_DIRECTION_TO_DEVICE))){ 739 DPRINTF(ad->port_no, "map failed\n"); 740 return -1; 741 } 742 743 if (prdt_len < real_prdt_len) { 744 DPRINTF(ad->port_no, "mapped less than expected\n"); 745 r = -1; 746 goto out; 747 } 748 749 /* Get entries in the PRDT, init a qemu sglist accordingly */ 750 if (sglist_alloc_hint > 0) { 751 AHCI_SG *tbl = (AHCI_SG *)prdt; 752 sum = 0; 753 for (i = 0; i < sglist_alloc_hint; i++) { 754 /* flags_size is zero-based */ 755 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 756 if (offset <= (sum + tbl_entry_size)) { 757 off_idx = i; 758 off_pos = offset - sum; 759 break; 760 } 761 sum += tbl_entry_size; 762 } 763 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 764 DPRINTF(ad->port_no, "%s: Incorrect offset! " 765 "off_idx: %d, off_pos: %d\n", 766 __func__, off_idx, off_pos); 767 r = -1; 768 goto out; 769 } 770 771 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx), 772 ad->hba->as); 773 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos), 774 prdt_tbl_entry_size(&tbl[off_idx]) - off_pos); 775 776 for (i = off_idx + 1; i < sglist_alloc_hint; i++) { 777 /* flags_size is zero-based */ 778 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 779 prdt_tbl_entry_size(&tbl[i])); 780 } 781 } 782 783 out: 784 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 785 DMA_DIRECTION_TO_DEVICE, prdt_len); 786 return r; 787 } 788 789 static void ncq_cb(void *opaque, int ret) 790 { 791 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 792 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 793 794 /* Clear bit for this tag in SActive */ 795 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 796 797 if (ret < 0) { 798 /* error */ 799 ide_state->error = ABRT_ERR; 800 ide_state->status = READY_STAT | ERR_STAT; 801 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 802 } else { 803 ide_state->status = READY_STAT | SEEK_STAT; 804 } 805 806 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 807 (1 << ncq_tfs->tag)); 808 809 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 810 ncq_tfs->tag); 811 812 block_acct_done(bdrv_get_stats(ncq_tfs->drive->port.ifs[0].bs), 813 &ncq_tfs->acct); 814 qemu_sglist_destroy(&ncq_tfs->sglist); 815 ncq_tfs->used = 0; 816 } 817 818 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 819 int slot) 820 { 821 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 822 uint8_t tag = ncq_fis->tag >> 3; 823 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 824 825 if (ncq_tfs->used) { 826 /* error - already in use */ 827 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 828 return; 829 } 830 831 ncq_tfs->used = 1; 832 ncq_tfs->drive = &s->dev[port]; 833 ncq_tfs->slot = slot; 834 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 835 ((uint64_t)ncq_fis->lba4 << 32) | 836 ((uint64_t)ncq_fis->lba3 << 24) | 837 ((uint64_t)ncq_fis->lba2 << 16) | 838 ((uint64_t)ncq_fis->lba1 << 8) | 839 (uint64_t)ncq_fis->lba0; 840 841 /* Note: We calculate the sector count, but don't currently rely on it. 842 * The total size of the DMA buffer tells us the transfer size instead. */ 843 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 844 ncq_fis->sector_count_low; 845 846 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 847 "drive max %"PRId64"\n", 848 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 849 s->dev[port].port.ifs[0].nb_sectors - 1); 850 851 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0); 852 ncq_tfs->tag = tag; 853 854 switch(ncq_fis->command) { 855 case READ_FPDMA_QUEUED: 856 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 857 "tag %d\n", 858 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 859 860 DPRINTF(port, "tag %d aio read %"PRId64"\n", 861 ncq_tfs->tag, ncq_tfs->lba); 862 863 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 864 &ncq_tfs->sglist, BLOCK_ACCT_READ); 865 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 866 &ncq_tfs->sglist, ncq_tfs->lba, 867 ncq_cb, ncq_tfs); 868 break; 869 case WRITE_FPDMA_QUEUED: 870 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 871 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 872 873 DPRINTF(port, "tag %d aio write %"PRId64"\n", 874 ncq_tfs->tag, ncq_tfs->lba); 875 876 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 877 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 878 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 879 &ncq_tfs->sglist, ncq_tfs->lba, 880 ncq_cb, ncq_tfs); 881 break; 882 default: 883 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 884 qemu_sglist_destroy(&ncq_tfs->sglist); 885 break; 886 } 887 } 888 889 static int handle_cmd(AHCIState *s, int port, int slot) 890 { 891 IDEState *ide_state; 892 uint32_t opts; 893 uint64_t tbl_addr; 894 AHCICmdHdr *cmd; 895 uint8_t *cmd_fis; 896 dma_addr_t cmd_len; 897 898 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 899 /* Engine currently busy, try again later */ 900 DPRINTF(port, "engine busy\n"); 901 return -1; 902 } 903 904 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 905 906 if (!s->dev[port].lst) { 907 DPRINTF(port, "error: lst not given but cmd handled"); 908 return -1; 909 } 910 911 /* remember current slot handle for later */ 912 s->dev[port].cur_cmd = cmd; 913 914 opts = le32_to_cpu(cmd->opts); 915 tbl_addr = le64_to_cpu(cmd->tbl_addr); 916 917 cmd_len = 0x80; 918 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 919 DMA_DIRECTION_FROM_DEVICE); 920 921 if (!cmd_fis) { 922 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 923 return -1; 924 } 925 926 /* The device we are working for */ 927 ide_state = &s->dev[port].port.ifs[0]; 928 929 if (!ide_state->bs) { 930 DPRINTF(port, "error: guest accessed unused port"); 931 goto out; 932 } 933 934 debug_print_fis(cmd_fis, 0x90); 935 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 936 937 switch (cmd_fis[0]) { 938 case SATA_FIS_TYPE_REGISTER_H2D: 939 break; 940 default: 941 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 942 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 943 cmd_fis[2]); 944 goto out; 945 break; 946 } 947 948 switch (cmd_fis[1]) { 949 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 950 break; 951 case 0: 952 break; 953 default: 954 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 955 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 956 cmd_fis[2]); 957 goto out; 958 break; 959 } 960 961 switch (s->dev[port].port_state) { 962 case STATE_RUN: 963 if (cmd_fis[15] & ATA_SRST) { 964 s->dev[port].port_state = STATE_RESET; 965 } 966 break; 967 case STATE_RESET: 968 if (!(cmd_fis[15] & ATA_SRST)) { 969 ahci_reset_port(s, port); 970 } 971 break; 972 } 973 974 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 975 976 /* Check for NCQ command */ 977 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 978 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 979 process_ncq_command(s, port, cmd_fis, slot); 980 goto out; 981 } 982 983 /* Decompose the FIS */ 984 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 985 ide_state->feature = cmd_fis[3]; 986 if (!ide_state->nsector) { 987 ide_state->nsector = 256; 988 } 989 990 if (ide_state->drive_kind != IDE_CD) { 991 /* 992 * We set the sector depending on the sector defined in the FIS. 993 * Unfortunately, the spec isn't exactly obvious on this one. 994 * 995 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 996 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 997 * such a command. 998 * 999 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 1000 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 1001 * a command. 1002 * 1003 * Since the spec doesn't explicitly state what each field should 1004 * do, I simply assume non-used fields as reserved and OR everything 1005 * together, independent of the command. 1006 */ 1007 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 1008 | ((uint64_t)cmd_fis[9] << 32) 1009 /* This is used for LBA48 commands */ 1010 | ((uint64_t)cmd_fis[8] << 24) 1011 /* This is used for non-LBA48 commands */ 1012 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 1013 | ((uint64_t)cmd_fis[6] << 16) 1014 | ((uint64_t)cmd_fis[5] << 8) 1015 | cmd_fis[4]); 1016 } 1017 1018 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1019 * table to ide_state->io_buffer 1020 */ 1021 if (opts & AHCI_CMD_ATAPI) { 1022 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1023 ide_state->lcyl = 0x14; 1024 ide_state->hcyl = 0xeb; 1025 debug_print_fis(ide_state->io_buffer, 0x10); 1026 ide_state->feature = IDE_FEATURE_DMA; 1027 s->dev[port].done_atapi_packet = false; 1028 /* XXX send PIO setup FIS */ 1029 } 1030 1031 ide_state->error = 0; 1032 1033 /* Reset transferred byte counter */ 1034 cmd->status = 0; 1035 1036 /* We're ready to process the command in FIS byte 2. */ 1037 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1038 } 1039 1040 out: 1041 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 1042 cmd_len); 1043 1044 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1045 /* async command, complete later */ 1046 s->dev[port].busy_slot = slot; 1047 return -1; 1048 } 1049 1050 /* done handling the command */ 1051 return 0; 1052 } 1053 1054 /* DMA dev <-> ram */ 1055 static void ahci_start_transfer(IDEDMA *dma) 1056 { 1057 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1058 IDEState *s = &ad->port.ifs[0]; 1059 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1060 /* write == ram -> device */ 1061 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 1062 int is_write = opts & AHCI_CMD_WRITE; 1063 int is_atapi = opts & AHCI_CMD_ATAPI; 1064 int has_sglist = 0; 1065 1066 if (is_atapi && !ad->done_atapi_packet) { 1067 /* already prepopulated iobuffer */ 1068 ad->done_atapi_packet = true; 1069 goto out; 1070 } 1071 1072 if (!ahci_populate_sglist(ad, &s->sg, 0)) { 1073 has_sglist = 1; 1074 } 1075 1076 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1077 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1078 has_sglist ? "" : "o"); 1079 1080 if (has_sglist && size) { 1081 if (is_write) { 1082 dma_buf_write(s->data_ptr, size, &s->sg); 1083 } else { 1084 dma_buf_read(s->data_ptr, size, &s->sg); 1085 } 1086 } 1087 1088 /* update number of transferred bytes */ 1089 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1090 1091 out: 1092 /* declare that we processed everything */ 1093 s->data_ptr = s->data_end; 1094 1095 if (has_sglist) { 1096 qemu_sglist_destroy(&s->sg); 1097 } 1098 1099 s->end_transfer_func(s); 1100 1101 if (!(s->status & DRQ_STAT)) { 1102 /* done with PIO send/receive */ 1103 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status)); 1104 } 1105 } 1106 1107 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1108 BlockDriverCompletionFunc *dma_cb) 1109 { 1110 #ifdef DEBUG_AHCI 1111 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1112 #endif 1113 DPRINTF(ad->port_no, "\n"); 1114 s->io_buffer_offset = 0; 1115 dma_cb(s, 0); 1116 } 1117 1118 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1119 { 1120 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1121 IDEState *s = &ad->port.ifs[0]; 1122 1123 ahci_populate_sglist(ad, &s->sg, 0); 1124 s->io_buffer_size = s->sg.size; 1125 1126 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1127 return s->io_buffer_size != 0; 1128 } 1129 1130 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1131 { 1132 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1133 IDEState *s = &ad->port.ifs[0]; 1134 uint8_t *p = s->io_buffer + s->io_buffer_index; 1135 int l = s->io_buffer_size - s->io_buffer_index; 1136 1137 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) { 1138 return 0; 1139 } 1140 1141 if (is_write) { 1142 dma_buf_read(p, l, &s->sg); 1143 } else { 1144 dma_buf_write(p, l, &s->sg); 1145 } 1146 1147 /* free sglist that was created in ahci_populate_sglist() */ 1148 qemu_sglist_destroy(&s->sg); 1149 1150 /* update number of transferred bytes */ 1151 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1152 s->io_buffer_index += l; 1153 s->io_buffer_offset += l; 1154 1155 DPRINTF(ad->port_no, "len=%#x\n", l); 1156 1157 return 1; 1158 } 1159 1160 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1161 { 1162 /* only a single unit per link */ 1163 return 0; 1164 } 1165 1166 static void ahci_cmd_done(IDEDMA *dma) 1167 { 1168 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1169 1170 DPRINTF(ad->port_no, "cmd done\n"); 1171 1172 /* update d2h status */ 1173 ahci_write_fis_d2h(ad, NULL); 1174 1175 if (!ad->check_bh) { 1176 /* maybe we still have something to process, check later */ 1177 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1178 qemu_bh_schedule(ad->check_bh); 1179 } 1180 } 1181 1182 static void ahci_irq_set(void *opaque, int n, int level) 1183 { 1184 } 1185 1186 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1187 { 1188 } 1189 1190 static const IDEDMAOps ahci_dma_ops = { 1191 .start_dma = ahci_start_dma, 1192 .start_transfer = ahci_start_transfer, 1193 .prepare_buf = ahci_dma_prepare_buf, 1194 .rw_buf = ahci_dma_rw_buf, 1195 .set_unit = ahci_dma_set_unit, 1196 .cmd_done = ahci_cmd_done, 1197 .restart_cb = ahci_dma_restart_cb, 1198 }; 1199 1200 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1201 { 1202 qemu_irq *irqs; 1203 int i; 1204 1205 s->as = as; 1206 s->ports = ports; 1207 s->dev = g_new0(AHCIDevice, ports); 1208 ahci_reg_init(s); 1209 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1210 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1211 "ahci", AHCI_MEM_BAR_SIZE); 1212 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1213 "ahci-idp", 32); 1214 1215 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1216 1217 for (i = 0; i < s->ports; i++) { 1218 AHCIDevice *ad = &s->dev[i]; 1219 1220 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1221 ide_init2(&ad->port, irqs[i]); 1222 1223 ad->hba = s; 1224 ad->port_no = i; 1225 ad->port.dma = &ad->dma; 1226 ad->port.dma->ops = &ahci_dma_ops; 1227 } 1228 } 1229 1230 void ahci_uninit(AHCIState *s) 1231 { 1232 g_free(s->dev); 1233 } 1234 1235 void ahci_reset(AHCIState *s) 1236 { 1237 AHCIPortRegs *pr; 1238 int i; 1239 1240 s->control_regs.irqstatus = 0; 1241 /* AHCI Enable (AE) 1242 * The implementation of this bit is dependent upon the value of the 1243 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1244 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1245 * read-only and shall have a reset value of '1'. 1246 * 1247 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1248 */ 1249 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1250 1251 for (i = 0; i < s->ports; i++) { 1252 pr = &s->dev[i].port_regs; 1253 pr->irq_stat = 0; 1254 pr->irq_mask = 0; 1255 pr->scr_ctl = 0; 1256 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1257 ahci_reset_port(s, i); 1258 } 1259 } 1260 1261 static const VMStateDescription vmstate_ahci_device = { 1262 .name = "ahci port", 1263 .version_id = 1, 1264 .fields = (VMStateField[]) { 1265 VMSTATE_IDE_BUS(port, AHCIDevice), 1266 VMSTATE_UINT32(port_state, AHCIDevice), 1267 VMSTATE_UINT32(finished, AHCIDevice), 1268 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1269 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1270 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1271 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1272 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1273 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1274 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1275 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1276 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1277 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1278 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1279 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1280 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1281 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1282 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1283 VMSTATE_INT32(busy_slot, AHCIDevice), 1284 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1285 VMSTATE_END_OF_LIST() 1286 }, 1287 }; 1288 1289 static int ahci_state_post_load(void *opaque, int version_id) 1290 { 1291 int i; 1292 struct AHCIDevice *ad; 1293 AHCIState *s = opaque; 1294 1295 for (i = 0; i < s->ports; i++) { 1296 ad = &s->dev[i]; 1297 AHCIPortRegs *pr = &ad->port_regs; 1298 1299 map_page(s->as, &ad->lst, 1300 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 1301 map_page(s->as, &ad->res_fis, 1302 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 1303 /* 1304 * All pending i/o should be flushed out on a migrate. However, 1305 * we might not have cleared the busy_slot since this is done 1306 * in a bh. Also, issue i/o against any slots that are pending. 1307 */ 1308 if ((ad->busy_slot != -1) && 1309 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 1310 pr->cmd_issue &= ~(1 << ad->busy_slot); 1311 ad->busy_slot = -1; 1312 } 1313 check_cmd(s, i); 1314 } 1315 1316 return 0; 1317 } 1318 1319 const VMStateDescription vmstate_ahci = { 1320 .name = "ahci", 1321 .version_id = 1, 1322 .post_load = ahci_state_post_load, 1323 .fields = (VMStateField[]) { 1324 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1325 vmstate_ahci_device, AHCIDevice), 1326 VMSTATE_UINT32(control_regs.cap, AHCIState), 1327 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1328 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1329 VMSTATE_UINT32(control_regs.impl, AHCIState), 1330 VMSTATE_UINT32(control_regs.version, AHCIState), 1331 VMSTATE_UINT32(idp_index, AHCIState), 1332 VMSTATE_INT32_EQUAL(ports, AHCIState), 1333 VMSTATE_END_OF_LIST() 1334 }, 1335 }; 1336 1337 #define TYPE_SYSBUS_AHCI "sysbus-ahci" 1338 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 1339 1340 typedef struct SysbusAHCIState { 1341 /*< private >*/ 1342 SysBusDevice parent_obj; 1343 /*< public >*/ 1344 1345 AHCIState ahci; 1346 uint32_t num_ports; 1347 } SysbusAHCIState; 1348 1349 static const VMStateDescription vmstate_sysbus_ahci = { 1350 .name = "sysbus-ahci", 1351 .unmigratable = 1, /* Still buggy under I/O load */ 1352 .fields = (VMStateField[]) { 1353 VMSTATE_AHCI(ahci, SysbusAHCIState), 1354 VMSTATE_END_OF_LIST() 1355 }, 1356 }; 1357 1358 static void sysbus_ahci_reset(DeviceState *dev) 1359 { 1360 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1361 1362 ahci_reset(&s->ahci); 1363 } 1364 1365 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1366 { 1367 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1368 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1369 1370 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports); 1371 1372 sysbus_init_mmio(sbd, &s->ahci.mem); 1373 sysbus_init_irq(sbd, &s->ahci.irq); 1374 } 1375 1376 static Property sysbus_ahci_properties[] = { 1377 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1378 DEFINE_PROP_END_OF_LIST(), 1379 }; 1380 1381 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1382 { 1383 DeviceClass *dc = DEVICE_CLASS(klass); 1384 1385 dc->realize = sysbus_ahci_realize; 1386 dc->vmsd = &vmstate_sysbus_ahci; 1387 dc->props = sysbus_ahci_properties; 1388 dc->reset = sysbus_ahci_reset; 1389 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1390 } 1391 1392 static const TypeInfo sysbus_ahci_info = { 1393 .name = TYPE_SYSBUS_AHCI, 1394 .parent = TYPE_SYS_BUS_DEVICE, 1395 .instance_size = sizeof(SysbusAHCIState), 1396 .class_init = sysbus_ahci_class_init, 1397 }; 1398 1399 static void sysbus_ahci_register_types(void) 1400 { 1401 type_register_static(&sysbus_ahci_info); 1402 } 1403 1404 type_init(sysbus_ahci_register_types) 1405