1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/irq.h" 26 #include "hw/qdev-properties.h" 27 #include "migration/vmstate.h" 28 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "qemu/main-loop.h" 32 #include "qemu/module.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/dma.h" 35 #include "hw/ide/ahci-sysbus.h" 36 #include "ahci-internal.h" 37 #include "ide-internal.h" 38 39 #include "trace.h" 40 41 static void check_cmd(AHCIState *s, int port); 42 static void handle_cmd(AHCIState *s, int port, uint8_t slot); 43 static void ahci_reset_port(AHCIState *s, int port); 44 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); 45 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); 46 static void ahci_init_d2h(AHCIDevice *ad); 47 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); 48 static bool ahci_map_clb_address(AHCIDevice *ad); 49 static bool ahci_map_fis_address(AHCIDevice *ad); 50 static void ahci_unmap_clb_address(AHCIDevice *ad); 51 static void ahci_unmap_fis_address(AHCIDevice *ad); 52 53 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { 54 [AHCI_HOST_REG_CAP] = "CAP", 55 [AHCI_HOST_REG_CTL] = "GHC", 56 [AHCI_HOST_REG_IRQ_STAT] = "IS", 57 [AHCI_HOST_REG_PORTS_IMPL] = "PI", 58 [AHCI_HOST_REG_VERSION] = "VS", 59 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", 60 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", 61 [AHCI_HOST_REG_EM_LOC] = "EM_LOC", 62 [AHCI_HOST_REG_EM_CTL] = "EM_CTL", 63 [AHCI_HOST_REG_CAP2] = "CAP2", 64 [AHCI_HOST_REG_BOHC] = "BOHC", 65 }; 66 67 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { 68 [AHCI_PORT_REG_LST_ADDR] = "PxCLB", 69 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", 70 [AHCI_PORT_REG_FIS_ADDR] = "PxFB", 71 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", 72 [AHCI_PORT_REG_IRQ_STAT] = "PxIS", 73 [AHCI_PORT_REG_IRQ_MASK] = "PXIE", 74 [AHCI_PORT_REG_CMD] = "PxCMD", 75 [7] = "Reserved", 76 [AHCI_PORT_REG_TFDATA] = "PxTFD", 77 [AHCI_PORT_REG_SIG] = "PxSIG", 78 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", 79 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", 80 [AHCI_PORT_REG_SCR_ERR] = "PxSERR", 81 [AHCI_PORT_REG_SCR_ACT] = "PxSACT", 82 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", 83 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", 84 [AHCI_PORT_REG_FIS_CTL] = "PxFBS", 85 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", 86 [18 ... 27] = "Reserved", 87 [AHCI_PORT_REG_VENDOR_1 ... 88 AHCI_PORT_REG_VENDOR_4] = "PxVS", 89 }; 90 91 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { 92 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", 93 [AHCI_PORT_IRQ_BIT_PSS] = "PSS", 94 [AHCI_PORT_IRQ_BIT_DSS] = "DSS", 95 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", 96 [AHCI_PORT_IRQ_BIT_UFS] = "UFS", 97 [AHCI_PORT_IRQ_BIT_DPS] = "DPS", 98 [AHCI_PORT_IRQ_BIT_PCS] = "PCS", 99 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", 100 [8 ... 21] = "RESERVED", 101 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", 102 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", 103 [AHCI_PORT_IRQ_BIT_OFS] = "OFS", 104 [25] = "RESERVED", 105 [AHCI_PORT_IRQ_BIT_INFS] = "INFS", 106 [AHCI_PORT_IRQ_BIT_IFS] = "IFS", 107 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", 108 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", 109 [AHCI_PORT_IRQ_BIT_TFES] = "TFES", 110 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" 111 }; 112 113 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 114 { 115 uint32_t val; 116 AHCIPortRegs *pr = &s->dev[port].port_regs; 117 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 118 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 119 120 switch (regnum) { 121 case AHCI_PORT_REG_LST_ADDR: 122 val = pr->lst_addr; 123 break; 124 case AHCI_PORT_REG_LST_ADDR_HI: 125 val = pr->lst_addr_hi; 126 break; 127 case AHCI_PORT_REG_FIS_ADDR: 128 val = pr->fis_addr; 129 break; 130 case AHCI_PORT_REG_FIS_ADDR_HI: 131 val = pr->fis_addr_hi; 132 break; 133 case AHCI_PORT_REG_IRQ_STAT: 134 val = pr->irq_stat; 135 break; 136 case AHCI_PORT_REG_IRQ_MASK: 137 val = pr->irq_mask; 138 break; 139 case AHCI_PORT_REG_CMD: 140 val = pr->cmd; 141 break; 142 case AHCI_PORT_REG_TFDATA: 143 val = pr->tfdata; 144 break; 145 case AHCI_PORT_REG_SIG: 146 val = pr->sig; 147 break; 148 case AHCI_PORT_REG_SCR_STAT: 149 if (s->dev[port].port.ifs[0].blk) { 150 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 151 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 152 } else { 153 val = SATA_SCR_SSTATUS_DET_NODEV; 154 } 155 break; 156 case AHCI_PORT_REG_SCR_CTL: 157 val = pr->scr_ctl; 158 break; 159 case AHCI_PORT_REG_SCR_ERR: 160 val = pr->scr_err; 161 break; 162 case AHCI_PORT_REG_SCR_ACT: 163 val = pr->scr_act; 164 break; 165 case AHCI_PORT_REG_CMD_ISSUE: 166 val = pr->cmd_issue; 167 break; 168 default: 169 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], 170 offset); 171 val = 0; 172 } 173 174 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); 175 return val; 176 } 177 178 static void ahci_check_irq(AHCIState *s) 179 { 180 int i; 181 uint32_t old_irq = s->control_regs.irqstatus; 182 183 s->control_regs.irqstatus = 0; 184 for (i = 0; i < s->ports; i++) { 185 AHCIPortRegs *pr = &s->dev[i].port_regs; 186 if (pr->irq_stat & pr->irq_mask) { 187 s->control_regs.irqstatus |= (1 << i); 188 } 189 } 190 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); 191 if (s->control_regs.irqstatus && 192 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 193 trace_ahci_irq_raise(s); 194 qemu_irq_raise(s->irq); 195 } else { 196 trace_ahci_irq_lower(s); 197 qemu_irq_lower(s->irq); 198 } 199 } 200 201 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 202 enum AHCIPortIRQ irqbit) 203 { 204 g_assert((unsigned)irqbit < 32); 205 uint32_t irq = 1U << irqbit; 206 uint32_t irqstat = d->port_regs.irq_stat | irq; 207 208 trace_ahci_trigger_irq(s, d->port_no, 209 AHCIPortIRQ_lookup[irqbit], irq, 210 d->port_regs.irq_stat, irqstat, 211 irqstat & d->port_regs.irq_mask); 212 213 d->port_regs.irq_stat = irqstat; 214 ahci_check_irq(s); 215 } 216 217 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 218 uint32_t wanted) 219 { 220 hwaddr len = wanted; 221 222 if (*ptr) { 223 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 224 } 225 226 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, 227 MEMTXATTRS_UNSPECIFIED); 228 if (len < wanted && *ptr) { 229 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 230 *ptr = NULL; 231 } 232 } 233 234 /** 235 * Check the cmd register to see if we should start or stop 236 * the DMA or FIS RX engines. 237 * 238 * @ad: Device to dis/engage. 239 * 240 * @return 0 on success, -1 on error. 241 */ 242 static int ahci_cond_start_engines(AHCIDevice *ad) 243 { 244 AHCIPortRegs *pr = &ad->port_regs; 245 bool cmd_start = pr->cmd & PORT_CMD_START; 246 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; 247 bool fis_start = pr->cmd & PORT_CMD_FIS_RX; 248 bool fis_on = pr->cmd & PORT_CMD_FIS_ON; 249 250 if (cmd_start && !cmd_on) { 251 if (!ahci_map_clb_address(ad)) { 252 pr->cmd &= ~PORT_CMD_START; 253 error_report("AHCI: Failed to start DMA engine: " 254 "bad command list buffer address"); 255 return -1; 256 } 257 } else if (!cmd_start && cmd_on) { 258 ahci_unmap_clb_address(ad); 259 } 260 261 if (fis_start && !fis_on) { 262 if (!ahci_map_fis_address(ad)) { 263 pr->cmd &= ~PORT_CMD_FIS_RX; 264 error_report("AHCI: Failed to start FIS receive engine: " 265 "bad FIS receive buffer address"); 266 return -1; 267 } 268 } else if (!fis_start && fis_on) { 269 ahci_unmap_fis_address(ad); 270 } 271 272 return 0; 273 } 274 275 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 276 { 277 AHCIPortRegs *pr = &s->dev[port].port_regs; 278 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 279 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 280 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); 281 282 switch (regnum) { 283 case AHCI_PORT_REG_LST_ADDR: 284 pr->lst_addr = val; 285 break; 286 case AHCI_PORT_REG_LST_ADDR_HI: 287 pr->lst_addr_hi = val; 288 break; 289 case AHCI_PORT_REG_FIS_ADDR: 290 pr->fis_addr = val; 291 break; 292 case AHCI_PORT_REG_FIS_ADDR_HI: 293 pr->fis_addr_hi = val; 294 break; 295 case AHCI_PORT_REG_IRQ_STAT: 296 pr->irq_stat &= ~val; 297 ahci_check_irq(s); 298 break; 299 case AHCI_PORT_REG_IRQ_MASK: 300 pr->irq_mask = val & 0xfdc000ff; 301 ahci_check_irq(s); 302 break; 303 case AHCI_PORT_REG_CMD: 304 if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { 305 pr->scr_act = 0; 306 pr->cmd_issue = 0; 307 } 308 309 /* Block any Read-only fields from being set; 310 * including LIST_ON and FIS_ON. 311 * The spec requires to set ICC bits to zero after the ICC change 312 * is done. We don't support ICC state changes, therefore always 313 * force the ICC bits to zero. 314 */ 315 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 316 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); 317 318 /* Check FIS RX and CLB engines */ 319 ahci_cond_start_engines(&s->dev[port]); 320 321 /* XXX usually the FIS would be pending on the bus here and 322 issuing deferred until the OS enables FIS receival. 323 Instead, we only submit it once - which works in most 324 cases, but is a hack. */ 325 if ((pr->cmd & PORT_CMD_FIS_ON) && 326 !s->dev[port].init_d2h_sent) { 327 ahci_init_d2h(&s->dev[port]); 328 } 329 330 check_cmd(s, port); 331 break; 332 case AHCI_PORT_REG_TFDATA: 333 case AHCI_PORT_REG_SIG: 334 case AHCI_PORT_REG_SCR_STAT: 335 /* Read Only */ 336 break; 337 case AHCI_PORT_REG_SCR_CTL: 338 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 339 ((val & AHCI_SCR_SCTL_DET) == 0)) { 340 ahci_reset_port(s, port); 341 } 342 pr->scr_ctl = val; 343 break; 344 case AHCI_PORT_REG_SCR_ERR: 345 pr->scr_err &= ~val; 346 break; 347 case AHCI_PORT_REG_SCR_ACT: 348 /* RW1 */ 349 pr->scr_act |= val; 350 break; 351 case AHCI_PORT_REG_CMD_ISSUE: 352 pr->cmd_issue |= val; 353 check_cmd(s, port); 354 break; 355 default: 356 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], 357 offset, val); 358 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 359 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, 360 port, AHCIPortReg_lookup[regnum], offset, val); 361 break; 362 } 363 } 364 365 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 366 { 367 AHCIState *s = opaque; 368 uint32_t val = 0; 369 370 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 371 enum AHCIHostReg regnum = addr / 4; 372 assert(regnum < AHCI_HOST_REG__COUNT); 373 374 switch (regnum) { 375 case AHCI_HOST_REG_CAP: 376 val = s->control_regs.cap; 377 break; 378 case AHCI_HOST_REG_CTL: 379 val = s->control_regs.ghc; 380 break; 381 case AHCI_HOST_REG_IRQ_STAT: 382 val = s->control_regs.irqstatus; 383 break; 384 case AHCI_HOST_REG_PORTS_IMPL: 385 val = s->control_regs.impl; 386 break; 387 case AHCI_HOST_REG_VERSION: 388 val = s->control_regs.version; 389 break; 390 default: 391 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], 392 addr); 393 } 394 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); 395 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 396 (addr < (AHCI_PORT_REGS_START_ADDR + 397 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 398 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 399 addr & AHCI_PORT_ADDR_OFFSET_MASK); 400 } else { 401 trace_ahci_mem_read_32_default(s, addr, val); 402 } 403 404 trace_ahci_mem_read_32(s, addr, val); 405 return val; 406 } 407 408 409 /** 410 * AHCI 1.3 section 3 ("HBA Memory Registers") 411 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 412 * Caller is responsible for masking unwanted higher order bytes. 413 */ 414 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 415 { 416 hwaddr aligned = addr & ~0x3; 417 int ofst = addr - aligned; 418 uint64_t lo = ahci_mem_read_32(opaque, aligned); 419 uint64_t hi; 420 uint64_t val; 421 422 /* if < 8 byte read does not cross 4 byte boundary */ 423 if (ofst + size <= 4) { 424 val = lo >> (ofst * 8); 425 } else { 426 g_assert(size > 1); 427 428 /* If the 64bit read is unaligned, we will produce undefined 429 * results. AHCI does not support unaligned 64bit reads. */ 430 hi = ahci_mem_read_32(opaque, aligned + 4); 431 val = (hi << 32 | lo) >> (ofst * 8); 432 } 433 434 trace_ahci_mem_read(opaque, size, addr, val); 435 return val; 436 } 437 438 439 static void ahci_mem_write(void *opaque, hwaddr addr, 440 uint64_t val, unsigned size) 441 { 442 AHCIState *s = opaque; 443 444 trace_ahci_mem_write(s, size, addr, val); 445 446 /* Only aligned reads are allowed on AHCI */ 447 if (addr & 3) { 448 qemu_log_mask(LOG_GUEST_ERROR, 449 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", 450 addr); 451 return; 452 } 453 454 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 455 enum AHCIHostReg regnum = addr / 4; 456 assert(regnum < AHCI_HOST_REG__COUNT); 457 458 switch (regnum) { 459 case AHCI_HOST_REG_CAP: /* R/WO, RO */ 460 /* FIXME handle R/WO */ 461 break; 462 case AHCI_HOST_REG_CTL: /* R/W */ 463 if (val & HOST_CTL_RESET) { 464 ahci_reset(s); 465 } else { 466 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 467 ahci_check_irq(s); 468 } 469 break; 470 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ 471 s->control_regs.irqstatus &= ~val; 472 ahci_check_irq(s); 473 break; 474 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ 475 /* FIXME handle R/WO */ 476 break; 477 case AHCI_HOST_REG_VERSION: /* RO */ 478 /* FIXME report write? */ 479 break; 480 default: 481 qemu_log_mask(LOG_UNIMP, 482 "Attempted write to unimplemented register: " 483 "AHCI host register %s, " 484 "offset 0x%"PRIx64": 0x%"PRIx64, 485 AHCIHostReg_lookup[regnum], addr, val); 486 trace_ahci_mem_write_host_unimpl(s, size, 487 AHCIHostReg_lookup[regnum], addr); 488 } 489 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], 490 addr, val); 491 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 492 (addr < (AHCI_PORT_REGS_START_ADDR + 493 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 494 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 495 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 496 } else { 497 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 498 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, 499 addr, val); 500 trace_ahci_mem_write_unimpl(s, size, addr, val); 501 } 502 } 503 504 static const MemoryRegionOps ahci_mem_ops = { 505 .read = ahci_mem_read, 506 .write = ahci_mem_write, 507 .endianness = DEVICE_LITTLE_ENDIAN, 508 }; 509 510 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 511 unsigned size) 512 { 513 AHCIState *s = opaque; 514 515 if (addr == s->idp_offset) { 516 /* index register */ 517 return s->idp_index; 518 } else if (addr == s->idp_offset + 4) { 519 /* data register - do memory read at location selected by index */ 520 return ahci_mem_read(opaque, s->idp_index, size); 521 } else { 522 return 0; 523 } 524 } 525 526 static void ahci_idp_write(void *opaque, hwaddr addr, 527 uint64_t val, unsigned size) 528 { 529 AHCIState *s = opaque; 530 531 if (addr == s->idp_offset) { 532 /* index register - mask off reserved bits */ 533 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 534 } else if (addr == s->idp_offset + 4) { 535 /* data register - do memory write at location selected by index */ 536 ahci_mem_write(opaque, s->idp_index, val, size); 537 } 538 } 539 540 static const MemoryRegionOps ahci_idp_ops = { 541 .read = ahci_idp_read, 542 .write = ahci_idp_write, 543 .endianness = DEVICE_LITTLE_ENDIAN, 544 }; 545 546 547 static void ahci_reg_init(AHCIState *s) 548 { 549 int i; 550 551 s->control_regs.cap = (s->ports - 1) | 552 (AHCI_NUM_COMMAND_SLOTS << 8) | 553 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 554 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; 555 556 s->control_regs.impl = (1 << s->ports) - 1; 557 558 s->control_regs.version = AHCI_VERSION_1_0; 559 560 for (i = 0; i < s->ports; i++) { 561 s->dev[i].port_state = STATE_RUN; 562 } 563 } 564 565 static void check_cmd(AHCIState *s, int port) 566 { 567 AHCIPortRegs *pr = &s->dev[port].port_regs; 568 uint8_t slot; 569 570 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 571 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 572 if (pr->cmd_issue & (1U << slot)) { 573 handle_cmd(s, port, slot); 574 } 575 } 576 } 577 } 578 579 static void ahci_check_cmd_bh(void *opaque) 580 { 581 AHCIDevice *ad = opaque; 582 583 qemu_bh_delete(ad->check_bh); 584 ad->check_bh = NULL; 585 586 check_cmd(ad->hba, ad->port_no); 587 } 588 589 static void ahci_init_d2h(AHCIDevice *ad) 590 { 591 IDEState *ide_state = &ad->port.ifs[0]; 592 AHCIPortRegs *pr = &ad->port_regs; 593 594 if (ad->init_d2h_sent) { 595 return; 596 } 597 598 /* 599 * For simplicity, do not call ahci_clear_cmd_issue() for this 600 * ahci_write_fis_d2h(). (The reset value for PxCI is 0.) 601 */ 602 if (ahci_write_fis_d2h(ad, true)) { 603 ad->init_d2h_sent = true; 604 /* We're emulating receiving the first Reg D2H FIS from the device; 605 * Update the SIG register, but otherwise proceed as normal. */ 606 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 607 (ide_state->lcyl << 16) | 608 (ide_state->sector << 8) | 609 (ide_state->nsector & 0xFF); 610 } 611 } 612 613 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 614 { 615 IDEState *s = &ad->port.ifs[0]; 616 s->hcyl = sig >> 24 & 0xFF; 617 s->lcyl = sig >> 16 & 0xFF; 618 s->sector = sig >> 8 & 0xFF; 619 s->nsector = sig & 0xFF; 620 621 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, 622 s->lcyl, s->hcyl, sig); 623 } 624 625 static void ahci_reset_port(AHCIState *s, int port) 626 { 627 AHCIDevice *d = &s->dev[port]; 628 AHCIPortRegs *pr = &d->port_regs; 629 IDEState *ide_state = &d->port.ifs[0]; 630 int i; 631 632 trace_ahci_reset_port(s, port); 633 634 ide_bus_reset(&d->port); 635 ide_state->ncq_queues = AHCI_MAX_CMDS; 636 637 pr->scr_stat = 0; 638 pr->scr_err = 0; 639 pr->scr_act = 0; 640 pr->tfdata = 0x7F; 641 pr->sig = 0xFFFFFFFF; 642 pr->cmd_issue = 0; 643 d->busy_slot = -1; 644 d->init_d2h_sent = false; 645 646 ide_state = &s->dev[port].port.ifs[0]; 647 if (!ide_state->blk) { 648 return; 649 } 650 651 /* reset ncq queue */ 652 for (i = 0; i < AHCI_MAX_CMDS; i++) { 653 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 654 ncq_tfs->halt = false; 655 if (!ncq_tfs->used) { 656 continue; 657 } 658 659 if (ncq_tfs->aiocb) { 660 blk_aio_cancel(ncq_tfs->aiocb); 661 ncq_tfs->aiocb = NULL; 662 } 663 664 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 665 if (!ncq_tfs->used) { 666 continue; 667 } 668 669 qemu_sglist_destroy(&ncq_tfs->sglist); 670 ncq_tfs->used = 0; 671 } 672 673 s->dev[port].port_state = STATE_RUN; 674 if (ide_state->drive_kind == IDE_CD) { 675 ahci_set_signature(d, SATA_SIGNATURE_CDROM); 676 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 677 } else { 678 ahci_set_signature(d, SATA_SIGNATURE_DISK); 679 ide_state->status = SEEK_STAT | WRERR_STAT; 680 } 681 682 ide_state->error = 1; 683 ahci_init_d2h(d); 684 } 685 686 /* Buffer pretty output based on a raw FIS structure. */ 687 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) 688 { 689 int i; 690 GString *s = g_string_new("FIS:"); 691 692 for (i = 0; i < cmd_len; i++) { 693 if ((i & 0xf) == 0) { 694 g_string_append_printf(s, "\n0x%02x: ", i); 695 } 696 g_string_append_printf(s, "%02x ", fis[i]); 697 } 698 g_string_append_c(s, '\n'); 699 700 return g_string_free(s, FALSE); 701 } 702 703 static bool ahci_map_fis_address(AHCIDevice *ad) 704 { 705 AHCIPortRegs *pr = &ad->port_regs; 706 map_page(ad->hba->as, &ad->res_fis, 707 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 708 if (ad->res_fis != NULL) { 709 pr->cmd |= PORT_CMD_FIS_ON; 710 return true; 711 } 712 713 pr->cmd &= ~PORT_CMD_FIS_ON; 714 return false; 715 } 716 717 static void ahci_unmap_fis_address(AHCIDevice *ad) 718 { 719 if (ad->res_fis == NULL) { 720 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); 721 return; 722 } 723 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; 724 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 725 DMA_DIRECTION_FROM_DEVICE, 256); 726 ad->res_fis = NULL; 727 } 728 729 static bool ahci_map_clb_address(AHCIDevice *ad) 730 { 731 AHCIPortRegs *pr = &ad->port_regs; 732 ad->cur_cmd = NULL; 733 map_page(ad->hba->as, &ad->lst, 734 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 735 if (ad->lst != NULL) { 736 pr->cmd |= PORT_CMD_LIST_ON; 737 return true; 738 } 739 740 pr->cmd &= ~PORT_CMD_LIST_ON; 741 return false; 742 } 743 744 static void ahci_unmap_clb_address(AHCIDevice *ad) 745 { 746 if (ad->lst == NULL) { 747 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); 748 return; 749 } 750 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; 751 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 752 DMA_DIRECTION_FROM_DEVICE, 1024); 753 ad->lst = NULL; 754 } 755 756 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 757 { 758 AHCIDevice *ad = ncq_tfs->drive; 759 AHCIPortRegs *pr = &ad->port_regs; 760 IDEState *ide_state; 761 SDBFIS *sdb_fis; 762 763 if (!ad->res_fis || 764 !(pr->cmd & PORT_CMD_FIS_RX)) { 765 return; 766 } 767 768 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 769 ide_state = &ad->port.ifs[0]; 770 771 sdb_fis->type = SATA_FIS_TYPE_SDB; 772 /* Interrupt pending & Notification bit */ 773 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 774 sdb_fis->status = ide_state->status & 0x77; 775 sdb_fis->error = ide_state->error; 776 /* update SAct field in SDB_FIS */ 777 sdb_fis->payload = cpu_to_le32(ad->finished); 778 779 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 780 pr->tfdata = (ad->port.ifs[0].error << 8) | 781 (ad->port.ifs[0].status & 0x77) | 782 (pr->tfdata & 0x88); 783 pr->scr_act &= ~ad->finished; 784 ad->finished = 0; 785 786 /* 787 * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. 788 * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set 789 * (which currently, it always is). 790 */ 791 if (sdb_fis->status & ERR_STAT) { 792 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES); 793 } else if (sdb_fis->flags & 0x40) { 794 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); 795 } 796 } 797 798 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) 799 { 800 AHCIPortRegs *pr = &ad->port_regs; 801 uint8_t *pio_fis; 802 IDEState *s = &ad->port.ifs[0]; 803 804 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 805 return; 806 } 807 808 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 809 810 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 811 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); 812 pio_fis[2] = s->status; 813 pio_fis[3] = s->error; 814 815 pio_fis[4] = s->sector; 816 pio_fis[5] = s->lcyl; 817 pio_fis[6] = s->hcyl; 818 pio_fis[7] = s->select; 819 pio_fis[8] = s->hob_sector; 820 pio_fis[9] = s->hob_lcyl; 821 pio_fis[10] = s->hob_hcyl; 822 pio_fis[11] = 0; 823 pio_fis[12] = s->nsector & 0xFF; 824 pio_fis[13] = (s->nsector >> 8) & 0xFF; 825 pio_fis[14] = 0; 826 pio_fis[15] = s->status; 827 pio_fis[16] = len & 255; 828 pio_fis[17] = len >> 8; 829 pio_fis[18] = 0; 830 pio_fis[19] = 0; 831 832 /* Update shadow registers: */ 833 pr->tfdata = (ad->port.ifs[0].error << 8) | 834 ad->port.ifs[0].status; 835 836 if (pio_fis[2] & ERR_STAT) { 837 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 838 } 839 } 840 841 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) 842 { 843 AHCIPortRegs *pr = &ad->port_regs; 844 uint8_t *d2h_fis; 845 int i; 846 IDEState *s = &ad->port.ifs[0]; 847 848 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 849 return false; 850 } 851 852 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 853 854 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 855 d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ 856 d2h_fis[2] = s->status; 857 d2h_fis[3] = s->error; 858 859 d2h_fis[4] = s->sector; 860 d2h_fis[5] = s->lcyl; 861 d2h_fis[6] = s->hcyl; 862 d2h_fis[7] = s->select; 863 d2h_fis[8] = s->hob_sector; 864 d2h_fis[9] = s->hob_lcyl; 865 d2h_fis[10] = s->hob_hcyl; 866 d2h_fis[11] = 0; 867 d2h_fis[12] = s->nsector & 0xFF; 868 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 869 for (i = 14; i < 20; i++) { 870 d2h_fis[i] = 0; 871 } 872 873 /* Update shadow registers: */ 874 pr->tfdata = (ad->port.ifs[0].error << 8) | 875 ad->port.ifs[0].status; 876 877 /* TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. */ 878 if (d2h_fis[2] & ERR_STAT) { 879 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 880 } else if (d2h_fis_i) { 881 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); 882 } 883 884 return true; 885 } 886 887 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 888 { 889 /* flags_size is zero-based */ 890 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 891 } 892 893 /** 894 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 895 * @ad: The AHCIDevice for whom we are building the SGList. 896 * @sglist: The SGList target to add PRD entries to. 897 * @cmd: The AHCI Command Header that describes where the PRDT is. 898 * @limit: The remaining size of the S/ATA transaction, in bytes. 899 * @offset: The number of bytes already transferred, in bytes. 900 * 901 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 902 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 903 * building the sglist from the PRDT as soon as we hit @limit bytes, 904 * which is <= INT32_MAX/2GiB. 905 */ 906 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 907 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 908 { 909 uint16_t opts = le16_to_cpu(cmd->opts); 910 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 911 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 912 uint64_t prdt_addr = cfis_addr + 0x80; 913 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 914 dma_addr_t real_prdt_len = prdt_len; 915 uint8_t *prdt; 916 int i; 917 int r = 0; 918 uint64_t sum = 0; 919 int off_idx = -1; 920 int64_t off_pos = -1; 921 IDEBus *bus = &ad->port; 922 BusState *qbus = BUS(bus); 923 924 trace_ahci_populate_sglist(ad->hba, ad->port_no); 925 926 if (!prdtl) { 927 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); 928 return -1; 929 } 930 931 /* map PRDT */ 932 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 933 DMA_DIRECTION_TO_DEVICE, 934 MEMTXATTRS_UNSPECIFIED))){ 935 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); 936 return -1; 937 } 938 939 if (prdt_len < real_prdt_len) { 940 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); 941 r = -1; 942 goto out; 943 } 944 945 /* Get entries in the PRDT, init a qemu sglist accordingly */ 946 if (prdtl > 0) { 947 AHCI_SG *tbl = (AHCI_SG *)prdt; 948 int tbl_entry_size = 0; 949 950 sum = 0; 951 for (i = 0; i < prdtl; i++) { 952 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 953 if (offset < (sum + tbl_entry_size)) { 954 off_idx = i; 955 off_pos = offset - sum; 956 break; 957 } 958 sum += tbl_entry_size; 959 } 960 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 961 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, 962 off_idx, off_pos); 963 r = -1; 964 goto out; 965 } 966 967 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 968 ad->hba->as); 969 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 970 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 971 limit)); 972 973 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 974 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 975 MIN(prdt_tbl_entry_size(&tbl[i]), 976 limit - sglist->size)); 977 } 978 } 979 980 out: 981 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 982 DMA_DIRECTION_TO_DEVICE, prdt_len); 983 return r; 984 } 985 986 static void ncq_err(NCQTransferState *ncq_tfs) 987 { 988 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 989 990 ide_state->error = ABRT_ERR; 991 ide_state->status = READY_STAT | ERR_STAT; 992 qemu_sglist_destroy(&ncq_tfs->sglist); 993 ncq_tfs->used = 0; 994 } 995 996 static void ncq_finish(NCQTransferState *ncq_tfs) 997 { 998 /* If we didn't error out, set our finished bit. Errored commands 999 * do not get a bit set for the SDB FIS ACT register, nor do they 1000 * clear the outstanding bit in scr_act (PxSACT). */ 1001 if (ncq_tfs->used) { 1002 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 1003 } 1004 1005 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 1006 1007 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 1008 ncq_tfs->tag); 1009 1010 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 1011 &ncq_tfs->acct); 1012 qemu_sglist_destroy(&ncq_tfs->sglist); 1013 ncq_tfs->used = 0; 1014 } 1015 1016 static void ncq_cb(void *opaque, int ret) 1017 { 1018 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 1019 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1020 1021 ncq_tfs->aiocb = NULL; 1022 1023 if (ret < 0) { 1024 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 1025 BlockErrorAction action = blk_get_error_action(ide_state->blk, 1026 is_read, -ret); 1027 if (action == BLOCK_ERROR_ACTION_STOP) { 1028 ncq_tfs->halt = true; 1029 ide_state->bus->error_status = IDE_RETRY_HBA; 1030 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 1031 ncq_err(ncq_tfs); 1032 } 1033 blk_error_action(ide_state->blk, action, is_read, -ret); 1034 } else { 1035 ide_state->status = READY_STAT | SEEK_STAT; 1036 } 1037 1038 if (!ncq_tfs->halt) { 1039 ncq_finish(ncq_tfs); 1040 } 1041 } 1042 1043 static int is_ncq(uint8_t ata_cmd) 1044 { 1045 /* Based on SATA 3.2 section 13.6.3.2 */ 1046 switch (ata_cmd) { 1047 case READ_FPDMA_QUEUED: 1048 case WRITE_FPDMA_QUEUED: 1049 case NCQ_NON_DATA: 1050 case RECEIVE_FPDMA_QUEUED: 1051 case SEND_FPDMA_QUEUED: 1052 return 1; 1053 default: 1054 return 0; 1055 } 1056 } 1057 1058 static void execute_ncq_command(NCQTransferState *ncq_tfs) 1059 { 1060 AHCIDevice *ad = ncq_tfs->drive; 1061 IDEState *ide_state = &ad->port.ifs[0]; 1062 int port = ad->port_no; 1063 1064 g_assert(is_ncq(ncq_tfs->cmd)); 1065 ncq_tfs->halt = false; 1066 1067 switch (ncq_tfs->cmd) { 1068 case READ_FPDMA_QUEUED: 1069 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1070 ncq_tfs->sector_count, ncq_tfs->lba); 1071 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1072 &ncq_tfs->sglist, BLOCK_ACCT_READ); 1073 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1074 ncq_tfs->lba << BDRV_SECTOR_BITS, 1075 BDRV_SECTOR_SIZE, 1076 ncq_cb, ncq_tfs); 1077 break; 1078 case WRITE_FPDMA_QUEUED: 1079 trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag, 1080 ncq_tfs->sector_count, ncq_tfs->lba); 1081 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1082 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1083 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1084 ncq_tfs->lba << BDRV_SECTOR_BITS, 1085 BDRV_SECTOR_SIZE, 1086 ncq_cb, ncq_tfs); 1087 break; 1088 default: 1089 trace_execute_ncq_command_unsup(ad->hba, port, 1090 ncq_tfs->tag, ncq_tfs->cmd); 1091 ncq_err(ncq_tfs); 1092 } 1093 } 1094 1095 1096 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, 1097 uint8_t slot) 1098 { 1099 AHCIDevice *ad = &s->dev[port]; 1100 const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; 1101 uint8_t tag = ncq_fis->tag >> 3; 1102 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1103 size_t size; 1104 1105 g_assert(is_ncq(ncq_fis->command)); 1106 if (ncq_tfs->used) { 1107 /* error - already in use */ 1108 qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", 1109 __func__, tag); 1110 return; 1111 } 1112 1113 /* 1114 * A NCQ command clears the bit in PxCI after the command has been QUEUED 1115 * successfully (ERROR not set, BUSY and DRQ cleared). 1116 * 1117 * For NCQ commands, PxCI will always be cleared here. 1118 * 1119 * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with 1120 * the interrupt bit set, which will clear PxSACT and raise an interrupt.) 1121 */ 1122 ahci_clear_cmd_issue(ad, slot); 1123 1124 /* 1125 * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS 1126 * without the interrupt bit set, but since ahci_write_fis_d2h() can raise 1127 * an IRQ on error, we need to call them in reverse order. 1128 */ 1129 ahci_write_fis_d2h(ad, false); 1130 1131 ncq_tfs->used = 1; 1132 ncq_tfs->drive = ad; 1133 ncq_tfs->slot = slot; 1134 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1135 ncq_tfs->cmd = ncq_fis->command; 1136 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1137 ((uint64_t)ncq_fis->lba4 << 32) | 1138 ((uint64_t)ncq_fis->lba3 << 24) | 1139 ((uint64_t)ncq_fis->lba2 << 16) | 1140 ((uint64_t)ncq_fis->lba1 << 8) | 1141 (uint64_t)ncq_fis->lba0; 1142 ncq_tfs->tag = tag; 1143 1144 /* Sanity-check the NCQ packet */ 1145 if (tag != slot) { 1146 trace_process_ncq_command_mismatch(s, port, tag, slot); 1147 } 1148 1149 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1150 trace_process_ncq_command_aux(s, port, tag); 1151 } 1152 if (ncq_fis->prio || ncq_fis->icc) { 1153 trace_process_ncq_command_prioicc(s, port, tag); 1154 } 1155 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1156 trace_process_ncq_command_fua(s, port, tag); 1157 } 1158 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1159 trace_process_ncq_command_rarc(s, port, tag); 1160 } 1161 1162 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1163 ncq_fis->sector_count_low); 1164 if (!ncq_tfs->sector_count) { 1165 ncq_tfs->sector_count = 0x10000; 1166 } 1167 size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; 1168 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1169 1170 if (ncq_tfs->sglist.size < size) { 1171 error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") " 1172 "is smaller than the requested size (0x%zx)", 1173 ncq_tfs->sglist.size, size); 1174 ncq_err(ncq_tfs); 1175 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); 1176 return; 1177 } else if (ncq_tfs->sglist.size != size) { 1178 trace_process_ncq_command_large(s, port, tag, 1179 ncq_tfs->sglist.size, size); 1180 } 1181 1182 trace_process_ncq_command(s, port, tag, 1183 ncq_fis->command, 1184 ncq_tfs->lba, 1185 ncq_tfs->lba + ncq_tfs->sector_count - 1); 1186 execute_ncq_command(ncq_tfs); 1187 } 1188 1189 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1190 { 1191 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1192 return NULL; 1193 } 1194 1195 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1196 } 1197 1198 static void handle_reg_h2d_fis(AHCIState *s, int port, 1199 uint8_t slot, const uint8_t *cmd_fis) 1200 { 1201 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1202 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1203 AHCIDevice *ad = &s->dev[port]; 1204 uint16_t opts = le16_to_cpu(cmd->opts); 1205 1206 if (cmd_fis[1] & 0x0F) { 1207 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], 1208 cmd_fis[2], cmd_fis[3]); 1209 return; 1210 } 1211 1212 if (cmd_fis[1] & 0x70) { 1213 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], 1214 cmd_fis[2], cmd_fis[3]); 1215 return; 1216 } 1217 1218 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1219 switch (s->dev[port].port_state) { 1220 case STATE_RUN: 1221 if (cmd_fis[15] & ATA_SRST) { 1222 s->dev[port].port_state = STATE_RESET; 1223 /* 1224 * When setting SRST in the first H2D FIS in the reset sequence, 1225 * the device does not send a D2H FIS. Host software thus has to 1226 * set the "Clear Busy upon R_OK" bit such that PxCI (and BUSY) 1227 * gets cleared. See AHCI 1.3.1, section 10.4.1 Software Reset. 1228 */ 1229 if (opts & AHCI_CMD_CLR_BUSY) { 1230 ahci_clear_cmd_issue(ad, slot); 1231 } 1232 } 1233 break; 1234 case STATE_RESET: 1235 if (!(cmd_fis[15] & ATA_SRST)) { 1236 /* 1237 * When clearing SRST in the second H2D FIS in the reset 1238 * sequence, the device will execute diagnostics. When this is 1239 * done, the device will send a D2H FIS with the good status. 1240 * See SATA 3.5a Gold, section 11.4 Software reset protocol. 1241 * 1242 * This D2H FIS is the first D2H FIS received from the device, 1243 * and is received regardless if the reset was performed by a 1244 * COMRESET or by setting and clearing the SRST bit. Therefore, 1245 * the logic for this is found in ahci_init_d2h() and not here. 1246 */ 1247 ahci_reset_port(s, port); 1248 } 1249 break; 1250 } 1251 return; 1252 } 1253 1254 /* Check for NCQ command */ 1255 if (is_ncq(cmd_fis[2])) { 1256 process_ncq_command(s, port, cmd_fis, slot); 1257 return; 1258 } 1259 1260 /* Decompose the FIS: 1261 * AHCI does not interpret FIS packets, it only forwards them. 1262 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1263 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1264 * 1265 * ATA4 describes sector number for LBA28/CHS commands. 1266 * ATA6 describes sector number for LBA48 commands. 1267 * ATA8 deprecates CHS fully, describing only LBA28/48. 1268 * 1269 * We dutifully convert the FIS into IDE registers, and allow the 1270 * core layer to interpret them as needed. */ 1271 ide_state->feature = cmd_fis[3]; 1272 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1273 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1274 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1275 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1276 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1277 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1278 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1279 ide_state->hob_feature = cmd_fis[11]; 1280 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1281 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1282 /* 15: Only valid when UPDATE_COMMAND not set. */ 1283 1284 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1285 * table to ide_state->io_buffer */ 1286 if (opts & AHCI_CMD_ATAPI) { 1287 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1288 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { 1289 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); 1290 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); 1291 g_free(pretty_fis); 1292 } 1293 } 1294 1295 ide_state->error = 0; 1296 s->dev[port].done_first_drq = false; 1297 /* Reset transferred byte counter */ 1298 cmd->status = 0; 1299 1300 /* 1301 * A non-NCQ command clears the bit in PxCI after the command has COMPLETED 1302 * successfully (ERROR not set, BUSY and DRQ cleared). 1303 * 1304 * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). 1305 */ 1306 ad->busy_slot = slot; 1307 1308 /* We're ready to process the command in FIS byte 2. */ 1309 ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1310 } 1311 1312 static void handle_cmd(AHCIState *s, int port, uint8_t slot) 1313 { 1314 IDEState *ide_state; 1315 uint64_t tbl_addr; 1316 AHCICmdHdr *cmd; 1317 uint8_t *cmd_fis; 1318 dma_addr_t cmd_len; 1319 1320 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1321 /* Engine currently busy, try again later */ 1322 trace_handle_cmd_busy(s, port); 1323 return; 1324 } 1325 1326 if (!s->dev[port].lst) { 1327 trace_handle_cmd_nolist(s, port); 1328 return; 1329 } 1330 cmd = get_cmd_header(s, port, slot); 1331 /* remember current slot handle for later */ 1332 s->dev[port].cur_cmd = cmd; 1333 1334 /* The device we are working for */ 1335 ide_state = &s->dev[port].port.ifs[0]; 1336 if (!ide_state->blk) { 1337 trace_handle_cmd_badport(s, port); 1338 return; 1339 } 1340 1341 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1342 cmd_len = 0x80; 1343 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1344 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 1345 if (!cmd_fis) { 1346 trace_handle_cmd_badfis(s, port); 1347 return; 1348 } else if (cmd_len != 0x80) { 1349 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); 1350 trace_handle_cmd_badmap(s, port, cmd_len); 1351 goto out; 1352 } 1353 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { 1354 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); 1355 trace_handle_cmd_fis_dump(s, port, pretty_fis); 1356 g_free(pretty_fis); 1357 } 1358 switch (cmd_fis[0]) { 1359 case SATA_FIS_TYPE_REGISTER_H2D: 1360 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1361 break; 1362 default: 1363 trace_handle_cmd_unhandled_fis(s, port, 1364 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1365 break; 1366 } 1367 1368 out: 1369 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, 1370 cmd_len); 1371 } 1372 1373 /* Transfer PIO data between RAM and device */ 1374 static void ahci_pio_transfer(const IDEDMA *dma) 1375 { 1376 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1377 IDEState *s = &ad->port.ifs[0]; 1378 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1379 /* write == ram -> device */ 1380 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1381 int is_write = opts & AHCI_CMD_WRITE; 1382 int is_atapi = opts & AHCI_CMD_ATAPI; 1383 int has_sglist = 0; 1384 bool pio_fis_i; 1385 1386 /* The PIO Setup FIS is received prior to transfer, but the interrupt 1387 * is only triggered after data is received. 1388 * 1389 * The device only sets the 'I' bit in the PIO Setup FIS for device->host 1390 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after 1391 * the first (see "DPIOO1"). The latter is consistent with the spec's 1392 * description of the PACKET protocol, where the command part of ATAPI requests 1393 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests 1394 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. 1395 */ 1396 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); 1397 ahci_write_fis_pio(ad, size, pio_fis_i); 1398 1399 if (is_atapi && !ad->done_first_drq) { 1400 /* already prepopulated iobuffer */ 1401 goto out; 1402 } 1403 1404 if (ahci_dma_prepare_buf(dma, size)) { 1405 has_sglist = 1; 1406 } 1407 1408 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", 1409 size, is_atapi ? "atapi" : "ata", 1410 has_sglist ? "" : "o"); 1411 1412 if (has_sglist && size) { 1413 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1414 1415 if (is_write) { 1416 dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs); 1417 } else { 1418 dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs); 1419 } 1420 } 1421 1422 /* Update number of transferred bytes, destroy sglist */ 1423 dma_buf_commit(s, size); 1424 1425 out: 1426 /* declare that we processed everything */ 1427 s->data_ptr = s->data_end; 1428 1429 ad->done_first_drq = true; 1430 if (pio_fis_i) { 1431 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); 1432 } 1433 } 1434 1435 static void ahci_start_dma(const IDEDMA *dma, IDEState *s, 1436 BlockCompletionFunc *dma_cb) 1437 { 1438 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1439 trace_ahci_start_dma(ad->hba, ad->port_no); 1440 s->io_buffer_offset = 0; 1441 dma_cb(s, 0); 1442 } 1443 1444 static void ahci_restart_dma(const IDEDMA *dma) 1445 { 1446 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1447 } 1448 1449 /** 1450 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1451 * need an extra kick from the AHCI HBA. 1452 */ 1453 static void ahci_restart(const IDEDMA *dma) 1454 { 1455 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1456 int i; 1457 1458 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1459 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1460 if (ncq_tfs->halt) { 1461 execute_ncq_command(ncq_tfs); 1462 } 1463 } 1464 } 1465 1466 /** 1467 * Called in DMA and PIO R/W chains to read the PRDT. 1468 * Not shared with NCQ pathways. 1469 */ 1470 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) 1471 { 1472 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1473 IDEState *s = &ad->port.ifs[0]; 1474 1475 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1476 limit, s->io_buffer_offset) == -1) { 1477 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); 1478 return -1; 1479 } 1480 s->io_buffer_size = s->sg.size; 1481 1482 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); 1483 return s->io_buffer_size; 1484 } 1485 1486 /** 1487 * Updates the command header with a bytes-read value. 1488 * Called via dma_buf_commit, for both DMA and PIO paths. 1489 * sglist destruction is handled within dma_buf_commit. 1490 */ 1491 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) 1492 { 1493 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1494 1495 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1496 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1497 } 1498 1499 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) 1500 { 1501 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1502 IDEState *s = &ad->port.ifs[0]; 1503 uint8_t *p = s->io_buffer + s->io_buffer_index; 1504 int l = s->io_buffer_size - s->io_buffer_index; 1505 1506 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1507 return 0; 1508 } 1509 1510 if (is_write) { 1511 dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1512 } else { 1513 dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1514 } 1515 1516 /* free sglist, update byte count */ 1517 dma_buf_commit(s, l); 1518 s->io_buffer_index += l; 1519 1520 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); 1521 return 1; 1522 } 1523 1524 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) 1525 { 1526 IDEState *ide_state = &ad->port.ifs[0]; 1527 1528 if (!(ide_state->status & ERR_STAT) && 1529 !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { 1530 ad->port_regs.cmd_issue &= ~(1 << slot); 1531 } 1532 } 1533 1534 /* Non-NCQ command is done - This function is never called for NCQ commands. */ 1535 static void ahci_cmd_done(const IDEDMA *dma) 1536 { 1537 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1538 IDEState *ide_state = &ad->port.ifs[0]; 1539 1540 trace_ahci_cmd_done(ad->hba, ad->port_no); 1541 1542 /* no longer busy */ 1543 if (ad->busy_slot != -1) { 1544 ahci_clear_cmd_issue(ad, ad->busy_slot); 1545 ad->busy_slot = -1; 1546 } 1547 1548 /* 1549 * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H 1550 * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise 1551 * an IRQ, we need to call them in reverse order. 1552 */ 1553 ahci_write_fis_d2h(ad, true); 1554 1555 if (!(ide_state->status & ERR_STAT) && 1556 ad->port_regs.cmd_issue && !ad->check_bh) { 1557 ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, 1558 &ad->mem_reentrancy_guard); 1559 qemu_bh_schedule(ad->check_bh); 1560 } 1561 } 1562 1563 static void ahci_irq_set(void *opaque, int n, int level) 1564 { 1565 qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); 1566 } 1567 1568 static const IDEDMAOps ahci_dma_ops = { 1569 .start_dma = ahci_start_dma, 1570 .restart = ahci_restart, 1571 .restart_dma = ahci_restart_dma, 1572 .pio_transfer = ahci_pio_transfer, 1573 .prepare_buf = ahci_dma_prepare_buf, 1574 .commit_buf = ahci_commit_buf, 1575 .rw_buf = ahci_dma_rw_buf, 1576 .cmd_done = ahci_cmd_done, 1577 }; 1578 1579 void ahci_init(AHCIState *s, DeviceState *qdev) 1580 { 1581 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1582 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1583 "ahci", AHCI_MEM_BAR_SIZE); 1584 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1585 "ahci-idp", 32); 1586 } 1587 1588 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as) 1589 { 1590 qemu_irq *irqs; 1591 int i; 1592 1593 s->as = as; 1594 assert(s->ports > 0); 1595 s->dev = g_new0(AHCIDevice, s->ports); 1596 ahci_reg_init(s); 1597 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1598 for (i = 0; i < s->ports; i++) { 1599 AHCIDevice *ad = &s->dev[i]; 1600 1601 ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); 1602 ide_bus_init_output_irq(&ad->port, irqs[i]); 1603 1604 ad->hba = s; 1605 ad->port_no = i; 1606 ad->port.dma = &ad->dma; 1607 ad->port.dma->ops = &ahci_dma_ops; 1608 ide_bus_register_restart_cb(&ad->port); 1609 } 1610 g_free(irqs); 1611 } 1612 1613 void ahci_uninit(AHCIState *s) 1614 { 1615 int i, j; 1616 1617 for (i = 0; i < s->ports; i++) { 1618 AHCIDevice *ad = &s->dev[i]; 1619 1620 for (j = 0; j < 2; j++) { 1621 ide_exit(&ad->port.ifs[j]); 1622 } 1623 object_unparent(OBJECT(&ad->port)); 1624 } 1625 1626 g_free(s->dev); 1627 } 1628 1629 void ahci_reset(AHCIState *s) 1630 { 1631 AHCIPortRegs *pr; 1632 int i; 1633 1634 trace_ahci_reset(s); 1635 1636 s->control_regs.irqstatus = 0; 1637 /* AHCI Enable (AE) 1638 * The implementation of this bit is dependent upon the value of the 1639 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1640 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1641 * read-only and shall have a reset value of '1'. 1642 * 1643 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1644 */ 1645 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1646 1647 for (i = 0; i < s->ports; i++) { 1648 pr = &s->dev[i].port_regs; 1649 pr->irq_stat = 0; 1650 pr->irq_mask = 0; 1651 pr->scr_ctl = 0; 1652 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1653 ahci_reset_port(s, i); 1654 } 1655 } 1656 1657 static const VMStateDescription vmstate_ncq_tfs = { 1658 .name = "ncq state", 1659 .version_id = 1, 1660 .fields = (const VMStateField[]) { 1661 VMSTATE_UINT32(sector_count, NCQTransferState), 1662 VMSTATE_UINT64(lba, NCQTransferState), 1663 VMSTATE_UINT8(tag, NCQTransferState), 1664 VMSTATE_UINT8(cmd, NCQTransferState), 1665 VMSTATE_UINT8(slot, NCQTransferState), 1666 VMSTATE_BOOL(used, NCQTransferState), 1667 VMSTATE_BOOL(halt, NCQTransferState), 1668 VMSTATE_END_OF_LIST() 1669 }, 1670 }; 1671 1672 static const VMStateDescription vmstate_ahci_device = { 1673 .name = "ahci port", 1674 .version_id = 1, 1675 .fields = (const VMStateField[]) { 1676 VMSTATE_IDE_BUS(port, AHCIDevice), 1677 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1678 VMSTATE_UINT32(port_state, AHCIDevice), 1679 VMSTATE_UINT32(finished, AHCIDevice), 1680 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1681 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1682 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1683 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1684 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1685 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1686 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1687 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1688 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1689 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1690 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1691 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1692 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1693 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1694 VMSTATE_BOOL(done_first_drq, AHCIDevice), 1695 VMSTATE_INT32(busy_slot, AHCIDevice), 1696 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1697 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1698 1, vmstate_ncq_tfs, NCQTransferState), 1699 VMSTATE_END_OF_LIST() 1700 }, 1701 }; 1702 1703 static int ahci_state_post_load(void *opaque, int version_id) 1704 { 1705 int i, j; 1706 struct AHCIDevice *ad; 1707 NCQTransferState *ncq_tfs; 1708 AHCIPortRegs *pr; 1709 AHCIState *s = opaque; 1710 1711 for (i = 0; i < s->ports; i++) { 1712 ad = &s->dev[i]; 1713 pr = &ad->port_regs; 1714 1715 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { 1716 error_report("AHCI: DMA engine should be off, but status bit " 1717 "indicates it is still running."); 1718 return -1; 1719 } 1720 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { 1721 error_report("AHCI: FIS RX engine should be off, but status bit " 1722 "indicates it is still running."); 1723 return -1; 1724 } 1725 1726 /* After a migrate, the DMA/FIS engines are "off" and 1727 * need to be conditionally restarted */ 1728 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 1729 if (ahci_cond_start_engines(ad) != 0) { 1730 return -1; 1731 } 1732 1733 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1734 ncq_tfs = &ad->ncq_tfs[j]; 1735 ncq_tfs->drive = ad; 1736 1737 if (ncq_tfs->used != ncq_tfs->halt) { 1738 return -1; 1739 } 1740 if (!ncq_tfs->halt) { 1741 continue; 1742 } 1743 if (!is_ncq(ncq_tfs->cmd)) { 1744 return -1; 1745 } 1746 if (ncq_tfs->slot != ncq_tfs->tag) { 1747 return -1; 1748 } 1749 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1750 * and the command list buffer should be mapped. */ 1751 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1752 if (!ncq_tfs->cmdh) { 1753 return -1; 1754 } 1755 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1756 ncq_tfs->cmdh, 1757 ncq_tfs->sector_count * BDRV_SECTOR_SIZE, 1758 0); 1759 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1760 return -1; 1761 } 1762 } 1763 1764 1765 /* 1766 * If an error is present, ad->busy_slot will be valid and not -1. 1767 * In this case, an operation is waiting to resume and will re-check 1768 * for additional AHCI commands to execute upon completion. 1769 * 1770 * In the case where no error was present, busy_slot will be -1, 1771 * and we should check to see if there are additional commands waiting. 1772 */ 1773 if (ad->busy_slot == -1) { 1774 check_cmd(s, i); 1775 } else { 1776 /* We are in the middle of a command, and may need to access 1777 * the command header in guest memory again. */ 1778 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1779 return -1; 1780 } 1781 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1782 } 1783 } 1784 1785 return 0; 1786 } 1787 1788 const VMStateDescription vmstate_ahci = { 1789 .name = "ahci", 1790 .version_id = 1, 1791 .post_load = ahci_state_post_load, 1792 .fields = (const VMStateField[]) { 1793 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(dev, AHCIState, ports, 1794 vmstate_ahci_device, AHCIDevice), 1795 VMSTATE_UINT32(control_regs.cap, AHCIState), 1796 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1797 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1798 VMSTATE_UINT32(control_regs.impl, AHCIState), 1799 VMSTATE_UINT32(control_regs.version, AHCIState), 1800 VMSTATE_UINT32(idp_index, AHCIState), 1801 VMSTATE_UINT32_EQUAL(ports, AHCIState, NULL), 1802 VMSTATE_END_OF_LIST() 1803 }, 1804 }; 1805 1806 static const VMStateDescription vmstate_sysbus_ahci = { 1807 .name = "sysbus-ahci", 1808 .fields = (const VMStateField[]) { 1809 VMSTATE_AHCI(ahci, SysbusAHCIState), 1810 VMSTATE_END_OF_LIST() 1811 }, 1812 }; 1813 1814 static void sysbus_ahci_reset(DeviceState *dev) 1815 { 1816 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1817 1818 ahci_reset(&s->ahci); 1819 } 1820 1821 static void sysbus_ahci_init(Object *obj) 1822 { 1823 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1824 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1825 1826 ahci_init(&s->ahci, DEVICE(obj)); 1827 1828 sysbus_init_mmio(sbd, &s->ahci.mem); 1829 sysbus_init_irq(sbd, &s->ahci.irq); 1830 } 1831 1832 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1833 { 1834 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1835 1836 ahci_realize(&s->ahci, dev, &address_space_memory); 1837 } 1838 1839 static Property sysbus_ahci_properties[] = { 1840 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1), 1841 DEFINE_PROP_END_OF_LIST(), 1842 }; 1843 1844 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1845 { 1846 DeviceClass *dc = DEVICE_CLASS(klass); 1847 1848 dc->realize = sysbus_ahci_realize; 1849 dc->vmsd = &vmstate_sysbus_ahci; 1850 device_class_set_props(dc, sysbus_ahci_properties); 1851 device_class_set_legacy_reset(dc, sysbus_ahci_reset); 1852 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1853 } 1854 1855 static const TypeInfo sysbus_ahci_info = { 1856 .name = TYPE_SYSBUS_AHCI, 1857 .parent = TYPE_SYS_BUS_DEVICE, 1858 .instance_size = sizeof(SysbusAHCIState), 1859 .instance_init = sysbus_ahci_init, 1860 .class_init = sysbus_ahci_class_init, 1861 }; 1862 1863 static void sysbus_ahci_register_types(void) 1864 { 1865 type_register_static(&sysbus_ahci_info); 1866 } 1867 1868 type_init(sysbus_ahci_register_types) 1869 1870 void ahci_ide_create_devs(AHCIState *ahci, DriveInfo **hd) 1871 { 1872 int i; 1873 1874 for (i = 0; i < ahci->ports; i++) { 1875 if (hd[i] == NULL) { 1876 continue; 1877 } 1878 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 1879 } 1880 } 1881