1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 29 #include "qemu/error-report.h" 30 #include "sysemu/block-backend.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 #define DEBUG_AHCI 0 37 38 #define DPRINTF(port, fmt, ...) \ 39 do { \ 40 if (DEBUG_AHCI) { \ 41 fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \ 42 fprintf(stderr, fmt, ## __VA_ARGS__); \ 43 } \ 44 } while (0) 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s, int port, uint8_t slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static bool ahci_write_fis_d2h(AHCIDevice *ad); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit); 52 static bool ahci_map_clb_address(AHCIDevice *ad); 53 static bool ahci_map_fis_address(AHCIDevice *ad); 54 static void ahci_unmap_clb_address(AHCIDevice *ad); 55 static void ahci_unmap_fis_address(AHCIDevice *ad); 56 57 58 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 59 { 60 uint32_t val; 61 AHCIPortRegs *pr; 62 pr = &s->dev[port].port_regs; 63 64 switch (offset) { 65 case PORT_LST_ADDR: 66 val = pr->lst_addr; 67 break; 68 case PORT_LST_ADDR_HI: 69 val = pr->lst_addr_hi; 70 break; 71 case PORT_FIS_ADDR: 72 val = pr->fis_addr; 73 break; 74 case PORT_FIS_ADDR_HI: 75 val = pr->fis_addr_hi; 76 break; 77 case PORT_IRQ_STAT: 78 val = pr->irq_stat; 79 break; 80 case PORT_IRQ_MASK: 81 val = pr->irq_mask; 82 break; 83 case PORT_CMD: 84 val = pr->cmd; 85 break; 86 case PORT_TFDATA: 87 val = pr->tfdata; 88 break; 89 case PORT_SIG: 90 val = pr->sig; 91 break; 92 case PORT_SCR_STAT: 93 if (s->dev[port].port.ifs[0].blk) { 94 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 95 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 96 } else { 97 val = SATA_SCR_SSTATUS_DET_NODEV; 98 } 99 break; 100 case PORT_SCR_CTL: 101 val = pr->scr_ctl; 102 break; 103 case PORT_SCR_ERR: 104 val = pr->scr_err; 105 break; 106 case PORT_SCR_ACT: 107 val = pr->scr_act; 108 break; 109 case PORT_CMD_ISSUE: 110 val = pr->cmd_issue; 111 break; 112 case PORT_RESERVED: 113 default: 114 val = 0; 115 } 116 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 117 return val; 118 119 } 120 121 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 122 { 123 DeviceState *dev_state = s->container; 124 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 125 TYPE_PCI_DEVICE); 126 127 DPRINTF(0, "raise irq\n"); 128 129 if (pci_dev && msi_enabled(pci_dev)) { 130 msi_notify(pci_dev, 0); 131 } else { 132 qemu_irq_raise(s->irq); 133 } 134 } 135 136 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 137 { 138 DeviceState *dev_state = s->container; 139 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 140 TYPE_PCI_DEVICE); 141 142 DPRINTF(0, "lower irq\n"); 143 144 if (!pci_dev || !msi_enabled(pci_dev)) { 145 qemu_irq_lower(s->irq); 146 } 147 } 148 149 static void ahci_check_irq(AHCIState *s) 150 { 151 int i; 152 153 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 154 155 s->control_regs.irqstatus = 0; 156 for (i = 0; i < s->ports; i++) { 157 AHCIPortRegs *pr = &s->dev[i].port_regs; 158 if (pr->irq_stat & pr->irq_mask) { 159 s->control_regs.irqstatus |= (1 << i); 160 } 161 } 162 163 if (s->control_regs.irqstatus && 164 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 165 ahci_irq_raise(s, NULL); 166 } else { 167 ahci_irq_lower(s, NULL); 168 } 169 } 170 171 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 172 int irq_type) 173 { 174 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 175 irq_type, d->port_regs.irq_mask & irq_type); 176 177 d->port_regs.irq_stat |= irq_type; 178 ahci_check_irq(s); 179 } 180 181 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 182 uint32_t wanted) 183 { 184 hwaddr len = wanted; 185 186 if (*ptr) { 187 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 188 } 189 190 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); 191 if (len < wanted) { 192 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 193 *ptr = NULL; 194 } 195 } 196 197 /** 198 * Check the cmd register to see if we should start or stop 199 * the DMA or FIS RX engines. 200 * 201 * @ad: Device to engage. 202 * @allow_stop: Allow device to transition from started to stopped? 203 * 'no' is useful for migration post_load, which does not expect a transition. 204 * 205 * @return 0 on success, -1 on error. 206 */ 207 static int ahci_cond_start_engines(AHCIDevice *ad, bool allow_stop) 208 { 209 AHCIPortRegs *pr = &ad->port_regs; 210 211 if (pr->cmd & PORT_CMD_START) { 212 if (ahci_map_clb_address(ad)) { 213 pr->cmd |= PORT_CMD_LIST_ON; 214 } else { 215 error_report("AHCI: Failed to start DMA engine: " 216 "bad command list buffer address"); 217 return -1; 218 } 219 } else if (pr->cmd & PORT_CMD_LIST_ON) { 220 if (allow_stop) { 221 ahci_unmap_clb_address(ad); 222 pr->cmd = pr->cmd & ~(PORT_CMD_LIST_ON); 223 } else { 224 error_report("AHCI: DMA engine should be off, " 225 "but appears to still be running"); 226 return -1; 227 } 228 } 229 230 if (pr->cmd & PORT_CMD_FIS_RX) { 231 if (ahci_map_fis_address(ad)) { 232 pr->cmd |= PORT_CMD_FIS_ON; 233 } else { 234 error_report("AHCI: Failed to start FIS receive engine: " 235 "bad FIS receive buffer address"); 236 return -1; 237 } 238 } else if (pr->cmd & PORT_CMD_FIS_ON) { 239 if (allow_stop) { 240 ahci_unmap_fis_address(ad); 241 pr->cmd = pr->cmd & ~(PORT_CMD_FIS_ON); 242 } else { 243 error_report("AHCI: FIS receive engine should be off, " 244 "but appears to still be running"); 245 return -1; 246 } 247 } 248 249 return 0; 250 } 251 252 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 253 { 254 AHCIPortRegs *pr = &s->dev[port].port_regs; 255 256 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 257 switch (offset) { 258 case PORT_LST_ADDR: 259 pr->lst_addr = val; 260 break; 261 case PORT_LST_ADDR_HI: 262 pr->lst_addr_hi = val; 263 break; 264 case PORT_FIS_ADDR: 265 pr->fis_addr = val; 266 break; 267 case PORT_FIS_ADDR_HI: 268 pr->fis_addr_hi = val; 269 break; 270 case PORT_IRQ_STAT: 271 pr->irq_stat &= ~val; 272 ahci_check_irq(s); 273 break; 274 case PORT_IRQ_MASK: 275 pr->irq_mask = val & 0xfdc000ff; 276 ahci_check_irq(s); 277 break; 278 case PORT_CMD: 279 /* Block any Read-only fields from being set; 280 * including LIST_ON and FIS_ON. 281 * The spec requires to set ICC bits to zero after the ICC change 282 * is done. We don't support ICC state changes, therefore always 283 * force the ICC bits to zero. 284 */ 285 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 286 (val & ~(PORT_CMD_RO_MASK|PORT_CMD_ICC_MASK)); 287 288 /* Check FIS RX and CLB engines, allow transition to false: */ 289 ahci_cond_start_engines(&s->dev[port], true); 290 291 /* XXX usually the FIS would be pending on the bus here and 292 issuing deferred until the OS enables FIS receival. 293 Instead, we only submit it once - which works in most 294 cases, but is a hack. */ 295 if ((pr->cmd & PORT_CMD_FIS_ON) && 296 !s->dev[port].init_d2h_sent) { 297 ahci_init_d2h(&s->dev[port]); 298 } 299 300 check_cmd(s, port); 301 break; 302 case PORT_TFDATA: 303 /* Read Only. */ 304 break; 305 case PORT_SIG: 306 /* Read Only */ 307 break; 308 case PORT_SCR_STAT: 309 /* Read Only */ 310 break; 311 case PORT_SCR_CTL: 312 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 313 ((val & AHCI_SCR_SCTL_DET) == 0)) { 314 ahci_reset_port(s, port); 315 } 316 pr->scr_ctl = val; 317 break; 318 case PORT_SCR_ERR: 319 pr->scr_err &= ~val; 320 break; 321 case PORT_SCR_ACT: 322 /* RW1 */ 323 pr->scr_act |= val; 324 break; 325 case PORT_CMD_ISSUE: 326 pr->cmd_issue |= val; 327 check_cmd(s, port); 328 break; 329 default: 330 break; 331 } 332 } 333 334 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 335 { 336 AHCIState *s = opaque; 337 uint32_t val = 0; 338 339 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 340 switch (addr) { 341 case HOST_CAP: 342 val = s->control_regs.cap; 343 break; 344 case HOST_CTL: 345 val = s->control_regs.ghc; 346 break; 347 case HOST_IRQ_STAT: 348 val = s->control_regs.irqstatus; 349 break; 350 case HOST_PORTS_IMPL: 351 val = s->control_regs.impl; 352 break; 353 case HOST_VERSION: 354 val = s->control_regs.version; 355 break; 356 } 357 358 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 359 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 360 (addr < (AHCI_PORT_REGS_START_ADDR + 361 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 362 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 363 addr & AHCI_PORT_ADDR_OFFSET_MASK); 364 } 365 366 return val; 367 } 368 369 370 /** 371 * AHCI 1.3 section 3 ("HBA Memory Registers") 372 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 373 * Caller is responsible for masking unwanted higher order bytes. 374 */ 375 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 376 { 377 hwaddr aligned = addr & ~0x3; 378 int ofst = addr - aligned; 379 uint64_t lo = ahci_mem_read_32(opaque, aligned); 380 uint64_t hi; 381 uint64_t val; 382 383 /* if < 8 byte read does not cross 4 byte boundary */ 384 if (ofst + size <= 4) { 385 val = lo >> (ofst * 8); 386 } else { 387 g_assert_cmpint(size, >, 1); 388 389 /* If the 64bit read is unaligned, we will produce undefined 390 * results. AHCI does not support unaligned 64bit reads. */ 391 hi = ahci_mem_read_32(opaque, aligned + 4); 392 val = (hi << 32 | lo) >> (ofst * 8); 393 } 394 395 DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n", 396 addr, val, size); 397 return val; 398 } 399 400 401 static void ahci_mem_write(void *opaque, hwaddr addr, 402 uint64_t val, unsigned size) 403 { 404 AHCIState *s = opaque; 405 406 DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n", 407 addr, val, size); 408 409 /* Only aligned reads are allowed on AHCI */ 410 if (addr & 3) { 411 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 412 TARGET_FMT_plx "\n", addr); 413 return; 414 } 415 416 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 417 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 418 419 switch (addr) { 420 case HOST_CAP: /* R/WO, RO */ 421 /* FIXME handle R/WO */ 422 break; 423 case HOST_CTL: /* R/W */ 424 if (val & HOST_CTL_RESET) { 425 DPRINTF(-1, "HBA Reset\n"); 426 ahci_reset(s); 427 } else { 428 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 429 ahci_check_irq(s); 430 } 431 break; 432 case HOST_IRQ_STAT: /* R/WC, RO */ 433 s->control_regs.irqstatus &= ~val; 434 ahci_check_irq(s); 435 break; 436 case HOST_PORTS_IMPL: /* R/WO, RO */ 437 /* FIXME handle R/WO */ 438 break; 439 case HOST_VERSION: /* RO */ 440 /* FIXME report write? */ 441 break; 442 default: 443 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 444 } 445 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 446 (addr < (AHCI_PORT_REGS_START_ADDR + 447 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 448 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 449 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 450 } 451 452 } 453 454 static const MemoryRegionOps ahci_mem_ops = { 455 .read = ahci_mem_read, 456 .write = ahci_mem_write, 457 .endianness = DEVICE_LITTLE_ENDIAN, 458 }; 459 460 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 461 unsigned size) 462 { 463 AHCIState *s = opaque; 464 465 if (addr == s->idp_offset) { 466 /* index register */ 467 return s->idp_index; 468 } else if (addr == s->idp_offset + 4) { 469 /* data register - do memory read at location selected by index */ 470 return ahci_mem_read(opaque, s->idp_index, size); 471 } else { 472 return 0; 473 } 474 } 475 476 static void ahci_idp_write(void *opaque, hwaddr addr, 477 uint64_t val, unsigned size) 478 { 479 AHCIState *s = opaque; 480 481 if (addr == s->idp_offset) { 482 /* index register - mask off reserved bits */ 483 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 484 } else if (addr == s->idp_offset + 4) { 485 /* data register - do memory write at location selected by index */ 486 ahci_mem_write(opaque, s->idp_index, val, size); 487 } 488 } 489 490 static const MemoryRegionOps ahci_idp_ops = { 491 .read = ahci_idp_read, 492 .write = ahci_idp_write, 493 .endianness = DEVICE_LITTLE_ENDIAN, 494 }; 495 496 497 static void ahci_reg_init(AHCIState *s) 498 { 499 int i; 500 501 s->control_regs.cap = (s->ports - 1) | 502 (AHCI_NUM_COMMAND_SLOTS << 8) | 503 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 504 HOST_CAP_NCQ | HOST_CAP_AHCI; 505 506 s->control_regs.impl = (1 << s->ports) - 1; 507 508 s->control_regs.version = AHCI_VERSION_1_0; 509 510 for (i = 0; i < s->ports; i++) { 511 s->dev[i].port_state = STATE_RUN; 512 } 513 } 514 515 static void check_cmd(AHCIState *s, int port) 516 { 517 AHCIPortRegs *pr = &s->dev[port].port_regs; 518 uint8_t slot; 519 520 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 521 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 522 if ((pr->cmd_issue & (1U << slot)) && 523 !handle_cmd(s, port, slot)) { 524 pr->cmd_issue &= ~(1U << slot); 525 } 526 } 527 } 528 } 529 530 static void ahci_check_cmd_bh(void *opaque) 531 { 532 AHCIDevice *ad = opaque; 533 534 qemu_bh_delete(ad->check_bh); 535 ad->check_bh = NULL; 536 537 if ((ad->busy_slot != -1) && 538 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 539 /* no longer busy */ 540 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 541 ad->busy_slot = -1; 542 } 543 544 check_cmd(ad->hba, ad->port_no); 545 } 546 547 static void ahci_init_d2h(AHCIDevice *ad) 548 { 549 IDEState *ide_state = &ad->port.ifs[0]; 550 AHCIPortRegs *pr = &ad->port_regs; 551 552 if (ad->init_d2h_sent) { 553 return; 554 } 555 556 if (ahci_write_fis_d2h(ad)) { 557 ad->init_d2h_sent = true; 558 /* We're emulating receiving the first Reg H2D Fis from the device; 559 * Update the SIG register, but otherwise proceed as normal. */ 560 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 561 (ide_state->lcyl << 16) | 562 (ide_state->sector << 8) | 563 (ide_state->nsector & 0xFF); 564 } 565 } 566 567 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 568 { 569 IDEState *s = &ad->port.ifs[0]; 570 s->hcyl = sig >> 24 & 0xFF; 571 s->lcyl = sig >> 16 & 0xFF; 572 s->sector = sig >> 8 & 0xFF; 573 s->nsector = sig & 0xFF; 574 575 DPRINTF(ad->port_no, "set hcyl:lcyl:sect:nsect = 0x%08x\n", sig); 576 } 577 578 static void ahci_reset_port(AHCIState *s, int port) 579 { 580 AHCIDevice *d = &s->dev[port]; 581 AHCIPortRegs *pr = &d->port_regs; 582 IDEState *ide_state = &d->port.ifs[0]; 583 int i; 584 585 DPRINTF(port, "reset port\n"); 586 587 ide_bus_reset(&d->port); 588 ide_state->ncq_queues = AHCI_MAX_CMDS; 589 590 pr->scr_stat = 0; 591 pr->scr_err = 0; 592 pr->scr_act = 0; 593 pr->tfdata = 0x7F; 594 pr->sig = 0xFFFFFFFF; 595 d->busy_slot = -1; 596 d->init_d2h_sent = false; 597 598 ide_state = &s->dev[port].port.ifs[0]; 599 if (!ide_state->blk) { 600 return; 601 } 602 603 /* reset ncq queue */ 604 for (i = 0; i < AHCI_MAX_CMDS; i++) { 605 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 606 ncq_tfs->halt = false; 607 if (!ncq_tfs->used) { 608 continue; 609 } 610 611 if (ncq_tfs->aiocb) { 612 blk_aio_cancel(ncq_tfs->aiocb); 613 ncq_tfs->aiocb = NULL; 614 } 615 616 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 617 if (!ncq_tfs->used) { 618 continue; 619 } 620 621 qemu_sglist_destroy(&ncq_tfs->sglist); 622 ncq_tfs->used = 0; 623 } 624 625 s->dev[port].port_state = STATE_RUN; 626 if (ide_state->drive_kind == IDE_CD) { 627 ahci_set_signature(d, SATA_SIGNATURE_CDROM);\ 628 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 629 } else { 630 ahci_set_signature(d, SATA_SIGNATURE_DISK); 631 ide_state->status = SEEK_STAT | WRERR_STAT; 632 } 633 634 ide_state->error = 1; 635 ahci_init_d2h(d); 636 } 637 638 static void debug_print_fis(uint8_t *fis, int cmd_len) 639 { 640 #if DEBUG_AHCI 641 int i; 642 643 fprintf(stderr, "fis:"); 644 for (i = 0; i < cmd_len; i++) { 645 if ((i & 0xf) == 0) { 646 fprintf(stderr, "\n%02x:",i); 647 } 648 fprintf(stderr, "%02x ",fis[i]); 649 } 650 fprintf(stderr, "\n"); 651 #endif 652 } 653 654 static bool ahci_map_fis_address(AHCIDevice *ad) 655 { 656 AHCIPortRegs *pr = &ad->port_regs; 657 map_page(ad->hba->as, &ad->res_fis, 658 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 659 return ad->res_fis != NULL; 660 } 661 662 static void ahci_unmap_fis_address(AHCIDevice *ad) 663 { 664 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 665 DMA_DIRECTION_FROM_DEVICE, 256); 666 ad->res_fis = NULL; 667 } 668 669 static bool ahci_map_clb_address(AHCIDevice *ad) 670 { 671 AHCIPortRegs *pr = &ad->port_regs; 672 ad->cur_cmd = NULL; 673 map_page(ad->hba->as, &ad->lst, 674 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 675 return ad->lst != NULL; 676 } 677 678 static void ahci_unmap_clb_address(AHCIDevice *ad) 679 { 680 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 681 DMA_DIRECTION_FROM_DEVICE, 1024); 682 ad->lst = NULL; 683 } 684 685 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 686 { 687 AHCIDevice *ad = ncq_tfs->drive; 688 AHCIPortRegs *pr = &ad->port_regs; 689 IDEState *ide_state; 690 SDBFIS *sdb_fis; 691 692 if (!ad->res_fis || 693 !(pr->cmd & PORT_CMD_FIS_RX)) { 694 return; 695 } 696 697 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 698 ide_state = &ad->port.ifs[0]; 699 700 sdb_fis->type = SATA_FIS_TYPE_SDB; 701 /* Interrupt pending & Notification bit */ 702 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 703 sdb_fis->status = ide_state->status & 0x77; 704 sdb_fis->error = ide_state->error; 705 /* update SAct field in SDB_FIS */ 706 sdb_fis->payload = cpu_to_le32(ad->finished); 707 708 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 709 pr->tfdata = (ad->port.ifs[0].error << 8) | 710 (ad->port.ifs[0].status & 0x77) | 711 (pr->tfdata & 0x88); 712 pr->scr_act &= ~ad->finished; 713 ad->finished = 0; 714 715 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */ 716 if (sdb_fis->flags & 0x40) { 717 ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS); 718 } 719 } 720 721 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) 722 { 723 AHCIPortRegs *pr = &ad->port_regs; 724 uint8_t *pio_fis; 725 IDEState *s = &ad->port.ifs[0]; 726 727 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 728 return; 729 } 730 731 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 732 733 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 734 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 735 pio_fis[2] = s->status; 736 pio_fis[3] = s->error; 737 738 pio_fis[4] = s->sector; 739 pio_fis[5] = s->lcyl; 740 pio_fis[6] = s->hcyl; 741 pio_fis[7] = s->select; 742 pio_fis[8] = s->hob_sector; 743 pio_fis[9] = s->hob_lcyl; 744 pio_fis[10] = s->hob_hcyl; 745 pio_fis[11] = 0; 746 pio_fis[12] = s->nsector & 0xFF; 747 pio_fis[13] = (s->nsector >> 8) & 0xFF; 748 pio_fis[14] = 0; 749 pio_fis[15] = s->status; 750 pio_fis[16] = len & 255; 751 pio_fis[17] = len >> 8; 752 pio_fis[18] = 0; 753 pio_fis[19] = 0; 754 755 /* Update shadow registers: */ 756 pr->tfdata = (ad->port.ifs[0].error << 8) | 757 ad->port.ifs[0].status; 758 759 if (pio_fis[2] & ERR_STAT) { 760 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 761 } 762 763 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS); 764 } 765 766 static bool ahci_write_fis_d2h(AHCIDevice *ad) 767 { 768 AHCIPortRegs *pr = &ad->port_regs; 769 uint8_t *d2h_fis; 770 int i; 771 IDEState *s = &ad->port.ifs[0]; 772 773 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 774 return false; 775 } 776 777 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 778 779 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 780 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 781 d2h_fis[2] = s->status; 782 d2h_fis[3] = s->error; 783 784 d2h_fis[4] = s->sector; 785 d2h_fis[5] = s->lcyl; 786 d2h_fis[6] = s->hcyl; 787 d2h_fis[7] = s->select; 788 d2h_fis[8] = s->hob_sector; 789 d2h_fis[9] = s->hob_lcyl; 790 d2h_fis[10] = s->hob_hcyl; 791 d2h_fis[11] = 0; 792 d2h_fis[12] = s->nsector & 0xFF; 793 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 794 for (i = 14; i < 20; i++) { 795 d2h_fis[i] = 0; 796 } 797 798 /* Update shadow registers: */ 799 pr->tfdata = (ad->port.ifs[0].error << 8) | 800 ad->port.ifs[0].status; 801 802 if (d2h_fis[2] & ERR_STAT) { 803 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 804 } 805 806 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 807 return true; 808 } 809 810 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 811 { 812 /* flags_size is zero-based */ 813 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 814 } 815 816 /** 817 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 818 * @ad: The AHCIDevice for whom we are building the SGList. 819 * @sglist: The SGList target to add PRD entries to. 820 * @cmd: The AHCI Command Header that describes where the PRDT is. 821 * @limit: The remaining size of the S/ATA transaction, in bytes. 822 * @offset: The number of bytes already transferred, in bytes. 823 * 824 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 825 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 826 * building the sglist from the PRDT as soon as we hit @limit bytes, 827 * which is <= INT32_MAX/2GiB. 828 */ 829 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 830 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 831 { 832 uint16_t opts = le16_to_cpu(cmd->opts); 833 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 834 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 835 uint64_t prdt_addr = cfis_addr + 0x80; 836 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 837 dma_addr_t real_prdt_len = prdt_len; 838 uint8_t *prdt; 839 int i; 840 int r = 0; 841 uint64_t sum = 0; 842 int off_idx = -1; 843 int64_t off_pos = -1; 844 int tbl_entry_size; 845 IDEBus *bus = &ad->port; 846 BusState *qbus = BUS(bus); 847 848 if (!prdtl) { 849 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 850 return -1; 851 } 852 853 /* map PRDT */ 854 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 855 DMA_DIRECTION_TO_DEVICE))){ 856 DPRINTF(ad->port_no, "map failed\n"); 857 return -1; 858 } 859 860 if (prdt_len < real_prdt_len) { 861 DPRINTF(ad->port_no, "mapped less than expected\n"); 862 r = -1; 863 goto out; 864 } 865 866 /* Get entries in the PRDT, init a qemu sglist accordingly */ 867 if (prdtl > 0) { 868 AHCI_SG *tbl = (AHCI_SG *)prdt; 869 sum = 0; 870 for (i = 0; i < prdtl; i++) { 871 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 872 if (offset < (sum + tbl_entry_size)) { 873 off_idx = i; 874 off_pos = offset - sum; 875 break; 876 } 877 sum += tbl_entry_size; 878 } 879 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 880 DPRINTF(ad->port_no, "%s: Incorrect offset! " 881 "off_idx: %d, off_pos: %"PRId64"\n", 882 __func__, off_idx, off_pos); 883 r = -1; 884 goto out; 885 } 886 887 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 888 ad->hba->as); 889 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 890 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 891 limit)); 892 893 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 894 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 895 MIN(prdt_tbl_entry_size(&tbl[i]), 896 limit - sglist->size)); 897 } 898 } 899 900 out: 901 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 902 DMA_DIRECTION_TO_DEVICE, prdt_len); 903 return r; 904 } 905 906 static void ncq_err(NCQTransferState *ncq_tfs) 907 { 908 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 909 910 ide_state->error = ABRT_ERR; 911 ide_state->status = READY_STAT | ERR_STAT; 912 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 913 ncq_tfs->used = 0; 914 } 915 916 static void ncq_finish(NCQTransferState *ncq_tfs) 917 { 918 /* If we didn't error out, set our finished bit. Errored commands 919 * do not get a bit set for the SDB FIS ACT register, nor do they 920 * clear the outstanding bit in scr_act (PxSACT). */ 921 if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) { 922 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 923 } 924 925 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 926 927 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 928 ncq_tfs->tag); 929 930 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 931 &ncq_tfs->acct); 932 qemu_sglist_destroy(&ncq_tfs->sglist); 933 ncq_tfs->used = 0; 934 } 935 936 static void ncq_cb(void *opaque, int ret) 937 { 938 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 939 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 940 941 if (ret == -ECANCELED) { 942 return; 943 } 944 945 if (ret < 0) { 946 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 947 BlockErrorAction action = blk_get_error_action(ide_state->blk, 948 is_read, -ret); 949 if (action == BLOCK_ERROR_ACTION_STOP) { 950 ncq_tfs->halt = true; 951 ide_state->bus->error_status = IDE_RETRY_HBA; 952 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 953 ncq_err(ncq_tfs); 954 } 955 blk_error_action(ide_state->blk, action, is_read, -ret); 956 } else { 957 ide_state->status = READY_STAT | SEEK_STAT; 958 } 959 960 if (!ncq_tfs->halt) { 961 ncq_finish(ncq_tfs); 962 } 963 } 964 965 static int is_ncq(uint8_t ata_cmd) 966 { 967 /* Based on SATA 3.2 section 13.6.3.2 */ 968 switch (ata_cmd) { 969 case READ_FPDMA_QUEUED: 970 case WRITE_FPDMA_QUEUED: 971 case NCQ_NON_DATA: 972 case RECEIVE_FPDMA_QUEUED: 973 case SEND_FPDMA_QUEUED: 974 return 1; 975 default: 976 return 0; 977 } 978 } 979 980 static void execute_ncq_command(NCQTransferState *ncq_tfs) 981 { 982 AHCIDevice *ad = ncq_tfs->drive; 983 IDEState *ide_state = &ad->port.ifs[0]; 984 int port = ad->port_no; 985 986 g_assert(is_ncq(ncq_tfs->cmd)); 987 ncq_tfs->halt = false; 988 989 switch (ncq_tfs->cmd) { 990 case READ_FPDMA_QUEUED: 991 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", tag %d\n", 992 ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag); 993 994 DPRINTF(port, "tag %d aio read %"PRId64"\n", 995 ncq_tfs->tag, ncq_tfs->lba); 996 997 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 998 &ncq_tfs->sglist, BLOCK_ACCT_READ); 999 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1000 ncq_tfs->lba, ncq_cb, ncq_tfs); 1001 break; 1002 case WRITE_FPDMA_QUEUED: 1003 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 1004 ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag); 1005 1006 DPRINTF(port, "tag %d aio write %"PRId64"\n", 1007 ncq_tfs->tag, ncq_tfs->lba); 1008 1009 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1010 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1011 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1012 ncq_tfs->lba, ncq_cb, ncq_tfs); 1013 break; 1014 default: 1015 DPRINTF(port, "error: unsupported NCQ command (0x%02x) received\n", 1016 ncq_tfs->cmd); 1017 qemu_sglist_destroy(&ncq_tfs->sglist); 1018 ncq_err(ncq_tfs); 1019 } 1020 } 1021 1022 1023 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 1024 uint8_t slot) 1025 { 1026 AHCIDevice *ad = &s->dev[port]; 1027 IDEState *ide_state = &ad->port.ifs[0]; 1028 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 1029 uint8_t tag = ncq_fis->tag >> 3; 1030 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1031 size_t size; 1032 1033 g_assert(is_ncq(ncq_fis->command)); 1034 if (ncq_tfs->used) { 1035 /* error - already in use */ 1036 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 1037 return; 1038 } 1039 1040 ncq_tfs->used = 1; 1041 ncq_tfs->drive = ad; 1042 ncq_tfs->slot = slot; 1043 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1044 ncq_tfs->cmd = ncq_fis->command; 1045 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1046 ((uint64_t)ncq_fis->lba4 << 32) | 1047 ((uint64_t)ncq_fis->lba3 << 24) | 1048 ((uint64_t)ncq_fis->lba2 << 16) | 1049 ((uint64_t)ncq_fis->lba1 << 8) | 1050 (uint64_t)ncq_fis->lba0; 1051 ncq_tfs->tag = tag; 1052 1053 /* Sanity-check the NCQ packet */ 1054 if (tag != slot) { 1055 DPRINTF(port, "Warn: NCQ slot (%d) did not match the given tag (%d)\n", 1056 slot, tag); 1057 } 1058 1059 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1060 DPRINTF(port, "Warn: Attempt to use NCQ auxiliary fields.\n"); 1061 } 1062 if (ncq_fis->prio || ncq_fis->icc) { 1063 DPRINTF(port, "Warn: Unsupported attempt to use PRIO/ICC fields\n"); 1064 } 1065 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1066 DPRINTF(port, "Warn: Unsupported attempt to use Force Unit Access\n"); 1067 } 1068 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1069 DPRINTF(port, "Warn: Unsupported attempt to use Rebuild Assist\n"); 1070 } 1071 1072 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1073 ncq_fis->sector_count_low); 1074 if (!ncq_tfs->sector_count) { 1075 ncq_tfs->sector_count = 0x10000; 1076 } 1077 size = ncq_tfs->sector_count * 512; 1078 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1079 1080 if (ncq_tfs->sglist.size < size) { 1081 error_report("ahci: PRDT length for NCQ command (0x%zx) " 1082 "is smaller than the requested size (0x%zx)", 1083 ncq_tfs->sglist.size, size); 1084 qemu_sglist_destroy(&ncq_tfs->sglist); 1085 ncq_err(ncq_tfs); 1086 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW); 1087 return; 1088 } else if (ncq_tfs->sglist.size != size) { 1089 DPRINTF(port, "Warn: PRDTL (0x%zx)" 1090 " does not match requested size (0x%zx)", 1091 ncq_tfs->sglist.size, size); 1092 } 1093 1094 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 1095 "drive max %"PRId64"\n", 1096 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 1, 1097 ide_state->nb_sectors - 1); 1098 1099 execute_ncq_command(ncq_tfs); 1100 } 1101 1102 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1103 { 1104 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1105 return NULL; 1106 } 1107 1108 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1109 } 1110 1111 static void handle_reg_h2d_fis(AHCIState *s, int port, 1112 uint8_t slot, uint8_t *cmd_fis) 1113 { 1114 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1115 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1116 uint16_t opts = le16_to_cpu(cmd->opts); 1117 1118 if (cmd_fis[1] & 0x0F) { 1119 DPRINTF(port, "Port Multiplier not supported." 1120 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n", 1121 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1122 return; 1123 } 1124 1125 if (cmd_fis[1] & 0x70) { 1126 DPRINTF(port, "Reserved flags set in H2D Register FIS." 1127 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n", 1128 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1129 return; 1130 } 1131 1132 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1133 switch (s->dev[port].port_state) { 1134 case STATE_RUN: 1135 if (cmd_fis[15] & ATA_SRST) { 1136 s->dev[port].port_state = STATE_RESET; 1137 } 1138 break; 1139 case STATE_RESET: 1140 if (!(cmd_fis[15] & ATA_SRST)) { 1141 ahci_reset_port(s, port); 1142 } 1143 break; 1144 } 1145 return; 1146 } 1147 1148 /* Check for NCQ command */ 1149 if (is_ncq(cmd_fis[2])) { 1150 process_ncq_command(s, port, cmd_fis, slot); 1151 return; 1152 } 1153 1154 /* Decompose the FIS: 1155 * AHCI does not interpret FIS packets, it only forwards them. 1156 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1157 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1158 * 1159 * ATA4 describes sector number for LBA28/CHS commands. 1160 * ATA6 describes sector number for LBA48 commands. 1161 * ATA8 deprecates CHS fully, describing only LBA28/48. 1162 * 1163 * We dutifully convert the FIS into IDE registers, and allow the 1164 * core layer to interpret them as needed. */ 1165 ide_state->feature = cmd_fis[3]; 1166 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1167 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1168 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1169 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1170 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1171 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1172 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1173 ide_state->hob_feature = cmd_fis[11]; 1174 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1175 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1176 /* 15: Only valid when UPDATE_COMMAND not set. */ 1177 1178 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1179 * table to ide_state->io_buffer */ 1180 if (opts & AHCI_CMD_ATAPI) { 1181 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1182 debug_print_fis(ide_state->io_buffer, 0x10); 1183 s->dev[port].done_atapi_packet = false; 1184 /* XXX send PIO setup FIS */ 1185 } 1186 1187 ide_state->error = 0; 1188 1189 /* Reset transferred byte counter */ 1190 cmd->status = 0; 1191 1192 /* We're ready to process the command in FIS byte 2. */ 1193 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1194 } 1195 1196 static int handle_cmd(AHCIState *s, int port, uint8_t slot) 1197 { 1198 IDEState *ide_state; 1199 uint64_t tbl_addr; 1200 AHCICmdHdr *cmd; 1201 uint8_t *cmd_fis; 1202 dma_addr_t cmd_len; 1203 1204 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1205 /* Engine currently busy, try again later */ 1206 DPRINTF(port, "engine busy\n"); 1207 return -1; 1208 } 1209 1210 if (!s->dev[port].lst) { 1211 DPRINTF(port, "error: lst not given but cmd handled"); 1212 return -1; 1213 } 1214 cmd = get_cmd_header(s, port, slot); 1215 /* remember current slot handle for later */ 1216 s->dev[port].cur_cmd = cmd; 1217 1218 /* The device we are working for */ 1219 ide_state = &s->dev[port].port.ifs[0]; 1220 if (!ide_state->blk) { 1221 DPRINTF(port, "error: guest accessed unused port"); 1222 return -1; 1223 } 1224 1225 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1226 cmd_len = 0x80; 1227 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1228 DMA_DIRECTION_FROM_DEVICE); 1229 if (!cmd_fis) { 1230 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 1231 return -1; 1232 } else if (cmd_len != 0x80) { 1233 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR); 1234 DPRINTF(port, "error: dma_memory_map failed: " 1235 "(len(%02"PRIx64") != 0x80)\n", 1236 cmd_len); 1237 goto out; 1238 } 1239 debug_print_fis(cmd_fis, 0x80); 1240 1241 switch (cmd_fis[0]) { 1242 case SATA_FIS_TYPE_REGISTER_H2D: 1243 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1244 break; 1245 default: 1246 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 1247 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 1248 cmd_fis[2]); 1249 break; 1250 } 1251 1252 out: 1253 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 1254 cmd_len); 1255 1256 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1257 /* async command, complete later */ 1258 s->dev[port].busy_slot = slot; 1259 return -1; 1260 } 1261 1262 /* done handling the command */ 1263 return 0; 1264 } 1265 1266 /* DMA dev <-> ram */ 1267 static void ahci_start_transfer(IDEDMA *dma) 1268 { 1269 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1270 IDEState *s = &ad->port.ifs[0]; 1271 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1272 /* write == ram -> device */ 1273 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1274 int is_write = opts & AHCI_CMD_WRITE; 1275 int is_atapi = opts & AHCI_CMD_ATAPI; 1276 int has_sglist = 0; 1277 1278 if (is_atapi && !ad->done_atapi_packet) { 1279 /* already prepopulated iobuffer */ 1280 ad->done_atapi_packet = true; 1281 size = 0; 1282 goto out; 1283 } 1284 1285 if (ahci_dma_prepare_buf(dma, size)) { 1286 has_sglist = 1; 1287 } 1288 1289 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1290 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1291 has_sglist ? "" : "o"); 1292 1293 if (has_sglist && size) { 1294 if (is_write) { 1295 dma_buf_write(s->data_ptr, size, &s->sg); 1296 } else { 1297 dma_buf_read(s->data_ptr, size, &s->sg); 1298 } 1299 } 1300 1301 out: 1302 /* declare that we processed everything */ 1303 s->data_ptr = s->data_end; 1304 1305 /* Update number of transferred bytes, destroy sglist */ 1306 dma_buf_commit(s, size); 1307 1308 s->end_transfer_func(s); 1309 1310 if (!(s->status & DRQ_STAT)) { 1311 /* done with PIO send/receive */ 1312 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status)); 1313 } 1314 } 1315 1316 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1317 BlockCompletionFunc *dma_cb) 1318 { 1319 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1320 DPRINTF(ad->port_no, "\n"); 1321 s->io_buffer_offset = 0; 1322 dma_cb(s, 0); 1323 } 1324 1325 static void ahci_restart_dma(IDEDMA *dma) 1326 { 1327 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1328 } 1329 1330 /** 1331 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1332 * need an extra kick from the AHCI HBA. 1333 */ 1334 static void ahci_restart(IDEDMA *dma) 1335 { 1336 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1337 int i; 1338 1339 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1340 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1341 if (ncq_tfs->halt) { 1342 execute_ncq_command(ncq_tfs); 1343 } 1344 } 1345 } 1346 1347 /** 1348 * Called in DMA and PIO R/W chains to read the PRDT. 1349 * Not shared with NCQ pathways. 1350 */ 1351 static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit) 1352 { 1353 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1354 IDEState *s = &ad->port.ifs[0]; 1355 1356 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1357 limit, s->io_buffer_offset) == -1) { 1358 DPRINTF(ad->port_no, "ahci_dma_prepare_buf failed.\n"); 1359 return -1; 1360 } 1361 s->io_buffer_size = s->sg.size; 1362 1363 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1364 return s->io_buffer_size; 1365 } 1366 1367 /** 1368 * Updates the command header with a bytes-read value. 1369 * Called via dma_buf_commit, for both DMA and PIO paths. 1370 * sglist destruction is handled within dma_buf_commit. 1371 */ 1372 static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes) 1373 { 1374 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1375 1376 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1377 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1378 } 1379 1380 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1381 { 1382 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1383 IDEState *s = &ad->port.ifs[0]; 1384 uint8_t *p = s->io_buffer + s->io_buffer_index; 1385 int l = s->io_buffer_size - s->io_buffer_index; 1386 1387 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1388 return 0; 1389 } 1390 1391 if (is_write) { 1392 dma_buf_read(p, l, &s->sg); 1393 } else { 1394 dma_buf_write(p, l, &s->sg); 1395 } 1396 1397 /* free sglist, update byte count */ 1398 dma_buf_commit(s, l); 1399 1400 s->io_buffer_index += l; 1401 1402 DPRINTF(ad->port_no, "len=%#x\n", l); 1403 1404 return 1; 1405 } 1406 1407 static void ahci_cmd_done(IDEDMA *dma) 1408 { 1409 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1410 1411 DPRINTF(ad->port_no, "cmd done\n"); 1412 1413 /* update d2h status */ 1414 ahci_write_fis_d2h(ad); 1415 1416 if (!ad->check_bh) { 1417 /* maybe we still have something to process, check later */ 1418 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1419 qemu_bh_schedule(ad->check_bh); 1420 } 1421 } 1422 1423 static void ahci_irq_set(void *opaque, int n, int level) 1424 { 1425 } 1426 1427 static const IDEDMAOps ahci_dma_ops = { 1428 .start_dma = ahci_start_dma, 1429 .restart = ahci_restart, 1430 .restart_dma = ahci_restart_dma, 1431 .start_transfer = ahci_start_transfer, 1432 .prepare_buf = ahci_dma_prepare_buf, 1433 .commit_buf = ahci_commit_buf, 1434 .rw_buf = ahci_dma_rw_buf, 1435 .cmd_done = ahci_cmd_done, 1436 }; 1437 1438 void ahci_init(AHCIState *s, DeviceState *qdev) 1439 { 1440 s->container = qdev; 1441 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1442 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1443 "ahci", AHCI_MEM_BAR_SIZE); 1444 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1445 "ahci-idp", 32); 1446 } 1447 1448 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1449 { 1450 qemu_irq *irqs; 1451 int i; 1452 1453 s->as = as; 1454 s->ports = ports; 1455 s->dev = g_new0(AHCIDevice, ports); 1456 ahci_reg_init(s); 1457 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1458 for (i = 0; i < s->ports; i++) { 1459 AHCIDevice *ad = &s->dev[i]; 1460 1461 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1462 ide_init2(&ad->port, irqs[i]); 1463 1464 ad->hba = s; 1465 ad->port_no = i; 1466 ad->port.dma = &ad->dma; 1467 ad->port.dma->ops = &ahci_dma_ops; 1468 ide_register_restart_cb(&ad->port); 1469 } 1470 } 1471 1472 void ahci_uninit(AHCIState *s) 1473 { 1474 g_free(s->dev); 1475 } 1476 1477 void ahci_reset(AHCIState *s) 1478 { 1479 AHCIPortRegs *pr; 1480 int i; 1481 1482 s->control_regs.irqstatus = 0; 1483 /* AHCI Enable (AE) 1484 * The implementation of this bit is dependent upon the value of the 1485 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1486 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1487 * read-only and shall have a reset value of '1'. 1488 * 1489 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1490 */ 1491 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1492 1493 for (i = 0; i < s->ports; i++) { 1494 pr = &s->dev[i].port_regs; 1495 pr->irq_stat = 0; 1496 pr->irq_mask = 0; 1497 pr->scr_ctl = 0; 1498 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1499 ahci_reset_port(s, i); 1500 } 1501 } 1502 1503 static const VMStateDescription vmstate_ncq_tfs = { 1504 .name = "ncq state", 1505 .version_id = 1, 1506 .fields = (VMStateField[]) { 1507 VMSTATE_UINT32(sector_count, NCQTransferState), 1508 VMSTATE_UINT64(lba, NCQTransferState), 1509 VMSTATE_UINT8(tag, NCQTransferState), 1510 VMSTATE_UINT8(cmd, NCQTransferState), 1511 VMSTATE_UINT8(slot, NCQTransferState), 1512 VMSTATE_BOOL(used, NCQTransferState), 1513 VMSTATE_BOOL(halt, NCQTransferState), 1514 VMSTATE_END_OF_LIST() 1515 }, 1516 }; 1517 1518 static const VMStateDescription vmstate_ahci_device = { 1519 .name = "ahci port", 1520 .version_id = 1, 1521 .fields = (VMStateField[]) { 1522 VMSTATE_IDE_BUS(port, AHCIDevice), 1523 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1524 VMSTATE_UINT32(port_state, AHCIDevice), 1525 VMSTATE_UINT32(finished, AHCIDevice), 1526 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1527 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1528 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1529 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1530 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1531 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1532 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1533 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1534 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1535 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1536 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1537 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1538 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1539 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1540 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1541 VMSTATE_INT32(busy_slot, AHCIDevice), 1542 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1543 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1544 1, vmstate_ncq_tfs, NCQTransferState), 1545 VMSTATE_END_OF_LIST() 1546 }, 1547 }; 1548 1549 static int ahci_state_post_load(void *opaque, int version_id) 1550 { 1551 int i, j; 1552 struct AHCIDevice *ad; 1553 NCQTransferState *ncq_tfs; 1554 AHCIState *s = opaque; 1555 1556 for (i = 0; i < s->ports; i++) { 1557 ad = &s->dev[i]; 1558 1559 /* Only remap the CLB address if appropriate, disallowing a state 1560 * transition from 'on' to 'off' it should be consistent here. */ 1561 if (ahci_cond_start_engines(ad, false) != 0) { 1562 return -1; 1563 } 1564 1565 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1566 ncq_tfs = &ad->ncq_tfs[j]; 1567 ncq_tfs->drive = ad; 1568 1569 if (ncq_tfs->used != ncq_tfs->halt) { 1570 return -1; 1571 } 1572 if (!ncq_tfs->halt) { 1573 continue; 1574 } 1575 if (!is_ncq(ncq_tfs->cmd)) { 1576 return -1; 1577 } 1578 if (ncq_tfs->slot != ncq_tfs->tag) { 1579 return -1; 1580 } 1581 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1582 * and the command list buffer should be mapped. */ 1583 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1584 if (!ncq_tfs->cmdh) { 1585 return -1; 1586 } 1587 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1588 ncq_tfs->cmdh, ncq_tfs->sector_count * 512, 1589 0); 1590 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1591 return -1; 1592 } 1593 } 1594 1595 1596 /* 1597 * If an error is present, ad->busy_slot will be valid and not -1. 1598 * In this case, an operation is waiting to resume and will re-check 1599 * for additional AHCI commands to execute upon completion. 1600 * 1601 * In the case where no error was present, busy_slot will be -1, 1602 * and we should check to see if there are additional commands waiting. 1603 */ 1604 if (ad->busy_slot == -1) { 1605 check_cmd(s, i); 1606 } else { 1607 /* We are in the middle of a command, and may need to access 1608 * the command header in guest memory again. */ 1609 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1610 return -1; 1611 } 1612 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1613 } 1614 } 1615 1616 return 0; 1617 } 1618 1619 const VMStateDescription vmstate_ahci = { 1620 .name = "ahci", 1621 .version_id = 1, 1622 .post_load = ahci_state_post_load, 1623 .fields = (VMStateField[]) { 1624 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1625 vmstate_ahci_device, AHCIDevice), 1626 VMSTATE_UINT32(control_regs.cap, AHCIState), 1627 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1628 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1629 VMSTATE_UINT32(control_regs.impl, AHCIState), 1630 VMSTATE_UINT32(control_regs.version, AHCIState), 1631 VMSTATE_UINT32(idp_index, AHCIState), 1632 VMSTATE_INT32_EQUAL(ports, AHCIState), 1633 VMSTATE_END_OF_LIST() 1634 }, 1635 }; 1636 1637 static const VMStateDescription vmstate_sysbus_ahci = { 1638 .name = "sysbus-ahci", 1639 .fields = (VMStateField[]) { 1640 VMSTATE_AHCI(ahci, SysbusAHCIState), 1641 VMSTATE_END_OF_LIST() 1642 }, 1643 }; 1644 1645 static void sysbus_ahci_reset(DeviceState *dev) 1646 { 1647 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1648 1649 ahci_reset(&s->ahci); 1650 } 1651 1652 static void sysbus_ahci_init(Object *obj) 1653 { 1654 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1655 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1656 1657 ahci_init(&s->ahci, DEVICE(obj)); 1658 1659 sysbus_init_mmio(sbd, &s->ahci.mem); 1660 sysbus_init_irq(sbd, &s->ahci.irq); 1661 } 1662 1663 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1664 { 1665 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1666 1667 ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports); 1668 } 1669 1670 static Property sysbus_ahci_properties[] = { 1671 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1672 DEFINE_PROP_END_OF_LIST(), 1673 }; 1674 1675 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1676 { 1677 DeviceClass *dc = DEVICE_CLASS(klass); 1678 1679 dc->realize = sysbus_ahci_realize; 1680 dc->vmsd = &vmstate_sysbus_ahci; 1681 dc->props = sysbus_ahci_properties; 1682 dc->reset = sysbus_ahci_reset; 1683 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1684 } 1685 1686 static const TypeInfo sysbus_ahci_info = { 1687 .name = TYPE_SYSBUS_AHCI, 1688 .parent = TYPE_SYS_BUS_DEVICE, 1689 .instance_size = sizeof(SysbusAHCIState), 1690 .instance_init = sysbus_ahci_init, 1691 .class_init = sysbus_ahci_class_init, 1692 }; 1693 1694 #define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1695 #define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1696 #define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1697 #define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4) 1698 #define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1699 #define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1700 #define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1701 #define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4) 1702 #define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1703 #define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1704 #define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1705 #define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1706 #define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1707 #define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4) 1708 #define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1709 #define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1710 #define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4) 1711 #define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4) 1712 #define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4) 1713 1714 static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr, 1715 unsigned size) 1716 { 1717 AllwinnerAHCIState *a = opaque; 1718 uint64_t val = a->regs[addr/4]; 1719 1720 switch (addr / 4) { 1721 case ALLWINNER_AHCI_PHYCS0R: 1722 val |= 0x2 << 28; 1723 break; 1724 case ALLWINNER_AHCI_PHYCS2R: 1725 val &= ~(0x1 << 24); 1726 break; 1727 } 1728 DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n", 1729 addr, val, size); 1730 return val; 1731 } 1732 1733 static void allwinner_ahci_mem_write(void *opaque, hwaddr addr, 1734 uint64_t val, unsigned size) 1735 { 1736 AllwinnerAHCIState *a = opaque; 1737 1738 DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n", 1739 addr, val, size); 1740 a->regs[addr/4] = val; 1741 } 1742 1743 static const MemoryRegionOps allwinner_ahci_mem_ops = { 1744 .read = allwinner_ahci_mem_read, 1745 .write = allwinner_ahci_mem_write, 1746 .valid.min_access_size = 4, 1747 .valid.max_access_size = 4, 1748 .endianness = DEVICE_LITTLE_ENDIAN, 1749 }; 1750 1751 static void allwinner_ahci_init(Object *obj) 1752 { 1753 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1754 AllwinnerAHCIState *a = ALLWINNER_AHCI(obj); 1755 1756 memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a, 1757 "allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE); 1758 memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF, 1759 &a->mmio); 1760 } 1761 1762 static const VMStateDescription vmstate_allwinner_ahci = { 1763 .name = "allwinner-ahci", 1764 .version_id = 1, 1765 .minimum_version_id = 1, 1766 .fields = (VMStateField[]) { 1767 VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState, 1768 ALLWINNER_AHCI_MMIO_SIZE/4), 1769 VMSTATE_END_OF_LIST() 1770 } 1771 }; 1772 1773 static void allwinner_ahci_class_init(ObjectClass *klass, void *data) 1774 { 1775 DeviceClass *dc = DEVICE_CLASS(klass); 1776 1777 dc->vmsd = &vmstate_allwinner_ahci; 1778 } 1779 1780 static const TypeInfo allwinner_ahci_info = { 1781 .name = TYPE_ALLWINNER_AHCI, 1782 .parent = TYPE_SYSBUS_AHCI, 1783 .instance_size = sizeof(AllwinnerAHCIState), 1784 .instance_init = allwinner_ahci_init, 1785 .class_init = allwinner_ahci_class_init, 1786 }; 1787 1788 static void sysbus_ahci_register_types(void) 1789 { 1790 type_register_static(&sysbus_ahci_info); 1791 type_register_static(&allwinner_ahci_info); 1792 } 1793 1794 type_init(sysbus_ahci_register_types) 1795 1796 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) 1797 { 1798 AHCIPCIState *d = ICH_AHCI(dev); 1799 AHCIState *ahci = &d->ahci; 1800 int i; 1801 1802 for (i = 0; i < ahci->ports; i++) { 1803 if (hd[i] == NULL) { 1804 continue; 1805 } 1806 ide_create_drive(&ahci->dev[i].port, 0, hd[i]); 1807 } 1808 1809 } 1810