1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor/monitor.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 /* #define DEBUG_AHCI */ 37 38 #ifdef DEBUG_AHCI 39 #define DPRINTF(port, fmt, ...) \ 40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(port, fmt, ...) do {} while(0) 44 #endif 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s,int port,int slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 53 { 54 uint32_t val; 55 AHCIPortRegs *pr; 56 pr = &s->dev[port].port_regs; 57 58 switch (offset) { 59 case PORT_LST_ADDR: 60 val = pr->lst_addr; 61 break; 62 case PORT_LST_ADDR_HI: 63 val = pr->lst_addr_hi; 64 break; 65 case PORT_FIS_ADDR: 66 val = pr->fis_addr; 67 break; 68 case PORT_FIS_ADDR_HI: 69 val = pr->fis_addr_hi; 70 break; 71 case PORT_IRQ_STAT: 72 val = pr->irq_stat; 73 break; 74 case PORT_IRQ_MASK: 75 val = pr->irq_mask; 76 break; 77 case PORT_CMD: 78 val = pr->cmd; 79 break; 80 case PORT_TFDATA: 81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 82 s->dev[port].port.ifs[0].status; 83 break; 84 case PORT_SIG: 85 val = pr->sig; 86 break; 87 case PORT_SCR_STAT: 88 if (s->dev[port].port.ifs[0].bs) { 89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 91 } else { 92 val = SATA_SCR_SSTATUS_DET_NODEV; 93 } 94 break; 95 case PORT_SCR_CTL: 96 val = pr->scr_ctl; 97 break; 98 case PORT_SCR_ERR: 99 val = pr->scr_err; 100 break; 101 case PORT_SCR_ACT: 102 pr->scr_act &= ~s->dev[port].finished; 103 s->dev[port].finished = 0; 104 val = pr->scr_act; 105 break; 106 case PORT_CMD_ISSUE: 107 val = pr->cmd_issue; 108 break; 109 case PORT_RESERVED: 110 default: 111 val = 0; 112 } 113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 114 return val; 115 116 } 117 118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 119 { 120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 121 PCIDevice *pci_dev = 122 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 123 124 DPRINTF(0, "raise irq\n"); 125 126 if (pci_dev && msi_enabled(pci_dev)) { 127 msi_notify(pci_dev, 0); 128 } else { 129 qemu_irq_raise(s->irq); 130 } 131 } 132 133 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 134 { 135 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 136 PCIDevice *pci_dev = 137 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 138 139 DPRINTF(0, "lower irq\n"); 140 141 if (!pci_dev || !msi_enabled(pci_dev)) { 142 qemu_irq_lower(s->irq); 143 } 144 } 145 146 static void ahci_check_irq(AHCIState *s) 147 { 148 int i; 149 150 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 151 152 s->control_regs.irqstatus = 0; 153 for (i = 0; i < s->ports; i++) { 154 AHCIPortRegs *pr = &s->dev[i].port_regs; 155 if (pr->irq_stat & pr->irq_mask) { 156 s->control_regs.irqstatus |= (1 << i); 157 } 158 } 159 160 if (s->control_regs.irqstatus && 161 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 162 ahci_irq_raise(s, NULL); 163 } else { 164 ahci_irq_lower(s, NULL); 165 } 166 } 167 168 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 169 int irq_type) 170 { 171 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 172 irq_type, d->port_regs.irq_mask & irq_type); 173 174 d->port_regs.irq_stat |= irq_type; 175 ahci_check_irq(s); 176 } 177 178 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 179 uint32_t wanted) 180 { 181 hwaddr len = wanted; 182 183 if (*ptr) { 184 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 185 } 186 187 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); 188 if (len < wanted) { 189 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 190 *ptr = NULL; 191 } 192 } 193 194 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 195 { 196 AHCIPortRegs *pr = &s->dev[port].port_regs; 197 198 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 199 switch (offset) { 200 case PORT_LST_ADDR: 201 pr->lst_addr = val; 202 map_page(s->as, &s->dev[port].lst, 203 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 204 s->dev[port].cur_cmd = NULL; 205 break; 206 case PORT_LST_ADDR_HI: 207 pr->lst_addr_hi = val; 208 map_page(s->as, &s->dev[port].lst, 209 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 210 s->dev[port].cur_cmd = NULL; 211 break; 212 case PORT_FIS_ADDR: 213 pr->fis_addr = val; 214 map_page(s->as, &s->dev[port].res_fis, 215 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 216 break; 217 case PORT_FIS_ADDR_HI: 218 pr->fis_addr_hi = val; 219 map_page(s->as, &s->dev[port].res_fis, 220 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 221 break; 222 case PORT_IRQ_STAT: 223 pr->irq_stat &= ~val; 224 ahci_check_irq(s); 225 break; 226 case PORT_IRQ_MASK: 227 pr->irq_mask = val & 0xfdc000ff; 228 ahci_check_irq(s); 229 break; 230 case PORT_CMD: 231 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 232 233 if (pr->cmd & PORT_CMD_START) { 234 pr->cmd |= PORT_CMD_LIST_ON; 235 } 236 237 if (pr->cmd & PORT_CMD_FIS_RX) { 238 pr->cmd |= PORT_CMD_FIS_ON; 239 } 240 241 /* XXX usually the FIS would be pending on the bus here and 242 issuing deferred until the OS enables FIS receival. 243 Instead, we only submit it once - which works in most 244 cases, but is a hack. */ 245 if ((pr->cmd & PORT_CMD_FIS_ON) && 246 !s->dev[port].init_d2h_sent) { 247 ahci_init_d2h(&s->dev[port]); 248 s->dev[port].init_d2h_sent = true; 249 } 250 251 check_cmd(s, port); 252 break; 253 case PORT_TFDATA: 254 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 255 s->dev[port].port.ifs[0].status = val & 0xff; 256 break; 257 case PORT_SIG: 258 pr->sig = val; 259 break; 260 case PORT_SCR_STAT: 261 pr->scr_stat = val; 262 break; 263 case PORT_SCR_CTL: 264 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 265 ((val & AHCI_SCR_SCTL_DET) == 0)) { 266 ahci_reset_port(s, port); 267 } 268 pr->scr_ctl = val; 269 break; 270 case PORT_SCR_ERR: 271 pr->scr_err &= ~val; 272 break; 273 case PORT_SCR_ACT: 274 /* RW1 */ 275 pr->scr_act |= val; 276 break; 277 case PORT_CMD_ISSUE: 278 pr->cmd_issue |= val; 279 check_cmd(s, port); 280 break; 281 default: 282 break; 283 } 284 } 285 286 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 287 unsigned size) 288 { 289 AHCIState *s = opaque; 290 uint32_t val = 0; 291 292 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 293 switch (addr) { 294 case HOST_CAP: 295 val = s->control_regs.cap; 296 break; 297 case HOST_CTL: 298 val = s->control_regs.ghc; 299 break; 300 case HOST_IRQ_STAT: 301 val = s->control_regs.irqstatus; 302 break; 303 case HOST_PORTS_IMPL: 304 val = s->control_regs.impl; 305 break; 306 case HOST_VERSION: 307 val = s->control_regs.version; 308 break; 309 } 310 311 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 312 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 313 (addr < (AHCI_PORT_REGS_START_ADDR + 314 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 315 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 316 addr & AHCI_PORT_ADDR_OFFSET_MASK); 317 } 318 319 return val; 320 } 321 322 323 324 static void ahci_mem_write(void *opaque, hwaddr addr, 325 uint64_t val, unsigned size) 326 { 327 AHCIState *s = opaque; 328 329 /* Only aligned reads are allowed on AHCI */ 330 if (addr & 3) { 331 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 332 TARGET_FMT_plx "\n", addr); 333 return; 334 } 335 336 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 337 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 338 339 switch (addr) { 340 case HOST_CAP: /* R/WO, RO */ 341 /* FIXME handle R/WO */ 342 break; 343 case HOST_CTL: /* R/W */ 344 if (val & HOST_CTL_RESET) { 345 DPRINTF(-1, "HBA Reset\n"); 346 ahci_reset(s); 347 } else { 348 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 349 ahci_check_irq(s); 350 } 351 break; 352 case HOST_IRQ_STAT: /* R/WC, RO */ 353 s->control_regs.irqstatus &= ~val; 354 ahci_check_irq(s); 355 break; 356 case HOST_PORTS_IMPL: /* R/WO, RO */ 357 /* FIXME handle R/WO */ 358 break; 359 case HOST_VERSION: /* RO */ 360 /* FIXME report write? */ 361 break; 362 default: 363 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 364 } 365 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 366 (addr < (AHCI_PORT_REGS_START_ADDR + 367 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 368 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 369 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 370 } 371 372 } 373 374 static const MemoryRegionOps ahci_mem_ops = { 375 .read = ahci_mem_read, 376 .write = ahci_mem_write, 377 .endianness = DEVICE_LITTLE_ENDIAN, 378 }; 379 380 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 381 unsigned size) 382 { 383 AHCIState *s = opaque; 384 385 if (addr == s->idp_offset) { 386 /* index register */ 387 return s->idp_index; 388 } else if (addr == s->idp_offset + 4) { 389 /* data register - do memory read at location selected by index */ 390 return ahci_mem_read(opaque, s->idp_index, size); 391 } else { 392 return 0; 393 } 394 } 395 396 static void ahci_idp_write(void *opaque, hwaddr addr, 397 uint64_t val, unsigned size) 398 { 399 AHCIState *s = opaque; 400 401 if (addr == s->idp_offset) { 402 /* index register - mask off reserved bits */ 403 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 404 } else if (addr == s->idp_offset + 4) { 405 /* data register - do memory write at location selected by index */ 406 ahci_mem_write(opaque, s->idp_index, val, size); 407 } 408 } 409 410 static const MemoryRegionOps ahci_idp_ops = { 411 .read = ahci_idp_read, 412 .write = ahci_idp_write, 413 .endianness = DEVICE_LITTLE_ENDIAN, 414 }; 415 416 417 static void ahci_reg_init(AHCIState *s) 418 { 419 int i; 420 421 s->control_regs.cap = (s->ports - 1) | 422 (AHCI_NUM_COMMAND_SLOTS << 8) | 423 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 424 HOST_CAP_NCQ | HOST_CAP_AHCI; 425 426 s->control_regs.impl = (1 << s->ports) - 1; 427 428 s->control_regs.version = AHCI_VERSION_1_0; 429 430 for (i = 0; i < s->ports; i++) { 431 s->dev[i].port_state = STATE_RUN; 432 } 433 } 434 435 static void check_cmd(AHCIState *s, int port) 436 { 437 AHCIPortRegs *pr = &s->dev[port].port_regs; 438 int slot; 439 440 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 441 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 442 if ((pr->cmd_issue & (1U << slot)) && 443 !handle_cmd(s, port, slot)) { 444 pr->cmd_issue &= ~(1U << slot); 445 } 446 } 447 } 448 } 449 450 static void ahci_check_cmd_bh(void *opaque) 451 { 452 AHCIDevice *ad = opaque; 453 454 qemu_bh_delete(ad->check_bh); 455 ad->check_bh = NULL; 456 457 if ((ad->busy_slot != -1) && 458 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 459 /* no longer busy */ 460 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 461 ad->busy_slot = -1; 462 } 463 464 check_cmd(ad->hba, ad->port_no); 465 } 466 467 static void ahci_init_d2h(AHCIDevice *ad) 468 { 469 uint8_t init_fis[20]; 470 IDEState *ide_state = &ad->port.ifs[0]; 471 472 memset(init_fis, 0, sizeof(init_fis)); 473 474 init_fis[4] = 1; 475 init_fis[12] = 1; 476 477 if (ide_state->drive_kind == IDE_CD) { 478 init_fis[5] = ide_state->lcyl; 479 init_fis[6] = ide_state->hcyl; 480 } 481 482 ahci_write_fis_d2h(ad, init_fis); 483 } 484 485 static void ahci_reset_port(AHCIState *s, int port) 486 { 487 AHCIDevice *d = &s->dev[port]; 488 AHCIPortRegs *pr = &d->port_regs; 489 IDEState *ide_state = &d->port.ifs[0]; 490 int i; 491 492 DPRINTF(port, "reset port\n"); 493 494 ide_bus_reset(&d->port); 495 ide_state->ncq_queues = AHCI_MAX_CMDS; 496 497 pr->scr_stat = 0; 498 pr->scr_err = 0; 499 pr->scr_act = 0; 500 d->busy_slot = -1; 501 d->init_d2h_sent = false; 502 503 ide_state = &s->dev[port].port.ifs[0]; 504 if (!ide_state->bs) { 505 return; 506 } 507 508 /* reset ncq queue */ 509 for (i = 0; i < AHCI_MAX_CMDS; i++) { 510 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 511 if (!ncq_tfs->used) { 512 continue; 513 } 514 515 if (ncq_tfs->aiocb) { 516 bdrv_aio_cancel(ncq_tfs->aiocb); 517 ncq_tfs->aiocb = NULL; 518 } 519 520 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 521 if (!ncq_tfs->used) { 522 continue; 523 } 524 525 qemu_sglist_destroy(&ncq_tfs->sglist); 526 ncq_tfs->used = 0; 527 } 528 529 s->dev[port].port_state = STATE_RUN; 530 if (!ide_state->bs) { 531 s->dev[port].port_regs.sig = 0; 532 ide_state->status = SEEK_STAT | WRERR_STAT; 533 } else if (ide_state->drive_kind == IDE_CD) { 534 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 535 ide_state->lcyl = 0x14; 536 ide_state->hcyl = 0xeb; 537 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 538 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 539 } else { 540 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 541 ide_state->status = SEEK_STAT | WRERR_STAT; 542 } 543 544 ide_state->error = 1; 545 ahci_init_d2h(d); 546 } 547 548 static void debug_print_fis(uint8_t *fis, int cmd_len) 549 { 550 #ifdef DEBUG_AHCI 551 int i; 552 553 fprintf(stderr, "fis:"); 554 for (i = 0; i < cmd_len; i++) { 555 if ((i & 0xf) == 0) { 556 fprintf(stderr, "\n%02x:",i); 557 } 558 fprintf(stderr, "%02x ",fis[i]); 559 } 560 fprintf(stderr, "\n"); 561 #endif 562 } 563 564 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 565 { 566 AHCIPortRegs *pr = &s->dev[port].port_regs; 567 IDEState *ide_state; 568 uint8_t *sdb_fis; 569 570 if (!s->dev[port].res_fis || 571 !(pr->cmd & PORT_CMD_FIS_RX)) { 572 return; 573 } 574 575 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 576 ide_state = &s->dev[port].port.ifs[0]; 577 578 /* clear memory */ 579 *(uint32_t*)sdb_fis = 0; 580 581 /* write values */ 582 sdb_fis[0] = ide_state->error; 583 sdb_fis[2] = ide_state->status & 0x77; 584 s->dev[port].finished |= finished; 585 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 586 587 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS); 588 } 589 590 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 591 { 592 AHCIPortRegs *pr = &ad->port_regs; 593 uint8_t *d2h_fis; 594 int i; 595 dma_addr_t cmd_len = 0x80; 596 int cmd_mapped = 0; 597 598 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 599 return; 600 } 601 602 if (!cmd_fis) { 603 /* map cmd_fis */ 604 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 605 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 606 DMA_DIRECTION_TO_DEVICE); 607 cmd_mapped = 1; 608 } 609 610 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 611 612 d2h_fis[0] = 0x34; 613 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 614 d2h_fis[2] = ad->port.ifs[0].status; 615 d2h_fis[3] = ad->port.ifs[0].error; 616 617 d2h_fis[4] = cmd_fis[4]; 618 d2h_fis[5] = cmd_fis[5]; 619 d2h_fis[6] = cmd_fis[6]; 620 d2h_fis[7] = cmd_fis[7]; 621 d2h_fis[8] = cmd_fis[8]; 622 d2h_fis[9] = cmd_fis[9]; 623 d2h_fis[10] = cmd_fis[10]; 624 d2h_fis[11] = cmd_fis[11]; 625 d2h_fis[12] = cmd_fis[12]; 626 d2h_fis[13] = cmd_fis[13]; 627 for (i = 14; i < 20; i++) { 628 d2h_fis[i] = 0; 629 } 630 631 if (d2h_fis[2] & ERR_STAT) { 632 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES); 633 } 634 635 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 636 637 if (cmd_mapped) { 638 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 639 DMA_DIRECTION_TO_DEVICE, cmd_len); 640 } 641 } 642 643 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 644 { 645 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 646 } 647 648 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset) 649 { 650 AHCICmdHdr *cmd = ad->cur_cmd; 651 uint32_t opts = le32_to_cpu(cmd->opts); 652 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 653 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 654 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 655 dma_addr_t real_prdt_len = prdt_len; 656 uint8_t *prdt; 657 int i; 658 int r = 0; 659 int sum = 0; 660 int off_idx = -1; 661 int off_pos = -1; 662 int tbl_entry_size; 663 IDEBus *bus = &ad->port; 664 BusState *qbus = BUS(bus); 665 666 if (!sglist_alloc_hint) { 667 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 668 return -1; 669 } 670 671 /* map PRDT */ 672 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 673 DMA_DIRECTION_TO_DEVICE))){ 674 DPRINTF(ad->port_no, "map failed\n"); 675 return -1; 676 } 677 678 if (prdt_len < real_prdt_len) { 679 DPRINTF(ad->port_no, "mapped less than expected\n"); 680 r = -1; 681 goto out; 682 } 683 684 /* Get entries in the PRDT, init a qemu sglist accordingly */ 685 if (sglist_alloc_hint > 0) { 686 AHCI_SG *tbl = (AHCI_SG *)prdt; 687 sum = 0; 688 for (i = 0; i < sglist_alloc_hint; i++) { 689 /* flags_size is zero-based */ 690 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 691 if (offset <= (sum + tbl_entry_size)) { 692 off_idx = i; 693 off_pos = offset - sum; 694 break; 695 } 696 sum += tbl_entry_size; 697 } 698 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 699 DPRINTF(ad->port_no, "%s: Incorrect offset! " 700 "off_idx: %d, off_pos: %d\n", 701 __func__, off_idx, off_pos); 702 r = -1; 703 goto out; 704 } 705 706 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx), 707 ad->hba->as); 708 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos), 709 prdt_tbl_entry_size(&tbl[off_idx]) - off_pos); 710 711 for (i = off_idx + 1; i < sglist_alloc_hint; i++) { 712 /* flags_size is zero-based */ 713 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 714 prdt_tbl_entry_size(&tbl[i])); 715 } 716 } 717 718 out: 719 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 720 DMA_DIRECTION_TO_DEVICE, prdt_len); 721 return r; 722 } 723 724 static void ncq_cb(void *opaque, int ret) 725 { 726 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 727 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 728 729 /* Clear bit for this tag in SActive */ 730 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 731 732 if (ret < 0) { 733 /* error */ 734 ide_state->error = ABRT_ERR; 735 ide_state->status = READY_STAT | ERR_STAT; 736 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 737 } else { 738 ide_state->status = READY_STAT | SEEK_STAT; 739 } 740 741 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 742 (1 << ncq_tfs->tag)); 743 744 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 745 ncq_tfs->tag); 746 747 bdrv_acct_done(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct); 748 qemu_sglist_destroy(&ncq_tfs->sglist); 749 ncq_tfs->used = 0; 750 } 751 752 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 753 int slot) 754 { 755 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 756 uint8_t tag = ncq_fis->tag >> 3; 757 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 758 759 if (ncq_tfs->used) { 760 /* error - already in use */ 761 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 762 return; 763 } 764 765 ncq_tfs->used = 1; 766 ncq_tfs->drive = &s->dev[port]; 767 ncq_tfs->slot = slot; 768 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 769 ((uint64_t)ncq_fis->lba4 << 32) | 770 ((uint64_t)ncq_fis->lba3 << 24) | 771 ((uint64_t)ncq_fis->lba2 << 16) | 772 ((uint64_t)ncq_fis->lba1 << 8) | 773 (uint64_t)ncq_fis->lba0; 774 775 /* Note: We calculate the sector count, but don't currently rely on it. 776 * The total size of the DMA buffer tells us the transfer size instead. */ 777 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 778 ncq_fis->sector_count_low; 779 780 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 781 "drive max %"PRId64"\n", 782 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 783 s->dev[port].port.ifs[0].nb_sectors - 1); 784 785 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0); 786 ncq_tfs->tag = tag; 787 788 switch(ncq_fis->command) { 789 case READ_FPDMA_QUEUED: 790 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 791 "tag %d\n", 792 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 793 794 DPRINTF(port, "tag %d aio read %"PRId64"\n", 795 ncq_tfs->tag, ncq_tfs->lba); 796 797 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 798 &ncq_tfs->sglist, BDRV_ACCT_READ); 799 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 800 &ncq_tfs->sglist, ncq_tfs->lba, 801 ncq_cb, ncq_tfs); 802 break; 803 case WRITE_FPDMA_QUEUED: 804 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 805 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 806 807 DPRINTF(port, "tag %d aio write %"PRId64"\n", 808 ncq_tfs->tag, ncq_tfs->lba); 809 810 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 811 &ncq_tfs->sglist, BDRV_ACCT_WRITE); 812 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 813 &ncq_tfs->sglist, ncq_tfs->lba, 814 ncq_cb, ncq_tfs); 815 break; 816 default: 817 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 818 qemu_sglist_destroy(&ncq_tfs->sglist); 819 break; 820 } 821 } 822 823 static int handle_cmd(AHCIState *s, int port, int slot) 824 { 825 IDEState *ide_state; 826 uint32_t opts; 827 uint64_t tbl_addr; 828 AHCICmdHdr *cmd; 829 uint8_t *cmd_fis; 830 dma_addr_t cmd_len; 831 832 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 833 /* Engine currently busy, try again later */ 834 DPRINTF(port, "engine busy\n"); 835 return -1; 836 } 837 838 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 839 840 if (!s->dev[port].lst) { 841 DPRINTF(port, "error: lst not given but cmd handled"); 842 return -1; 843 } 844 845 /* remember current slot handle for later */ 846 s->dev[port].cur_cmd = cmd; 847 848 opts = le32_to_cpu(cmd->opts); 849 tbl_addr = le64_to_cpu(cmd->tbl_addr); 850 851 cmd_len = 0x80; 852 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 853 DMA_DIRECTION_FROM_DEVICE); 854 855 if (!cmd_fis) { 856 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 857 return -1; 858 } 859 860 /* The device we are working for */ 861 ide_state = &s->dev[port].port.ifs[0]; 862 863 if (!ide_state->bs) { 864 DPRINTF(port, "error: guest accessed unused port"); 865 goto out; 866 } 867 868 debug_print_fis(cmd_fis, 0x90); 869 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 870 871 switch (cmd_fis[0]) { 872 case SATA_FIS_TYPE_REGISTER_H2D: 873 break; 874 default: 875 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 876 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 877 cmd_fis[2]); 878 goto out; 879 break; 880 } 881 882 switch (cmd_fis[1]) { 883 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 884 break; 885 case 0: 886 break; 887 default: 888 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 889 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 890 cmd_fis[2]); 891 goto out; 892 break; 893 } 894 895 switch (s->dev[port].port_state) { 896 case STATE_RUN: 897 if (cmd_fis[15] & ATA_SRST) { 898 s->dev[port].port_state = STATE_RESET; 899 } 900 break; 901 case STATE_RESET: 902 if (!(cmd_fis[15] & ATA_SRST)) { 903 ahci_reset_port(s, port); 904 } 905 break; 906 } 907 908 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 909 910 /* Check for NCQ command */ 911 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 912 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 913 process_ncq_command(s, port, cmd_fis, slot); 914 goto out; 915 } 916 917 /* Decompose the FIS */ 918 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 919 ide_state->feature = cmd_fis[3]; 920 if (!ide_state->nsector) { 921 ide_state->nsector = 256; 922 } 923 924 if (ide_state->drive_kind != IDE_CD) { 925 /* 926 * We set the sector depending on the sector defined in the FIS. 927 * Unfortunately, the spec isn't exactly obvious on this one. 928 * 929 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 930 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 931 * such a command. 932 * 933 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 934 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 935 * a command. 936 * 937 * Since the spec doesn't explicitly state what each field should 938 * do, I simply assume non-used fields as reserved and OR everything 939 * together, independent of the command. 940 */ 941 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 942 | ((uint64_t)cmd_fis[9] << 32) 943 /* This is used for LBA48 commands */ 944 | ((uint64_t)cmd_fis[8] << 24) 945 /* This is used for non-LBA48 commands */ 946 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 947 | ((uint64_t)cmd_fis[6] << 16) 948 | ((uint64_t)cmd_fis[5] << 8) 949 | cmd_fis[4]); 950 } 951 952 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 953 * table to ide_state->io_buffer 954 */ 955 if (opts & AHCI_CMD_ATAPI) { 956 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 957 ide_state->lcyl = 0x14; 958 ide_state->hcyl = 0xeb; 959 debug_print_fis(ide_state->io_buffer, 0x10); 960 ide_state->feature = IDE_FEATURE_DMA; 961 s->dev[port].done_atapi_packet = false; 962 /* XXX send PIO setup FIS */ 963 } 964 965 ide_state->error = 0; 966 967 /* Reset transferred byte counter */ 968 cmd->status = 0; 969 970 /* We're ready to process the command in FIS byte 2. */ 971 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 972 973 if ((s->dev[port].port.ifs[0].status & (READY_STAT|DRQ_STAT|BUSY_STAT)) == 974 READY_STAT) { 975 ahci_write_fis_d2h(&s->dev[port], cmd_fis); 976 } 977 } 978 979 out: 980 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 981 cmd_len); 982 983 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 984 /* async command, complete later */ 985 s->dev[port].busy_slot = slot; 986 return -1; 987 } 988 989 /* done handling the command */ 990 return 0; 991 } 992 993 /* DMA dev <-> ram */ 994 static int ahci_start_transfer(IDEDMA *dma) 995 { 996 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 997 IDEState *s = &ad->port.ifs[0]; 998 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 999 /* write == ram -> device */ 1000 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 1001 int is_write = opts & AHCI_CMD_WRITE; 1002 int is_atapi = opts & AHCI_CMD_ATAPI; 1003 int has_sglist = 0; 1004 1005 if (is_atapi && !ad->done_atapi_packet) { 1006 /* already prepopulated iobuffer */ 1007 ad->done_atapi_packet = true; 1008 goto out; 1009 } 1010 1011 if (!ahci_populate_sglist(ad, &s->sg, 0)) { 1012 has_sglist = 1; 1013 } 1014 1015 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1016 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1017 has_sglist ? "" : "o"); 1018 1019 if (has_sglist && size) { 1020 if (is_write) { 1021 dma_buf_write(s->data_ptr, size, &s->sg); 1022 } else { 1023 dma_buf_read(s->data_ptr, size, &s->sg); 1024 } 1025 } 1026 1027 /* update number of transferred bytes */ 1028 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1029 1030 out: 1031 /* declare that we processed everything */ 1032 s->data_ptr = s->data_end; 1033 1034 if (has_sglist) { 1035 qemu_sglist_destroy(&s->sg); 1036 } 1037 1038 s->end_transfer_func(s); 1039 1040 if (!(s->status & DRQ_STAT)) { 1041 /* done with DMA */ 1042 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1043 } 1044 1045 return 0; 1046 } 1047 1048 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1049 BlockDriverCompletionFunc *dma_cb) 1050 { 1051 #ifdef DEBUG_AHCI 1052 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1053 #endif 1054 DPRINTF(ad->port_no, "\n"); 1055 s->io_buffer_offset = 0; 1056 dma_cb(s, 0); 1057 } 1058 1059 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1060 { 1061 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1062 IDEState *s = &ad->port.ifs[0]; 1063 1064 ahci_populate_sglist(ad, &s->sg, 0); 1065 s->io_buffer_size = s->sg.size; 1066 1067 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1068 return s->io_buffer_size != 0; 1069 } 1070 1071 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1072 { 1073 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1074 IDEState *s = &ad->port.ifs[0]; 1075 uint8_t *p = s->io_buffer + s->io_buffer_index; 1076 int l = s->io_buffer_size - s->io_buffer_index; 1077 1078 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) { 1079 return 0; 1080 } 1081 1082 if (is_write) { 1083 dma_buf_read(p, l, &s->sg); 1084 } else { 1085 dma_buf_write(p, l, &s->sg); 1086 } 1087 1088 /* free sglist that was created in ahci_populate_sglist() */ 1089 qemu_sglist_destroy(&s->sg); 1090 1091 /* update number of transferred bytes */ 1092 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1093 s->io_buffer_index += l; 1094 s->io_buffer_offset += l; 1095 1096 DPRINTF(ad->port_no, "len=%#x\n", l); 1097 1098 return 1; 1099 } 1100 1101 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1102 { 1103 /* only a single unit per link */ 1104 return 0; 1105 } 1106 1107 static int ahci_dma_add_status(IDEDMA *dma, int status) 1108 { 1109 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1110 DPRINTF(ad->port_no, "set status: %x\n", status); 1111 1112 if (status & BM_STATUS_INT) { 1113 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS); 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int ahci_dma_set_inactive(IDEDMA *dma) 1120 { 1121 return 0; 1122 } 1123 1124 static int ahci_async_cmd_done(IDEDMA *dma) 1125 { 1126 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1127 1128 DPRINTF(ad->port_no, "async cmd done\n"); 1129 1130 /* update d2h status */ 1131 ahci_write_fis_d2h(ad, NULL); 1132 1133 if (!ad->check_bh) { 1134 /* maybe we still have something to process, check later */ 1135 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1136 qemu_bh_schedule(ad->check_bh); 1137 } 1138 1139 return 0; 1140 } 1141 1142 static void ahci_irq_set(void *opaque, int n, int level) 1143 { 1144 } 1145 1146 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1147 { 1148 } 1149 1150 static int ahci_dma_reset(IDEDMA *dma) 1151 { 1152 return 0; 1153 } 1154 1155 static const IDEDMAOps ahci_dma_ops = { 1156 .start_dma = ahci_start_dma, 1157 .start_transfer = ahci_start_transfer, 1158 .prepare_buf = ahci_dma_prepare_buf, 1159 .rw_buf = ahci_dma_rw_buf, 1160 .set_unit = ahci_dma_set_unit, 1161 .add_status = ahci_dma_add_status, 1162 .set_inactive = ahci_dma_set_inactive, 1163 .async_cmd_done = ahci_async_cmd_done, 1164 .restart_cb = ahci_dma_restart_cb, 1165 .reset = ahci_dma_reset, 1166 }; 1167 1168 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1169 { 1170 qemu_irq *irqs; 1171 int i; 1172 1173 s->as = as; 1174 s->ports = ports; 1175 s->dev = g_malloc0(sizeof(AHCIDevice) * ports); 1176 ahci_reg_init(s); 1177 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1178 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1179 "ahci", AHCI_MEM_BAR_SIZE); 1180 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1181 "ahci-idp", 32); 1182 1183 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1184 1185 for (i = 0; i < s->ports; i++) { 1186 AHCIDevice *ad = &s->dev[i]; 1187 1188 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1189 ide_init2(&ad->port, irqs[i]); 1190 1191 ad->hba = s; 1192 ad->port_no = i; 1193 ad->port.dma = &ad->dma; 1194 ad->port.dma->ops = &ahci_dma_ops; 1195 } 1196 } 1197 1198 void ahci_uninit(AHCIState *s) 1199 { 1200 g_free(s->dev); 1201 } 1202 1203 void ahci_reset(AHCIState *s) 1204 { 1205 AHCIPortRegs *pr; 1206 int i; 1207 1208 s->control_regs.irqstatus = 0; 1209 /* AHCI Enable (AE) 1210 * The implementation of this bit is dependent upon the value of the 1211 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1212 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1213 * read-only and shall have a reset value of '1'. 1214 * 1215 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1216 */ 1217 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1218 1219 for (i = 0; i < s->ports; i++) { 1220 pr = &s->dev[i].port_regs; 1221 pr->irq_stat = 0; 1222 pr->irq_mask = 0; 1223 pr->scr_ctl = 0; 1224 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1225 ahci_reset_port(s, i); 1226 } 1227 } 1228 1229 static const VMStateDescription vmstate_ahci_device = { 1230 .name = "ahci port", 1231 .version_id = 1, 1232 .fields = (VMStateField[]) { 1233 VMSTATE_IDE_BUS(port, AHCIDevice), 1234 VMSTATE_UINT32(port_state, AHCIDevice), 1235 VMSTATE_UINT32(finished, AHCIDevice), 1236 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1237 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1238 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1239 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1240 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1241 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1242 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1243 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1244 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1245 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1246 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1247 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1248 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1249 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1250 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1251 VMSTATE_INT32(busy_slot, AHCIDevice), 1252 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1253 VMSTATE_END_OF_LIST() 1254 }, 1255 }; 1256 1257 static int ahci_state_post_load(void *opaque, int version_id) 1258 { 1259 int i; 1260 struct AHCIDevice *ad; 1261 AHCIState *s = opaque; 1262 1263 for (i = 0; i < s->ports; i++) { 1264 ad = &s->dev[i]; 1265 AHCIPortRegs *pr = &ad->port_regs; 1266 1267 map_page(s->as, &ad->lst, 1268 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 1269 map_page(s->as, &ad->res_fis, 1270 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 1271 /* 1272 * All pending i/o should be flushed out on a migrate. However, 1273 * we might not have cleared the busy_slot since this is done 1274 * in a bh. Also, issue i/o against any slots that are pending. 1275 */ 1276 if ((ad->busy_slot != -1) && 1277 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 1278 pr->cmd_issue &= ~(1 << ad->busy_slot); 1279 ad->busy_slot = -1; 1280 } 1281 check_cmd(s, i); 1282 } 1283 1284 return 0; 1285 } 1286 1287 const VMStateDescription vmstate_ahci = { 1288 .name = "ahci", 1289 .version_id = 1, 1290 .post_load = ahci_state_post_load, 1291 .fields = (VMStateField[]) { 1292 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1293 vmstate_ahci_device, AHCIDevice), 1294 VMSTATE_UINT32(control_regs.cap, AHCIState), 1295 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1296 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1297 VMSTATE_UINT32(control_regs.impl, AHCIState), 1298 VMSTATE_UINT32(control_regs.version, AHCIState), 1299 VMSTATE_UINT32(idp_index, AHCIState), 1300 VMSTATE_INT32_EQUAL(ports, AHCIState), 1301 VMSTATE_END_OF_LIST() 1302 }, 1303 }; 1304 1305 #define TYPE_SYSBUS_AHCI "sysbus-ahci" 1306 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 1307 1308 typedef struct SysbusAHCIState { 1309 /*< private >*/ 1310 SysBusDevice parent_obj; 1311 /*< public >*/ 1312 1313 AHCIState ahci; 1314 uint32_t num_ports; 1315 } SysbusAHCIState; 1316 1317 static const VMStateDescription vmstate_sysbus_ahci = { 1318 .name = "sysbus-ahci", 1319 .unmigratable = 1, /* Still buggy under I/O load */ 1320 .fields = (VMStateField[]) { 1321 VMSTATE_AHCI(ahci, SysbusAHCIState), 1322 VMSTATE_END_OF_LIST() 1323 }, 1324 }; 1325 1326 static void sysbus_ahci_reset(DeviceState *dev) 1327 { 1328 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1329 1330 ahci_reset(&s->ahci); 1331 } 1332 1333 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1334 { 1335 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1336 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1337 1338 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports); 1339 1340 sysbus_init_mmio(sbd, &s->ahci.mem); 1341 sysbus_init_irq(sbd, &s->ahci.irq); 1342 } 1343 1344 static Property sysbus_ahci_properties[] = { 1345 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1346 DEFINE_PROP_END_OF_LIST(), 1347 }; 1348 1349 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1350 { 1351 DeviceClass *dc = DEVICE_CLASS(klass); 1352 1353 dc->realize = sysbus_ahci_realize; 1354 dc->vmsd = &vmstate_sysbus_ahci; 1355 dc->props = sysbus_ahci_properties; 1356 dc->reset = sysbus_ahci_reset; 1357 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1358 } 1359 1360 static const TypeInfo sysbus_ahci_info = { 1361 .name = TYPE_SYSBUS_AHCI, 1362 .parent = TYPE_SYS_BUS_DEVICE, 1363 .instance_size = sizeof(SysbusAHCIState), 1364 .class_init = sysbus_ahci_class_init, 1365 }; 1366 1367 static void sysbus_ahci_register_types(void) 1368 { 1369 type_register_static(&sysbus_ahci_info); 1370 } 1371 1372 type_init(sysbus_ahci_register_types) 1373