1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include <hw/hw.h> 25 #include <hw/pci/msi.h> 26 #include <hw/i386/pc.h> 27 #include <hw/pci/pci.h> 28 #include <hw/sysbus.h> 29 30 #include "monitor/monitor.h" 31 #include "sysemu/dma.h" 32 #include "internal.h" 33 #include <hw/ide/pci.h> 34 #include <hw/ide/ahci.h> 35 36 /* #define DEBUG_AHCI */ 37 38 #ifdef DEBUG_AHCI 39 #define DPRINTF(port, fmt, ...) \ 40 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \ 41 fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(port, fmt, ...) do {} while(0) 44 #endif 45 46 static void check_cmd(AHCIState *s, int port); 47 static int handle_cmd(AHCIState *s,int port,int slot); 48 static void ahci_reset_port(AHCIState *s, int port); 49 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis); 50 static void ahci_init_d2h(AHCIDevice *ad); 51 52 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 53 { 54 uint32_t val; 55 AHCIPortRegs *pr; 56 pr = &s->dev[port].port_regs; 57 58 switch (offset) { 59 case PORT_LST_ADDR: 60 val = pr->lst_addr; 61 break; 62 case PORT_LST_ADDR_HI: 63 val = pr->lst_addr_hi; 64 break; 65 case PORT_FIS_ADDR: 66 val = pr->fis_addr; 67 break; 68 case PORT_FIS_ADDR_HI: 69 val = pr->fis_addr_hi; 70 break; 71 case PORT_IRQ_STAT: 72 val = pr->irq_stat; 73 break; 74 case PORT_IRQ_MASK: 75 val = pr->irq_mask; 76 break; 77 case PORT_CMD: 78 val = pr->cmd; 79 break; 80 case PORT_TFDATA: 81 val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) | 82 s->dev[port].port.ifs[0].status; 83 break; 84 case PORT_SIG: 85 val = pr->sig; 86 break; 87 case PORT_SCR_STAT: 88 if (s->dev[port].port.ifs[0].bs) { 89 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 90 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 91 } else { 92 val = SATA_SCR_SSTATUS_DET_NODEV; 93 } 94 break; 95 case PORT_SCR_CTL: 96 val = pr->scr_ctl; 97 break; 98 case PORT_SCR_ERR: 99 val = pr->scr_err; 100 break; 101 case PORT_SCR_ACT: 102 pr->scr_act &= ~s->dev[port].finished; 103 s->dev[port].finished = 0; 104 val = pr->scr_act; 105 break; 106 case PORT_CMD_ISSUE: 107 val = pr->cmd_issue; 108 break; 109 case PORT_RESERVED: 110 default: 111 val = 0; 112 } 113 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 114 return val; 115 116 } 117 118 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev) 119 { 120 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 121 PCIDevice *pci_dev = 122 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 123 124 DPRINTF(0, "raise irq\n"); 125 126 if (pci_dev && msi_enabled(pci_dev)) { 127 msi_notify(pci_dev, 0); 128 } else { 129 qemu_irq_raise(s->irq); 130 } 131 } 132 133 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev) 134 { 135 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci); 136 PCIDevice *pci_dev = 137 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE); 138 139 DPRINTF(0, "lower irq\n"); 140 141 if (!pci_dev || !msi_enabled(pci_dev)) { 142 qemu_irq_lower(s->irq); 143 } 144 } 145 146 static void ahci_check_irq(AHCIState *s) 147 { 148 int i; 149 150 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus); 151 152 s->control_regs.irqstatus = 0; 153 for (i = 0; i < s->ports; i++) { 154 AHCIPortRegs *pr = &s->dev[i].port_regs; 155 if (pr->irq_stat & pr->irq_mask) { 156 s->control_regs.irqstatus |= (1 << i); 157 } 158 } 159 160 if (s->control_regs.irqstatus && 161 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 162 ahci_irq_raise(s, NULL); 163 } else { 164 ahci_irq_lower(s, NULL); 165 } 166 } 167 168 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 169 int irq_type) 170 { 171 DPRINTF(d->port_no, "trigger irq %#x -> %x\n", 172 irq_type, d->port_regs.irq_mask & irq_type); 173 174 d->port_regs.irq_stat |= irq_type; 175 ahci_check_irq(s); 176 } 177 178 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 179 uint32_t wanted) 180 { 181 hwaddr len = wanted; 182 183 if (*ptr) { 184 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 185 } 186 187 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); 188 if (len < wanted) { 189 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 190 *ptr = NULL; 191 } 192 } 193 194 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 195 { 196 AHCIPortRegs *pr = &s->dev[port].port_regs; 197 198 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val); 199 switch (offset) { 200 case PORT_LST_ADDR: 201 pr->lst_addr = val; 202 map_page(s->as, &s->dev[port].lst, 203 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 204 s->dev[port].cur_cmd = NULL; 205 break; 206 case PORT_LST_ADDR_HI: 207 pr->lst_addr_hi = val; 208 map_page(s->as, &s->dev[port].lst, 209 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 210 s->dev[port].cur_cmd = NULL; 211 break; 212 case PORT_FIS_ADDR: 213 pr->fis_addr = val; 214 map_page(s->as, &s->dev[port].res_fis, 215 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 216 break; 217 case PORT_FIS_ADDR_HI: 218 pr->fis_addr_hi = val; 219 map_page(s->as, &s->dev[port].res_fis, 220 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 221 break; 222 case PORT_IRQ_STAT: 223 pr->irq_stat &= ~val; 224 ahci_check_irq(s); 225 break; 226 case PORT_IRQ_MASK: 227 pr->irq_mask = val & 0xfdc000ff; 228 ahci_check_irq(s); 229 break; 230 case PORT_CMD: 231 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 232 233 if (pr->cmd & PORT_CMD_START) { 234 pr->cmd |= PORT_CMD_LIST_ON; 235 } 236 237 if (pr->cmd & PORT_CMD_FIS_RX) { 238 pr->cmd |= PORT_CMD_FIS_ON; 239 } 240 241 /* XXX usually the FIS would be pending on the bus here and 242 issuing deferred until the OS enables FIS receival. 243 Instead, we only submit it once - which works in most 244 cases, but is a hack. */ 245 if ((pr->cmd & PORT_CMD_FIS_ON) && 246 !s->dev[port].init_d2h_sent) { 247 ahci_init_d2h(&s->dev[port]); 248 s->dev[port].init_d2h_sent = true; 249 } 250 251 check_cmd(s, port); 252 break; 253 case PORT_TFDATA: 254 s->dev[port].port.ifs[0].error = (val >> 8) & 0xff; 255 s->dev[port].port.ifs[0].status = val & 0xff; 256 break; 257 case PORT_SIG: 258 pr->sig = val; 259 break; 260 case PORT_SCR_STAT: 261 pr->scr_stat = val; 262 break; 263 case PORT_SCR_CTL: 264 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 265 ((val & AHCI_SCR_SCTL_DET) == 0)) { 266 ahci_reset_port(s, port); 267 } 268 pr->scr_ctl = val; 269 break; 270 case PORT_SCR_ERR: 271 pr->scr_err &= ~val; 272 break; 273 case PORT_SCR_ACT: 274 /* RW1 */ 275 pr->scr_act |= val; 276 break; 277 case PORT_CMD_ISSUE: 278 pr->cmd_issue |= val; 279 check_cmd(s, port); 280 break; 281 default: 282 break; 283 } 284 } 285 286 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 287 unsigned size) 288 { 289 AHCIState *s = opaque; 290 uint32_t val = 0; 291 292 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 293 switch (addr) { 294 case HOST_CAP: 295 val = s->control_regs.cap; 296 break; 297 case HOST_CTL: 298 val = s->control_regs.ghc; 299 break; 300 case HOST_IRQ_STAT: 301 val = s->control_regs.irqstatus; 302 break; 303 case HOST_PORTS_IMPL: 304 val = s->control_regs.impl; 305 break; 306 case HOST_VERSION: 307 val = s->control_regs.version; 308 break; 309 } 310 311 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); 312 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 313 (addr < (AHCI_PORT_REGS_START_ADDR + 314 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 315 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 316 addr & AHCI_PORT_ADDR_OFFSET_MASK); 317 } 318 319 return val; 320 } 321 322 323 324 static void ahci_mem_write(void *opaque, hwaddr addr, 325 uint64_t val, unsigned size) 326 { 327 AHCIState *s = opaque; 328 329 /* Only aligned reads are allowed on AHCI */ 330 if (addr & 3) { 331 fprintf(stderr, "ahci: Mis-aligned write to addr 0x" 332 TARGET_FMT_plx "\n", addr); 333 return; 334 } 335 336 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 337 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val); 338 339 switch (addr) { 340 case HOST_CAP: /* R/WO, RO */ 341 /* FIXME handle R/WO */ 342 break; 343 case HOST_CTL: /* R/W */ 344 if (val & HOST_CTL_RESET) { 345 DPRINTF(-1, "HBA Reset\n"); 346 ahci_reset(s); 347 } else { 348 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 349 ahci_check_irq(s); 350 } 351 break; 352 case HOST_IRQ_STAT: /* R/WC, RO */ 353 s->control_regs.irqstatus &= ~val; 354 ahci_check_irq(s); 355 break; 356 case HOST_PORTS_IMPL: /* R/WO, RO */ 357 /* FIXME handle R/WO */ 358 break; 359 case HOST_VERSION: /* RO */ 360 /* FIXME report write? */ 361 break; 362 default: 363 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr); 364 } 365 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 366 (addr < (AHCI_PORT_REGS_START_ADDR + 367 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 368 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 369 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 370 } 371 372 } 373 374 static const MemoryRegionOps ahci_mem_ops = { 375 .read = ahci_mem_read, 376 .write = ahci_mem_write, 377 .endianness = DEVICE_LITTLE_ENDIAN, 378 }; 379 380 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 381 unsigned size) 382 { 383 AHCIState *s = opaque; 384 385 if (addr == s->idp_offset) { 386 /* index register */ 387 return s->idp_index; 388 } else if (addr == s->idp_offset + 4) { 389 /* data register - do memory read at location selected by index */ 390 return ahci_mem_read(opaque, s->idp_index, size); 391 } else { 392 return 0; 393 } 394 } 395 396 static void ahci_idp_write(void *opaque, hwaddr addr, 397 uint64_t val, unsigned size) 398 { 399 AHCIState *s = opaque; 400 401 if (addr == s->idp_offset) { 402 /* index register - mask off reserved bits */ 403 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 404 } else if (addr == s->idp_offset + 4) { 405 /* data register - do memory write at location selected by index */ 406 ahci_mem_write(opaque, s->idp_index, val, size); 407 } 408 } 409 410 static const MemoryRegionOps ahci_idp_ops = { 411 .read = ahci_idp_read, 412 .write = ahci_idp_write, 413 .endianness = DEVICE_LITTLE_ENDIAN, 414 }; 415 416 417 static void ahci_reg_init(AHCIState *s) 418 { 419 int i; 420 421 s->control_regs.cap = (s->ports - 1) | 422 (AHCI_NUM_COMMAND_SLOTS << 8) | 423 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 424 HOST_CAP_NCQ | HOST_CAP_AHCI; 425 426 s->control_regs.impl = (1 << s->ports) - 1; 427 428 s->control_regs.version = AHCI_VERSION_1_0; 429 430 for (i = 0; i < s->ports; i++) { 431 s->dev[i].port_state = STATE_RUN; 432 } 433 } 434 435 static void check_cmd(AHCIState *s, int port) 436 { 437 AHCIPortRegs *pr = &s->dev[port].port_regs; 438 int slot; 439 440 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 441 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 442 if ((pr->cmd_issue & (1U << slot)) && 443 !handle_cmd(s, port, slot)) { 444 pr->cmd_issue &= ~(1U << slot); 445 } 446 } 447 } 448 } 449 450 static void ahci_check_cmd_bh(void *opaque) 451 { 452 AHCIDevice *ad = opaque; 453 454 qemu_bh_delete(ad->check_bh); 455 ad->check_bh = NULL; 456 457 if ((ad->busy_slot != -1) && 458 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 459 /* no longer busy */ 460 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); 461 ad->busy_slot = -1; 462 } 463 464 check_cmd(ad->hba, ad->port_no); 465 } 466 467 static void ahci_init_d2h(AHCIDevice *ad) 468 { 469 uint8_t init_fis[20]; 470 IDEState *ide_state = &ad->port.ifs[0]; 471 472 memset(init_fis, 0, sizeof(init_fis)); 473 474 init_fis[4] = 1; 475 init_fis[12] = 1; 476 477 if (ide_state->drive_kind == IDE_CD) { 478 init_fis[5] = ide_state->lcyl; 479 init_fis[6] = ide_state->hcyl; 480 } 481 482 ahci_write_fis_d2h(ad, init_fis); 483 } 484 485 static void ahci_reset_port(AHCIState *s, int port) 486 { 487 AHCIDevice *d = &s->dev[port]; 488 AHCIPortRegs *pr = &d->port_regs; 489 IDEState *ide_state = &d->port.ifs[0]; 490 int i; 491 492 DPRINTF(port, "reset port\n"); 493 494 ide_bus_reset(&d->port); 495 ide_state->ncq_queues = AHCI_MAX_CMDS; 496 497 pr->scr_stat = 0; 498 pr->scr_err = 0; 499 pr->scr_act = 0; 500 d->busy_slot = -1; 501 d->init_d2h_sent = false; 502 503 ide_state = &s->dev[port].port.ifs[0]; 504 if (!ide_state->bs) { 505 return; 506 } 507 508 /* reset ncq queue */ 509 for (i = 0; i < AHCI_MAX_CMDS; i++) { 510 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 511 if (!ncq_tfs->used) { 512 continue; 513 } 514 515 if (ncq_tfs->aiocb) { 516 bdrv_aio_cancel(ncq_tfs->aiocb); 517 ncq_tfs->aiocb = NULL; 518 } 519 520 /* Maybe we just finished the request thanks to bdrv_aio_cancel() */ 521 if (!ncq_tfs->used) { 522 continue; 523 } 524 525 qemu_sglist_destroy(&ncq_tfs->sglist); 526 ncq_tfs->used = 0; 527 } 528 529 s->dev[port].port_state = STATE_RUN; 530 if (!ide_state->bs) { 531 s->dev[port].port_regs.sig = 0; 532 ide_state->status = SEEK_STAT | WRERR_STAT; 533 } else if (ide_state->drive_kind == IDE_CD) { 534 s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM; 535 ide_state->lcyl = 0x14; 536 ide_state->hcyl = 0xeb; 537 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl); 538 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 539 } else { 540 s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK; 541 ide_state->status = SEEK_STAT | WRERR_STAT; 542 } 543 544 ide_state->error = 1; 545 ahci_init_d2h(d); 546 } 547 548 static void debug_print_fis(uint8_t *fis, int cmd_len) 549 { 550 #ifdef DEBUG_AHCI 551 int i; 552 553 fprintf(stderr, "fis:"); 554 for (i = 0; i < cmd_len; i++) { 555 if ((i & 0xf) == 0) { 556 fprintf(stderr, "\n%02x:",i); 557 } 558 fprintf(stderr, "%02x ",fis[i]); 559 } 560 fprintf(stderr, "\n"); 561 #endif 562 } 563 564 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 565 { 566 AHCIPortRegs *pr = &s->dev[port].port_regs; 567 IDEState *ide_state; 568 uint8_t *sdb_fis; 569 570 if (!s->dev[port].res_fis || 571 !(pr->cmd & PORT_CMD_FIS_RX)) { 572 return; 573 } 574 575 sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS]; 576 ide_state = &s->dev[port].port.ifs[0]; 577 578 /* clear memory */ 579 *(uint32_t*)sdb_fis = 0; 580 581 /* write values */ 582 sdb_fis[0] = ide_state->error; 583 sdb_fis[2] = ide_state->status & 0x77; 584 s->dev[port].finished |= finished; 585 *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished); 586 587 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_SDB_FIS); 588 } 589 590 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) 591 { 592 AHCIPortRegs *pr = &ad->port_regs; 593 uint8_t *pio_fis, *cmd_fis; 594 uint64_t tbl_addr; 595 dma_addr_t cmd_len = 0x80; 596 597 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 598 return; 599 } 600 601 /* map cmd_fis */ 602 tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 603 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 604 DMA_DIRECTION_TO_DEVICE); 605 606 if (cmd_fis == NULL) { 607 DPRINTF(ad->port_no, "dma_memory_map failed in ahci_write_fis_pio"); 608 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR); 609 return; 610 } 611 612 if (cmd_len != 0x80) { 613 DPRINTF(ad->port_no, 614 "dma_memory_map mapped too few bytes in ahci_write_fis_pio"); 615 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 616 DMA_DIRECTION_TO_DEVICE, cmd_len); 617 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR); 618 return; 619 } 620 621 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 622 623 pio_fis[0] = 0x5f; 624 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 625 pio_fis[2] = ad->port.ifs[0].status; 626 pio_fis[3] = ad->port.ifs[0].error; 627 628 pio_fis[4] = cmd_fis[4]; 629 pio_fis[5] = cmd_fis[5]; 630 pio_fis[6] = cmd_fis[6]; 631 pio_fis[7] = cmd_fis[7]; 632 pio_fis[8] = cmd_fis[8]; 633 pio_fis[9] = cmd_fis[9]; 634 pio_fis[10] = cmd_fis[10]; 635 pio_fis[11] = cmd_fis[11]; 636 pio_fis[12] = cmd_fis[12]; 637 pio_fis[13] = cmd_fis[13]; 638 pio_fis[14] = 0; 639 pio_fis[15] = ad->port.ifs[0].status; 640 pio_fis[16] = len & 255; 641 pio_fis[17] = len >> 8; 642 pio_fis[18] = 0; 643 pio_fis[19] = 0; 644 645 if (pio_fis[2] & ERR_STAT) { 646 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 647 } 648 649 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS); 650 651 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 652 DMA_DIRECTION_TO_DEVICE, cmd_len); 653 } 654 655 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 656 { 657 AHCIPortRegs *pr = &ad->port_regs; 658 uint8_t *d2h_fis; 659 int i; 660 dma_addr_t cmd_len = 0x80; 661 int cmd_mapped = 0; 662 663 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 664 return; 665 } 666 667 if (!cmd_fis) { 668 /* map cmd_fis */ 669 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr); 670 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len, 671 DMA_DIRECTION_TO_DEVICE); 672 cmd_mapped = 1; 673 } 674 675 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 676 677 d2h_fis[0] = 0x34; 678 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0); 679 d2h_fis[2] = ad->port.ifs[0].status; 680 d2h_fis[3] = ad->port.ifs[0].error; 681 682 d2h_fis[4] = cmd_fis[4]; 683 d2h_fis[5] = cmd_fis[5]; 684 d2h_fis[6] = cmd_fis[6]; 685 d2h_fis[7] = cmd_fis[7]; 686 d2h_fis[8] = cmd_fis[8]; 687 d2h_fis[9] = cmd_fis[9]; 688 d2h_fis[10] = cmd_fis[10]; 689 d2h_fis[11] = cmd_fis[11]; 690 d2h_fis[12] = cmd_fis[12]; 691 d2h_fis[13] = cmd_fis[13]; 692 for (i = 14; i < 20; i++) { 693 d2h_fis[i] = 0; 694 } 695 696 if (d2h_fis[2] & ERR_STAT) { 697 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR); 698 } 699 700 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS); 701 702 if (cmd_mapped) { 703 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len, 704 DMA_DIRECTION_TO_DEVICE, cmd_len); 705 } 706 } 707 708 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 709 { 710 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 711 } 712 713 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset) 714 { 715 AHCICmdHdr *cmd = ad->cur_cmd; 716 uint32_t opts = le32_to_cpu(cmd->opts); 717 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80; 718 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN; 719 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG)); 720 dma_addr_t real_prdt_len = prdt_len; 721 uint8_t *prdt; 722 int i; 723 int r = 0; 724 int sum = 0; 725 int off_idx = -1; 726 int off_pos = -1; 727 int tbl_entry_size; 728 IDEBus *bus = &ad->port; 729 BusState *qbus = BUS(bus); 730 731 if (!sglist_alloc_hint) { 732 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts); 733 return -1; 734 } 735 736 /* map PRDT */ 737 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 738 DMA_DIRECTION_TO_DEVICE))){ 739 DPRINTF(ad->port_no, "map failed\n"); 740 return -1; 741 } 742 743 if (prdt_len < real_prdt_len) { 744 DPRINTF(ad->port_no, "mapped less than expected\n"); 745 r = -1; 746 goto out; 747 } 748 749 /* Get entries in the PRDT, init a qemu sglist accordingly */ 750 if (sglist_alloc_hint > 0) { 751 AHCI_SG *tbl = (AHCI_SG *)prdt; 752 sum = 0; 753 for (i = 0; i < sglist_alloc_hint; i++) { 754 /* flags_size is zero-based */ 755 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 756 if (offset <= (sum + tbl_entry_size)) { 757 off_idx = i; 758 off_pos = offset - sum; 759 break; 760 } 761 sum += tbl_entry_size; 762 } 763 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 764 DPRINTF(ad->port_no, "%s: Incorrect offset! " 765 "off_idx: %d, off_pos: %d\n", 766 __func__, off_idx, off_pos); 767 r = -1; 768 goto out; 769 } 770 771 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx), 772 ad->hba->as); 773 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos), 774 prdt_tbl_entry_size(&tbl[off_idx]) - off_pos); 775 776 for (i = off_idx + 1; i < sglist_alloc_hint; i++) { 777 /* flags_size is zero-based */ 778 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 779 prdt_tbl_entry_size(&tbl[i])); 780 } 781 } 782 783 out: 784 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 785 DMA_DIRECTION_TO_DEVICE, prdt_len); 786 return r; 787 } 788 789 static void ncq_cb(void *opaque, int ret) 790 { 791 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 792 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 793 794 if (ret == -ECANCELED) { 795 return; 796 } 797 /* Clear bit for this tag in SActive */ 798 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag); 799 800 if (ret < 0) { 801 /* error */ 802 ide_state->error = ABRT_ERR; 803 ide_state->status = READY_STAT | ERR_STAT; 804 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 805 } else { 806 ide_state->status = READY_STAT | SEEK_STAT; 807 } 808 809 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 810 (1 << ncq_tfs->tag)); 811 812 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n", 813 ncq_tfs->tag); 814 815 block_acct_done(bdrv_get_stats(ncq_tfs->drive->port.ifs[0].bs), 816 &ncq_tfs->acct); 817 qemu_sglist_destroy(&ncq_tfs->sglist); 818 ncq_tfs->used = 0; 819 } 820 821 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 822 int slot) 823 { 824 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis; 825 uint8_t tag = ncq_fis->tag >> 3; 826 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag]; 827 828 if (ncq_tfs->used) { 829 /* error - already in use */ 830 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag); 831 return; 832 } 833 834 ncq_tfs->used = 1; 835 ncq_tfs->drive = &s->dev[port]; 836 ncq_tfs->slot = slot; 837 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 838 ((uint64_t)ncq_fis->lba4 << 32) | 839 ((uint64_t)ncq_fis->lba3 << 24) | 840 ((uint64_t)ncq_fis->lba2 << 16) | 841 ((uint64_t)ncq_fis->lba1 << 8) | 842 (uint64_t)ncq_fis->lba0; 843 844 /* Note: We calculate the sector count, but don't currently rely on it. 845 * The total size of the DMA buffer tells us the transfer size instead. */ 846 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) | 847 ncq_fis->sector_count_low; 848 849 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", " 850 "drive max %"PRId64"\n", 851 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2, 852 s->dev[port].port.ifs[0].nb_sectors - 1); 853 854 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0); 855 ncq_tfs->tag = tag; 856 857 switch(ncq_fis->command) { 858 case READ_FPDMA_QUEUED: 859 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", " 860 "tag %d\n", 861 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 862 863 DPRINTF(port, "tag %d aio read %"PRId64"\n", 864 ncq_tfs->tag, ncq_tfs->lba); 865 866 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 867 &ncq_tfs->sglist, BLOCK_ACCT_READ); 868 ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, 869 &ncq_tfs->sglist, ncq_tfs->lba, 870 ncq_cb, ncq_tfs); 871 break; 872 case WRITE_FPDMA_QUEUED: 873 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n", 874 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag); 875 876 DPRINTF(port, "tag %d aio write %"PRId64"\n", 877 ncq_tfs->tag, ncq_tfs->lba); 878 879 dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct, 880 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 881 ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, 882 &ncq_tfs->sglist, ncq_tfs->lba, 883 ncq_cb, ncq_tfs); 884 break; 885 default: 886 DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n"); 887 qemu_sglist_destroy(&ncq_tfs->sglist); 888 break; 889 } 890 } 891 892 static int handle_cmd(AHCIState *s, int port, int slot) 893 { 894 IDEState *ide_state; 895 uint32_t opts; 896 uint64_t tbl_addr; 897 AHCICmdHdr *cmd; 898 uint8_t *cmd_fis; 899 dma_addr_t cmd_len; 900 901 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 902 /* Engine currently busy, try again later */ 903 DPRINTF(port, "engine busy\n"); 904 return -1; 905 } 906 907 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot]; 908 909 if (!s->dev[port].lst) { 910 DPRINTF(port, "error: lst not given but cmd handled"); 911 return -1; 912 } 913 914 /* remember current slot handle for later */ 915 s->dev[port].cur_cmd = cmd; 916 917 opts = le32_to_cpu(cmd->opts); 918 tbl_addr = le64_to_cpu(cmd->tbl_addr); 919 920 cmd_len = 0x80; 921 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 922 DMA_DIRECTION_FROM_DEVICE); 923 924 if (!cmd_fis) { 925 DPRINTF(port, "error: guest passed us an invalid cmd fis\n"); 926 return -1; 927 } 928 929 /* The device we are working for */ 930 ide_state = &s->dev[port].port.ifs[0]; 931 932 if (!ide_state->bs) { 933 DPRINTF(port, "error: guest accessed unused port"); 934 goto out; 935 } 936 937 debug_print_fis(cmd_fis, 0x90); 938 //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4); 939 940 switch (cmd_fis[0]) { 941 case SATA_FIS_TYPE_REGISTER_H2D: 942 break; 943 default: 944 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 945 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 946 cmd_fis[2]); 947 goto out; 948 break; 949 } 950 951 switch (cmd_fis[1]) { 952 case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER: 953 break; 954 case 0: 955 break; 956 default: 957 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x " 958 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1], 959 cmd_fis[2]); 960 goto out; 961 break; 962 } 963 964 switch (s->dev[port].port_state) { 965 case STATE_RUN: 966 if (cmd_fis[15] & ATA_SRST) { 967 s->dev[port].port_state = STATE_RESET; 968 } 969 break; 970 case STATE_RESET: 971 if (!(cmd_fis[15] & ATA_SRST)) { 972 ahci_reset_port(s, port); 973 } 974 break; 975 } 976 977 if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) { 978 979 /* Check for NCQ command */ 980 if ((cmd_fis[2] == READ_FPDMA_QUEUED) || 981 (cmd_fis[2] == WRITE_FPDMA_QUEUED)) { 982 process_ncq_command(s, port, cmd_fis, slot); 983 goto out; 984 } 985 986 /* Decompose the FIS */ 987 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 988 ide_state->feature = cmd_fis[3]; 989 if (!ide_state->nsector) { 990 ide_state->nsector = 256; 991 } 992 993 if (ide_state->drive_kind != IDE_CD) { 994 /* 995 * We set the sector depending on the sector defined in the FIS. 996 * Unfortunately, the spec isn't exactly obvious on this one. 997 * 998 * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the 999 * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for 1000 * such a command. 1001 * 1002 * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a 1003 * 28-bit sector number. ATA_CMD_READ_DMA is an example for such 1004 * a command. 1005 * 1006 * Since the spec doesn't explicitly state what each field should 1007 * do, I simply assume non-used fields as reserved and OR everything 1008 * together, independent of the command. 1009 */ 1010 ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40) 1011 | ((uint64_t)cmd_fis[9] << 32) 1012 /* This is used for LBA48 commands */ 1013 | ((uint64_t)cmd_fis[8] << 24) 1014 /* This is used for non-LBA48 commands */ 1015 | ((uint64_t)(cmd_fis[7] & 0xf) << 24) 1016 | ((uint64_t)cmd_fis[6] << 16) 1017 | ((uint64_t)cmd_fis[5] << 8) 1018 | cmd_fis[4]); 1019 } 1020 1021 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1022 * table to ide_state->io_buffer 1023 */ 1024 if (opts & AHCI_CMD_ATAPI) { 1025 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1026 ide_state->lcyl = 0x14; 1027 ide_state->hcyl = 0xeb; 1028 debug_print_fis(ide_state->io_buffer, 0x10); 1029 ide_state->feature = IDE_FEATURE_DMA; 1030 s->dev[port].done_atapi_packet = false; 1031 /* XXX send PIO setup FIS */ 1032 } 1033 1034 ide_state->error = 0; 1035 1036 /* Reset transferred byte counter */ 1037 cmd->status = 0; 1038 1039 /* We're ready to process the command in FIS byte 2. */ 1040 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1041 } 1042 1043 out: 1044 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE, 1045 cmd_len); 1046 1047 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1048 /* async command, complete later */ 1049 s->dev[port].busy_slot = slot; 1050 return -1; 1051 } 1052 1053 /* done handling the command */ 1054 return 0; 1055 } 1056 1057 /* DMA dev <-> ram */ 1058 static void ahci_start_transfer(IDEDMA *dma) 1059 { 1060 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1061 IDEState *s = &ad->port.ifs[0]; 1062 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1063 /* write == ram -> device */ 1064 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts); 1065 int is_write = opts & AHCI_CMD_WRITE; 1066 int is_atapi = opts & AHCI_CMD_ATAPI; 1067 int has_sglist = 0; 1068 1069 if (is_atapi && !ad->done_atapi_packet) { 1070 /* already prepopulated iobuffer */ 1071 ad->done_atapi_packet = true; 1072 goto out; 1073 } 1074 1075 if (!ahci_populate_sglist(ad, &s->sg, 0)) { 1076 has_sglist = 1; 1077 } 1078 1079 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n", 1080 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata", 1081 has_sglist ? "" : "o"); 1082 1083 if (has_sglist && size) { 1084 if (is_write) { 1085 dma_buf_write(s->data_ptr, size, &s->sg); 1086 } else { 1087 dma_buf_read(s->data_ptr, size, &s->sg); 1088 } 1089 } 1090 1091 /* update number of transferred bytes */ 1092 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size); 1093 1094 out: 1095 /* declare that we processed everything */ 1096 s->data_ptr = s->data_end; 1097 1098 if (has_sglist) { 1099 qemu_sglist_destroy(&s->sg); 1100 } 1101 1102 s->end_transfer_func(s); 1103 1104 if (!(s->status & DRQ_STAT)) { 1105 /* done with PIO send/receive */ 1106 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status)); 1107 } 1108 } 1109 1110 static void ahci_start_dma(IDEDMA *dma, IDEState *s, 1111 BlockDriverCompletionFunc *dma_cb) 1112 { 1113 #ifdef DEBUG_AHCI 1114 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1115 #endif 1116 DPRINTF(ad->port_no, "\n"); 1117 s->io_buffer_offset = 0; 1118 dma_cb(s, 0); 1119 } 1120 1121 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write) 1122 { 1123 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1124 IDEState *s = &ad->port.ifs[0]; 1125 1126 ahci_populate_sglist(ad, &s->sg, 0); 1127 s->io_buffer_size = s->sg.size; 1128 1129 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size); 1130 return s->io_buffer_size != 0; 1131 } 1132 1133 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 1134 { 1135 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1136 IDEState *s = &ad->port.ifs[0]; 1137 uint8_t *p = s->io_buffer + s->io_buffer_index; 1138 int l = s->io_buffer_size - s->io_buffer_index; 1139 1140 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) { 1141 return 0; 1142 } 1143 1144 if (is_write) { 1145 dma_buf_read(p, l, &s->sg); 1146 } else { 1147 dma_buf_write(p, l, &s->sg); 1148 } 1149 1150 /* free sglist that was created in ahci_populate_sglist() */ 1151 qemu_sglist_destroy(&s->sg); 1152 1153 /* update number of transferred bytes */ 1154 ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l); 1155 s->io_buffer_index += l; 1156 s->io_buffer_offset += l; 1157 1158 DPRINTF(ad->port_no, "len=%#x\n", l); 1159 1160 return 1; 1161 } 1162 1163 static int ahci_dma_set_unit(IDEDMA *dma, int unit) 1164 { 1165 /* only a single unit per link */ 1166 return 0; 1167 } 1168 1169 static void ahci_cmd_done(IDEDMA *dma) 1170 { 1171 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1172 1173 DPRINTF(ad->port_no, "cmd done\n"); 1174 1175 /* update d2h status */ 1176 ahci_write_fis_d2h(ad, NULL); 1177 1178 if (!ad->check_bh) { 1179 /* maybe we still have something to process, check later */ 1180 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad); 1181 qemu_bh_schedule(ad->check_bh); 1182 } 1183 } 1184 1185 static void ahci_irq_set(void *opaque, int n, int level) 1186 { 1187 } 1188 1189 static void ahci_dma_restart_cb(void *opaque, int running, RunState state) 1190 { 1191 } 1192 1193 static const IDEDMAOps ahci_dma_ops = { 1194 .start_dma = ahci_start_dma, 1195 .start_transfer = ahci_start_transfer, 1196 .prepare_buf = ahci_dma_prepare_buf, 1197 .rw_buf = ahci_dma_rw_buf, 1198 .set_unit = ahci_dma_set_unit, 1199 .cmd_done = ahci_cmd_done, 1200 .restart_cb = ahci_dma_restart_cb, 1201 }; 1202 1203 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1204 { 1205 qemu_irq *irqs; 1206 int i; 1207 1208 s->as = as; 1209 s->ports = ports; 1210 s->dev = g_new0(AHCIDevice, ports); 1211 ahci_reg_init(s); 1212 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1213 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1214 "ahci", AHCI_MEM_BAR_SIZE); 1215 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1216 "ahci-idp", 32); 1217 1218 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1219 1220 for (i = 0; i < s->ports; i++) { 1221 AHCIDevice *ad = &s->dev[i]; 1222 1223 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); 1224 ide_init2(&ad->port, irqs[i]); 1225 1226 ad->hba = s; 1227 ad->port_no = i; 1228 ad->port.dma = &ad->dma; 1229 ad->port.dma->ops = &ahci_dma_ops; 1230 } 1231 } 1232 1233 void ahci_uninit(AHCIState *s) 1234 { 1235 g_free(s->dev); 1236 } 1237 1238 void ahci_reset(AHCIState *s) 1239 { 1240 AHCIPortRegs *pr; 1241 int i; 1242 1243 s->control_regs.irqstatus = 0; 1244 /* AHCI Enable (AE) 1245 * The implementation of this bit is dependent upon the value of the 1246 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1247 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1248 * read-only and shall have a reset value of '1'. 1249 * 1250 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1251 */ 1252 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1253 1254 for (i = 0; i < s->ports; i++) { 1255 pr = &s->dev[i].port_regs; 1256 pr->irq_stat = 0; 1257 pr->irq_mask = 0; 1258 pr->scr_ctl = 0; 1259 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1260 ahci_reset_port(s, i); 1261 } 1262 } 1263 1264 static const VMStateDescription vmstate_ahci_device = { 1265 .name = "ahci port", 1266 .version_id = 1, 1267 .fields = (VMStateField[]) { 1268 VMSTATE_IDE_BUS(port, AHCIDevice), 1269 VMSTATE_UINT32(port_state, AHCIDevice), 1270 VMSTATE_UINT32(finished, AHCIDevice), 1271 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1272 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1273 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1274 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1275 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1276 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1277 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1278 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1279 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1280 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1281 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1282 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1283 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1284 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1285 VMSTATE_BOOL(done_atapi_packet, AHCIDevice), 1286 VMSTATE_INT32(busy_slot, AHCIDevice), 1287 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1288 VMSTATE_END_OF_LIST() 1289 }, 1290 }; 1291 1292 static int ahci_state_post_load(void *opaque, int version_id) 1293 { 1294 int i; 1295 struct AHCIDevice *ad; 1296 AHCIState *s = opaque; 1297 1298 for (i = 0; i < s->ports; i++) { 1299 ad = &s->dev[i]; 1300 AHCIPortRegs *pr = &ad->port_regs; 1301 1302 map_page(s->as, &ad->lst, 1303 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 1304 map_page(s->as, &ad->res_fis, 1305 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 1306 /* 1307 * All pending i/o should be flushed out on a migrate. However, 1308 * we might not have cleared the busy_slot since this is done 1309 * in a bh. Also, issue i/o against any slots that are pending. 1310 */ 1311 if ((ad->busy_slot != -1) && 1312 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) { 1313 pr->cmd_issue &= ~(1 << ad->busy_slot); 1314 ad->busy_slot = -1; 1315 } 1316 check_cmd(s, i); 1317 } 1318 1319 return 0; 1320 } 1321 1322 const VMStateDescription vmstate_ahci = { 1323 .name = "ahci", 1324 .version_id = 1, 1325 .post_load = ahci_state_post_load, 1326 .fields = (VMStateField[]) { 1327 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1328 vmstate_ahci_device, AHCIDevice), 1329 VMSTATE_UINT32(control_regs.cap, AHCIState), 1330 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1331 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1332 VMSTATE_UINT32(control_regs.impl, AHCIState), 1333 VMSTATE_UINT32(control_regs.version, AHCIState), 1334 VMSTATE_UINT32(idp_index, AHCIState), 1335 VMSTATE_INT32_EQUAL(ports, AHCIState), 1336 VMSTATE_END_OF_LIST() 1337 }, 1338 }; 1339 1340 #define TYPE_SYSBUS_AHCI "sysbus-ahci" 1341 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 1342 1343 typedef struct SysbusAHCIState { 1344 /*< private >*/ 1345 SysBusDevice parent_obj; 1346 /*< public >*/ 1347 1348 AHCIState ahci; 1349 uint32_t num_ports; 1350 } SysbusAHCIState; 1351 1352 static const VMStateDescription vmstate_sysbus_ahci = { 1353 .name = "sysbus-ahci", 1354 .unmigratable = 1, /* Still buggy under I/O load */ 1355 .fields = (VMStateField[]) { 1356 VMSTATE_AHCI(ahci, SysbusAHCIState), 1357 VMSTATE_END_OF_LIST() 1358 }, 1359 }; 1360 1361 static void sysbus_ahci_reset(DeviceState *dev) 1362 { 1363 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1364 1365 ahci_reset(&s->ahci); 1366 } 1367 1368 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1369 { 1370 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1371 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1372 1373 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports); 1374 1375 sysbus_init_mmio(sbd, &s->ahci.mem); 1376 sysbus_init_irq(sbd, &s->ahci.irq); 1377 } 1378 1379 static Property sysbus_ahci_properties[] = { 1380 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1381 DEFINE_PROP_END_OF_LIST(), 1382 }; 1383 1384 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1385 { 1386 DeviceClass *dc = DEVICE_CLASS(klass); 1387 1388 dc->realize = sysbus_ahci_realize; 1389 dc->vmsd = &vmstate_sysbus_ahci; 1390 dc->props = sysbus_ahci_properties; 1391 dc->reset = sysbus_ahci_reset; 1392 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1393 } 1394 1395 static const TypeInfo sysbus_ahci_info = { 1396 .name = TYPE_SYSBUS_AHCI, 1397 .parent = TYPE_SYS_BUS_DEVICE, 1398 .instance_size = sizeof(SysbusAHCIState), 1399 .class_init = sysbus_ahci_class_init, 1400 }; 1401 1402 static void sysbus_ahci_register_types(void) 1403 { 1404 type_register_static(&sysbus_ahci_info); 1405 } 1406 1407 type_init(sysbus_ahci_register_types) 1408