1 /* 2 * QEMU AHCI Emulation 3 * 4 * Copyright (c) 2010 qiaochong@loongson.cn 5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com> 6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/irq.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/pci.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "qemu/main-loop.h" 34 #include "qemu/module.h" 35 #include "sysemu/block-backend.h" 36 #include "sysemu/dma.h" 37 #include "hw/ide/internal.h" 38 #include "hw/ide/pci.h" 39 #include "ahci_internal.h" 40 41 #include "trace.h" 42 43 static void check_cmd(AHCIState *s, int port); 44 static void handle_cmd(AHCIState *s, int port, uint8_t slot); 45 static void ahci_reset_port(AHCIState *s, int port); 46 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); 47 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); 48 static void ahci_init_d2h(AHCIDevice *ad); 49 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); 50 static bool ahci_map_clb_address(AHCIDevice *ad); 51 static bool ahci_map_fis_address(AHCIDevice *ad); 52 static void ahci_unmap_clb_address(AHCIDevice *ad); 53 static void ahci_unmap_fis_address(AHCIDevice *ad); 54 55 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = { 56 [AHCI_HOST_REG_CAP] = "CAP", 57 [AHCI_HOST_REG_CTL] = "GHC", 58 [AHCI_HOST_REG_IRQ_STAT] = "IS", 59 [AHCI_HOST_REG_PORTS_IMPL] = "PI", 60 [AHCI_HOST_REG_VERSION] = "VS", 61 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL", 62 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS", 63 [AHCI_HOST_REG_EM_LOC] = "EM_LOC", 64 [AHCI_HOST_REG_EM_CTL] = "EM_CTL", 65 [AHCI_HOST_REG_CAP2] = "CAP2", 66 [AHCI_HOST_REG_BOHC] = "BOHC", 67 }; 68 69 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = { 70 [AHCI_PORT_REG_LST_ADDR] = "PxCLB", 71 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU", 72 [AHCI_PORT_REG_FIS_ADDR] = "PxFB", 73 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU", 74 [AHCI_PORT_REG_IRQ_STAT] = "PxIS", 75 [AHCI_PORT_REG_IRQ_MASK] = "PXIE", 76 [AHCI_PORT_REG_CMD] = "PxCMD", 77 [7] = "Reserved", 78 [AHCI_PORT_REG_TFDATA] = "PxTFD", 79 [AHCI_PORT_REG_SIG] = "PxSIG", 80 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS", 81 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL", 82 [AHCI_PORT_REG_SCR_ERR] = "PxSERR", 83 [AHCI_PORT_REG_SCR_ACT] = "PxSACT", 84 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI", 85 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF", 86 [AHCI_PORT_REG_FIS_CTL] = "PxFBS", 87 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP", 88 [18 ... 27] = "Reserved", 89 [AHCI_PORT_REG_VENDOR_1 ... 90 AHCI_PORT_REG_VENDOR_4] = "PxVS", 91 }; 92 93 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = { 94 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS", 95 [AHCI_PORT_IRQ_BIT_PSS] = "PSS", 96 [AHCI_PORT_IRQ_BIT_DSS] = "DSS", 97 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS", 98 [AHCI_PORT_IRQ_BIT_UFS] = "UFS", 99 [AHCI_PORT_IRQ_BIT_DPS] = "DPS", 100 [AHCI_PORT_IRQ_BIT_PCS] = "PCS", 101 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS", 102 [8 ... 21] = "RESERVED", 103 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS", 104 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS", 105 [AHCI_PORT_IRQ_BIT_OFS] = "OFS", 106 [25] = "RESERVED", 107 [AHCI_PORT_IRQ_BIT_INFS] = "INFS", 108 [AHCI_PORT_IRQ_BIT_IFS] = "IFS", 109 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS", 110 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS", 111 [AHCI_PORT_IRQ_BIT_TFES] = "TFES", 112 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS" 113 }; 114 115 static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 116 { 117 uint32_t val; 118 AHCIPortRegs *pr = &s->dev[port].port_regs; 119 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 120 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 121 122 switch (regnum) { 123 case AHCI_PORT_REG_LST_ADDR: 124 val = pr->lst_addr; 125 break; 126 case AHCI_PORT_REG_LST_ADDR_HI: 127 val = pr->lst_addr_hi; 128 break; 129 case AHCI_PORT_REG_FIS_ADDR: 130 val = pr->fis_addr; 131 break; 132 case AHCI_PORT_REG_FIS_ADDR_HI: 133 val = pr->fis_addr_hi; 134 break; 135 case AHCI_PORT_REG_IRQ_STAT: 136 val = pr->irq_stat; 137 break; 138 case AHCI_PORT_REG_IRQ_MASK: 139 val = pr->irq_mask; 140 break; 141 case AHCI_PORT_REG_CMD: 142 val = pr->cmd; 143 break; 144 case AHCI_PORT_REG_TFDATA: 145 val = pr->tfdata; 146 break; 147 case AHCI_PORT_REG_SIG: 148 val = pr->sig; 149 break; 150 case AHCI_PORT_REG_SCR_STAT: 151 if (s->dev[port].port.ifs[0].blk) { 152 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP | 153 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE; 154 } else { 155 val = SATA_SCR_SSTATUS_DET_NODEV; 156 } 157 break; 158 case AHCI_PORT_REG_SCR_CTL: 159 val = pr->scr_ctl; 160 break; 161 case AHCI_PORT_REG_SCR_ERR: 162 val = pr->scr_err; 163 break; 164 case AHCI_PORT_REG_SCR_ACT: 165 val = pr->scr_act; 166 break; 167 case AHCI_PORT_REG_CMD_ISSUE: 168 val = pr->cmd_issue; 169 break; 170 default: 171 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum], 172 offset); 173 val = 0; 174 } 175 176 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val); 177 return val; 178 } 179 180 static void ahci_irq_raise(AHCIState *s) 181 { 182 DeviceState *dev_state = s->container; 183 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 184 TYPE_PCI_DEVICE); 185 186 trace_ahci_irq_raise(s); 187 188 if (pci_dev && msi_enabled(pci_dev)) { 189 msi_notify(pci_dev, 0); 190 } else { 191 qemu_irq_raise(s->irq); 192 } 193 } 194 195 static void ahci_irq_lower(AHCIState *s) 196 { 197 DeviceState *dev_state = s->container; 198 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state), 199 TYPE_PCI_DEVICE); 200 201 trace_ahci_irq_lower(s); 202 203 if (!pci_dev || !msi_enabled(pci_dev)) { 204 qemu_irq_lower(s->irq); 205 } 206 } 207 208 static void ahci_check_irq(AHCIState *s) 209 { 210 int i; 211 uint32_t old_irq = s->control_regs.irqstatus; 212 213 s->control_regs.irqstatus = 0; 214 for (i = 0; i < s->ports; i++) { 215 AHCIPortRegs *pr = &s->dev[i].port_regs; 216 if (pr->irq_stat & pr->irq_mask) { 217 s->control_regs.irqstatus |= (1 << i); 218 } 219 } 220 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); 221 if (s->control_regs.irqstatus && 222 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { 223 ahci_irq_raise(s); 224 } else { 225 ahci_irq_lower(s); 226 } 227 } 228 229 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d, 230 enum AHCIPortIRQ irqbit) 231 { 232 g_assert((unsigned)irqbit < 32); 233 uint32_t irq = 1U << irqbit; 234 uint32_t irqstat = d->port_regs.irq_stat | irq; 235 236 trace_ahci_trigger_irq(s, d->port_no, 237 AHCIPortIRQ_lookup[irqbit], irq, 238 d->port_regs.irq_stat, irqstat, 239 irqstat & d->port_regs.irq_mask); 240 241 d->port_regs.irq_stat = irqstat; 242 ahci_check_irq(s); 243 } 244 245 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr, 246 uint32_t wanted) 247 { 248 hwaddr len = wanted; 249 250 if (*ptr) { 251 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 252 } 253 254 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, 255 MEMTXATTRS_UNSPECIFIED); 256 if (len < wanted && *ptr) { 257 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); 258 *ptr = NULL; 259 } 260 } 261 262 /** 263 * Check the cmd register to see if we should start or stop 264 * the DMA or FIS RX engines. 265 * 266 * @ad: Device to dis/engage. 267 * 268 * @return 0 on success, -1 on error. 269 */ 270 static int ahci_cond_start_engines(AHCIDevice *ad) 271 { 272 AHCIPortRegs *pr = &ad->port_regs; 273 bool cmd_start = pr->cmd & PORT_CMD_START; 274 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON; 275 bool fis_start = pr->cmd & PORT_CMD_FIS_RX; 276 bool fis_on = pr->cmd & PORT_CMD_FIS_ON; 277 278 if (cmd_start && !cmd_on) { 279 if (!ahci_map_clb_address(ad)) { 280 pr->cmd &= ~PORT_CMD_START; 281 error_report("AHCI: Failed to start DMA engine: " 282 "bad command list buffer address"); 283 return -1; 284 } 285 } else if (!cmd_start && cmd_on) { 286 ahci_unmap_clb_address(ad); 287 } 288 289 if (fis_start && !fis_on) { 290 if (!ahci_map_fis_address(ad)) { 291 pr->cmd &= ~PORT_CMD_FIS_RX; 292 error_report("AHCI: Failed to start FIS receive engine: " 293 "bad FIS receive buffer address"); 294 return -1; 295 } 296 } else if (!fis_start && fis_on) { 297 ahci_unmap_fis_address(ad); 298 } 299 300 return 0; 301 } 302 303 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 304 { 305 AHCIPortRegs *pr = &s->dev[port].port_regs; 306 enum AHCIPortReg regnum = offset / sizeof(uint32_t); 307 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t))); 308 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val); 309 310 switch (regnum) { 311 case AHCI_PORT_REG_LST_ADDR: 312 pr->lst_addr = val; 313 break; 314 case AHCI_PORT_REG_LST_ADDR_HI: 315 pr->lst_addr_hi = val; 316 break; 317 case AHCI_PORT_REG_FIS_ADDR: 318 pr->fis_addr = val; 319 break; 320 case AHCI_PORT_REG_FIS_ADDR_HI: 321 pr->fis_addr_hi = val; 322 break; 323 case AHCI_PORT_REG_IRQ_STAT: 324 pr->irq_stat &= ~val; 325 ahci_check_irq(s); 326 break; 327 case AHCI_PORT_REG_IRQ_MASK: 328 pr->irq_mask = val & 0xfdc000ff; 329 ahci_check_irq(s); 330 break; 331 case AHCI_PORT_REG_CMD: 332 if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { 333 pr->scr_act = 0; 334 pr->cmd_issue = 0; 335 } 336 337 /* Block any Read-only fields from being set; 338 * including LIST_ON and FIS_ON. 339 * The spec requires to set ICC bits to zero after the ICC change 340 * is done. We don't support ICC state changes, therefore always 341 * force the ICC bits to zero. 342 */ 343 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | 344 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK)); 345 346 /* Check FIS RX and CLB engines */ 347 ahci_cond_start_engines(&s->dev[port]); 348 349 /* XXX usually the FIS would be pending on the bus here and 350 issuing deferred until the OS enables FIS receival. 351 Instead, we only submit it once - which works in most 352 cases, but is a hack. */ 353 if ((pr->cmd & PORT_CMD_FIS_ON) && 354 !s->dev[port].init_d2h_sent) { 355 ahci_init_d2h(&s->dev[port]); 356 } 357 358 check_cmd(s, port); 359 break; 360 case AHCI_PORT_REG_TFDATA: 361 case AHCI_PORT_REG_SIG: 362 case AHCI_PORT_REG_SCR_STAT: 363 /* Read Only */ 364 break; 365 case AHCI_PORT_REG_SCR_CTL: 366 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && 367 ((val & AHCI_SCR_SCTL_DET) == 0)) { 368 ahci_reset_port(s, port); 369 } 370 pr->scr_ctl = val; 371 break; 372 case AHCI_PORT_REG_SCR_ERR: 373 pr->scr_err &= ~val; 374 break; 375 case AHCI_PORT_REG_SCR_ACT: 376 /* RW1 */ 377 pr->scr_act |= val; 378 break; 379 case AHCI_PORT_REG_CMD_ISSUE: 380 pr->cmd_issue |= val; 381 check_cmd(s, port); 382 break; 383 default: 384 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum], 385 offset, val); 386 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 387 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32, 388 port, AHCIPortReg_lookup[regnum], offset, val); 389 break; 390 } 391 } 392 393 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr) 394 { 395 AHCIState *s = opaque; 396 uint32_t val = 0; 397 398 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 399 enum AHCIHostReg regnum = addr / 4; 400 assert(regnum < AHCI_HOST_REG__COUNT); 401 402 switch (regnum) { 403 case AHCI_HOST_REG_CAP: 404 val = s->control_regs.cap; 405 break; 406 case AHCI_HOST_REG_CTL: 407 val = s->control_regs.ghc; 408 break; 409 case AHCI_HOST_REG_IRQ_STAT: 410 val = s->control_regs.irqstatus; 411 break; 412 case AHCI_HOST_REG_PORTS_IMPL: 413 val = s->control_regs.impl; 414 break; 415 case AHCI_HOST_REG_VERSION: 416 val = s->control_regs.version; 417 break; 418 default: 419 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum], 420 addr); 421 } 422 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val); 423 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 424 (addr < (AHCI_PORT_REGS_START_ADDR + 425 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 426 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 427 addr & AHCI_PORT_ADDR_OFFSET_MASK); 428 } else { 429 trace_ahci_mem_read_32_default(s, addr, val); 430 } 431 432 trace_ahci_mem_read_32(s, addr, val); 433 return val; 434 } 435 436 437 /** 438 * AHCI 1.3 section 3 ("HBA Memory Registers") 439 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads. 440 * Caller is responsible for masking unwanted higher order bytes. 441 */ 442 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 443 { 444 hwaddr aligned = addr & ~0x3; 445 int ofst = addr - aligned; 446 uint64_t lo = ahci_mem_read_32(opaque, aligned); 447 uint64_t hi; 448 uint64_t val; 449 450 /* if < 8 byte read does not cross 4 byte boundary */ 451 if (ofst + size <= 4) { 452 val = lo >> (ofst * 8); 453 } else { 454 g_assert(size > 1); 455 456 /* If the 64bit read is unaligned, we will produce undefined 457 * results. AHCI does not support unaligned 64bit reads. */ 458 hi = ahci_mem_read_32(opaque, aligned + 4); 459 val = (hi << 32 | lo) >> (ofst * 8); 460 } 461 462 trace_ahci_mem_read(opaque, size, addr, val); 463 return val; 464 } 465 466 467 static void ahci_mem_write(void *opaque, hwaddr addr, 468 uint64_t val, unsigned size) 469 { 470 AHCIState *s = opaque; 471 472 trace_ahci_mem_write(s, size, addr, val); 473 474 /* Only aligned reads are allowed on AHCI */ 475 if (addr & 3) { 476 qemu_log_mask(LOG_GUEST_ERROR, 477 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", 478 addr); 479 return; 480 } 481 482 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { 483 enum AHCIHostReg regnum = addr / 4; 484 assert(regnum < AHCI_HOST_REG__COUNT); 485 486 switch (regnum) { 487 case AHCI_HOST_REG_CAP: /* R/WO, RO */ 488 /* FIXME handle R/WO */ 489 break; 490 case AHCI_HOST_REG_CTL: /* R/W */ 491 if (val & HOST_CTL_RESET) { 492 ahci_reset(s); 493 } else { 494 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN; 495 ahci_check_irq(s); 496 } 497 break; 498 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */ 499 s->control_regs.irqstatus &= ~val; 500 ahci_check_irq(s); 501 break; 502 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */ 503 /* FIXME handle R/WO */ 504 break; 505 case AHCI_HOST_REG_VERSION: /* RO */ 506 /* FIXME report write? */ 507 break; 508 default: 509 qemu_log_mask(LOG_UNIMP, 510 "Attempted write to unimplemented register: " 511 "AHCI host register %s, " 512 "offset 0x%"PRIx64": 0x%"PRIx64, 513 AHCIHostReg_lookup[regnum], addr, val); 514 trace_ahci_mem_write_host_unimpl(s, size, 515 AHCIHostReg_lookup[regnum], addr); 516 } 517 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum], 518 addr, val); 519 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && 520 (addr < (AHCI_PORT_REGS_START_ADDR + 521 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { 522 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, 523 addr & AHCI_PORT_ADDR_OFFSET_MASK, val); 524 } else { 525 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: " 526 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64, 527 addr, val); 528 trace_ahci_mem_write_unimpl(s, size, addr, val); 529 } 530 } 531 532 static const MemoryRegionOps ahci_mem_ops = { 533 .read = ahci_mem_read, 534 .write = ahci_mem_write, 535 .endianness = DEVICE_LITTLE_ENDIAN, 536 }; 537 538 static uint64_t ahci_idp_read(void *opaque, hwaddr addr, 539 unsigned size) 540 { 541 AHCIState *s = opaque; 542 543 if (addr == s->idp_offset) { 544 /* index register */ 545 return s->idp_index; 546 } else if (addr == s->idp_offset + 4) { 547 /* data register - do memory read at location selected by index */ 548 return ahci_mem_read(opaque, s->idp_index, size); 549 } else { 550 return 0; 551 } 552 } 553 554 static void ahci_idp_write(void *opaque, hwaddr addr, 555 uint64_t val, unsigned size) 556 { 557 AHCIState *s = opaque; 558 559 if (addr == s->idp_offset) { 560 /* index register - mask off reserved bits */ 561 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3); 562 } else if (addr == s->idp_offset + 4) { 563 /* data register - do memory write at location selected by index */ 564 ahci_mem_write(opaque, s->idp_index, val, size); 565 } 566 } 567 568 static const MemoryRegionOps ahci_idp_ops = { 569 .read = ahci_idp_read, 570 .write = ahci_idp_write, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 }; 573 574 575 static void ahci_reg_init(AHCIState *s) 576 { 577 int i; 578 579 s->control_regs.cap = (s->ports - 1) | 580 (AHCI_NUM_COMMAND_SLOTS << 8) | 581 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) | 582 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64; 583 584 s->control_regs.impl = (1 << s->ports) - 1; 585 586 s->control_regs.version = AHCI_VERSION_1_0; 587 588 for (i = 0; i < s->ports; i++) { 589 s->dev[i].port_state = STATE_RUN; 590 } 591 } 592 593 static void check_cmd(AHCIState *s, int port) 594 { 595 AHCIPortRegs *pr = &s->dev[port].port_regs; 596 uint8_t slot; 597 598 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { 599 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { 600 if (pr->cmd_issue & (1U << slot)) { 601 handle_cmd(s, port, slot); 602 } 603 } 604 } 605 } 606 607 static void ahci_check_cmd_bh(void *opaque) 608 { 609 AHCIDevice *ad = opaque; 610 611 qemu_bh_delete(ad->check_bh); 612 ad->check_bh = NULL; 613 614 check_cmd(ad->hba, ad->port_no); 615 } 616 617 static void ahci_init_d2h(AHCIDevice *ad) 618 { 619 IDEState *ide_state = &ad->port.ifs[0]; 620 AHCIPortRegs *pr = &ad->port_regs; 621 622 if (ad->init_d2h_sent) { 623 return; 624 } 625 626 if (ahci_write_fis_d2h(ad, true)) { 627 ad->init_d2h_sent = true; 628 /* We're emulating receiving the first Reg H2D Fis from the device; 629 * Update the SIG register, but otherwise proceed as normal. */ 630 pr->sig = ((uint32_t)ide_state->hcyl << 24) | 631 (ide_state->lcyl << 16) | 632 (ide_state->sector << 8) | 633 (ide_state->nsector & 0xFF); 634 } 635 } 636 637 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig) 638 { 639 IDEState *s = &ad->port.ifs[0]; 640 s->hcyl = sig >> 24 & 0xFF; 641 s->lcyl = sig >> 16 & 0xFF; 642 s->sector = sig >> 8 & 0xFF; 643 s->nsector = sig & 0xFF; 644 645 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector, 646 s->lcyl, s->hcyl, sig); 647 } 648 649 static void ahci_reset_port(AHCIState *s, int port) 650 { 651 AHCIDevice *d = &s->dev[port]; 652 AHCIPortRegs *pr = &d->port_regs; 653 IDEState *ide_state = &d->port.ifs[0]; 654 int i; 655 656 trace_ahci_reset_port(s, port); 657 658 ide_bus_reset(&d->port); 659 ide_state->ncq_queues = AHCI_MAX_CMDS; 660 661 pr->scr_stat = 0; 662 pr->scr_err = 0; 663 pr->scr_act = 0; 664 pr->tfdata = 0x7F; 665 pr->sig = 0xFFFFFFFF; 666 d->busy_slot = -1; 667 d->init_d2h_sent = false; 668 669 ide_state = &s->dev[port].port.ifs[0]; 670 if (!ide_state->blk) { 671 return; 672 } 673 674 /* reset ncq queue */ 675 for (i = 0; i < AHCI_MAX_CMDS; i++) { 676 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i]; 677 ncq_tfs->halt = false; 678 if (!ncq_tfs->used) { 679 continue; 680 } 681 682 if (ncq_tfs->aiocb) { 683 blk_aio_cancel(ncq_tfs->aiocb); 684 ncq_tfs->aiocb = NULL; 685 } 686 687 /* Maybe we just finished the request thanks to blk_aio_cancel() */ 688 if (!ncq_tfs->used) { 689 continue; 690 } 691 692 qemu_sglist_destroy(&ncq_tfs->sglist); 693 ncq_tfs->used = 0; 694 } 695 696 s->dev[port].port_state = STATE_RUN; 697 if (ide_state->drive_kind == IDE_CD) { 698 ahci_set_signature(d, SATA_SIGNATURE_CDROM); 699 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT; 700 } else { 701 ahci_set_signature(d, SATA_SIGNATURE_DISK); 702 ide_state->status = SEEK_STAT | WRERR_STAT; 703 } 704 705 ide_state->error = 1; 706 ahci_init_d2h(d); 707 } 708 709 /* Buffer pretty output based on a raw FIS structure. */ 710 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len) 711 { 712 int i; 713 GString *s = g_string_new("FIS:"); 714 715 for (i = 0; i < cmd_len; i++) { 716 if ((i & 0xf) == 0) { 717 g_string_append_printf(s, "\n0x%02x: ", i); 718 } 719 g_string_append_printf(s, "%02x ", fis[i]); 720 } 721 g_string_append_c(s, '\n'); 722 723 return g_string_free(s, FALSE); 724 } 725 726 static bool ahci_map_fis_address(AHCIDevice *ad) 727 { 728 AHCIPortRegs *pr = &ad->port_regs; 729 map_page(ad->hba->as, &ad->res_fis, 730 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256); 731 if (ad->res_fis != NULL) { 732 pr->cmd |= PORT_CMD_FIS_ON; 733 return true; 734 } 735 736 pr->cmd &= ~PORT_CMD_FIS_ON; 737 return false; 738 } 739 740 static void ahci_unmap_fis_address(AHCIDevice *ad) 741 { 742 if (ad->res_fis == NULL) { 743 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no); 744 return; 745 } 746 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON; 747 dma_memory_unmap(ad->hba->as, ad->res_fis, 256, 748 DMA_DIRECTION_FROM_DEVICE, 256); 749 ad->res_fis = NULL; 750 } 751 752 static bool ahci_map_clb_address(AHCIDevice *ad) 753 { 754 AHCIPortRegs *pr = &ad->port_regs; 755 ad->cur_cmd = NULL; 756 map_page(ad->hba->as, &ad->lst, 757 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024); 758 if (ad->lst != NULL) { 759 pr->cmd |= PORT_CMD_LIST_ON; 760 return true; 761 } 762 763 pr->cmd &= ~PORT_CMD_LIST_ON; 764 return false; 765 } 766 767 static void ahci_unmap_clb_address(AHCIDevice *ad) 768 { 769 if (ad->lst == NULL) { 770 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no); 771 return; 772 } 773 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON; 774 dma_memory_unmap(ad->hba->as, ad->lst, 1024, 775 DMA_DIRECTION_FROM_DEVICE, 1024); 776 ad->lst = NULL; 777 } 778 779 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) 780 { 781 AHCIDevice *ad = ncq_tfs->drive; 782 AHCIPortRegs *pr = &ad->port_regs; 783 IDEState *ide_state; 784 SDBFIS *sdb_fis; 785 786 if (!ad->res_fis || 787 !(pr->cmd & PORT_CMD_FIS_RX)) { 788 return; 789 } 790 791 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS]; 792 ide_state = &ad->port.ifs[0]; 793 794 sdb_fis->type = SATA_FIS_TYPE_SDB; 795 /* Interrupt pending & Notification bit */ 796 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */ 797 sdb_fis->status = ide_state->status & 0x77; 798 sdb_fis->error = ide_state->error; 799 /* update SAct field in SDB_FIS */ 800 sdb_fis->payload = cpu_to_le32(ad->finished); 801 802 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */ 803 pr->tfdata = (ad->port.ifs[0].error << 8) | 804 (ad->port.ifs[0].status & 0x77) | 805 (pr->tfdata & 0x88); 806 pr->scr_act &= ~ad->finished; 807 ad->finished = 0; 808 809 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */ 810 if (sdb_fis->flags & 0x40) { 811 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); 812 } 813 } 814 815 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) 816 { 817 AHCIPortRegs *pr = &ad->port_regs; 818 uint8_t *pio_fis; 819 IDEState *s = &ad->port.ifs[0]; 820 821 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 822 return; 823 } 824 825 pio_fis = &ad->res_fis[RES_FIS_PSFIS]; 826 827 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP; 828 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0); 829 pio_fis[2] = s->status; 830 pio_fis[3] = s->error; 831 832 pio_fis[4] = s->sector; 833 pio_fis[5] = s->lcyl; 834 pio_fis[6] = s->hcyl; 835 pio_fis[7] = s->select; 836 pio_fis[8] = s->hob_sector; 837 pio_fis[9] = s->hob_lcyl; 838 pio_fis[10] = s->hob_hcyl; 839 pio_fis[11] = 0; 840 pio_fis[12] = s->nsector & 0xFF; 841 pio_fis[13] = (s->nsector >> 8) & 0xFF; 842 pio_fis[14] = 0; 843 pio_fis[15] = s->status; 844 pio_fis[16] = len & 255; 845 pio_fis[17] = len >> 8; 846 pio_fis[18] = 0; 847 pio_fis[19] = 0; 848 849 /* Update shadow registers: */ 850 pr->tfdata = (ad->port.ifs[0].error << 8) | 851 ad->port.ifs[0].status; 852 853 if (pio_fis[2] & ERR_STAT) { 854 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 855 } 856 } 857 858 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) 859 { 860 AHCIPortRegs *pr = &ad->port_regs; 861 uint8_t *d2h_fis; 862 int i; 863 IDEState *s = &ad->port.ifs[0]; 864 865 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) { 866 return false; 867 } 868 869 d2h_fis = &ad->res_fis[RES_FIS_RFIS]; 870 871 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; 872 d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ 873 d2h_fis[2] = s->status; 874 d2h_fis[3] = s->error; 875 876 d2h_fis[4] = s->sector; 877 d2h_fis[5] = s->lcyl; 878 d2h_fis[6] = s->hcyl; 879 d2h_fis[7] = s->select; 880 d2h_fis[8] = s->hob_sector; 881 d2h_fis[9] = s->hob_lcyl; 882 d2h_fis[10] = s->hob_hcyl; 883 d2h_fis[11] = 0; 884 d2h_fis[12] = s->nsector & 0xFF; 885 d2h_fis[13] = (s->nsector >> 8) & 0xFF; 886 for (i = 14; i < 20; i++) { 887 d2h_fis[i] = 0; 888 } 889 890 /* Update shadow registers: */ 891 pr->tfdata = (ad->port.ifs[0].error << 8) | 892 ad->port.ifs[0].status; 893 894 if (d2h_fis[2] & ERR_STAT) { 895 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); 896 } 897 898 if (d2h_fis_i) { 899 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); 900 } 901 902 return true; 903 } 904 905 static int prdt_tbl_entry_size(const AHCI_SG *tbl) 906 { 907 /* flags_size is zero-based */ 908 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1; 909 } 910 911 /** 912 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist. 913 * @ad: The AHCIDevice for whom we are building the SGList. 914 * @sglist: The SGList target to add PRD entries to. 915 * @cmd: The AHCI Command Header that describes where the PRDT is. 916 * @limit: The remaining size of the S/ATA transaction, in bytes. 917 * @offset: The number of bytes already transferred, in bytes. 918 * 919 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of 920 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop 921 * building the sglist from the PRDT as soon as we hit @limit bytes, 922 * which is <= INT32_MAX/2GiB. 923 */ 924 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 925 AHCICmdHdr *cmd, int64_t limit, uint64_t offset) 926 { 927 uint16_t opts = le16_to_cpu(cmd->opts); 928 uint16_t prdtl = le16_to_cpu(cmd->prdtl); 929 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr); 930 uint64_t prdt_addr = cfis_addr + 0x80; 931 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG)); 932 dma_addr_t real_prdt_len = prdt_len; 933 uint8_t *prdt; 934 int i; 935 int r = 0; 936 uint64_t sum = 0; 937 int off_idx = -1; 938 int64_t off_pos = -1; 939 int tbl_entry_size; 940 IDEBus *bus = &ad->port; 941 BusState *qbus = BUS(bus); 942 943 trace_ahci_populate_sglist(ad->hba, ad->port_no); 944 945 if (!prdtl) { 946 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts); 947 return -1; 948 } 949 950 /* map PRDT */ 951 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, 952 DMA_DIRECTION_TO_DEVICE, 953 MEMTXATTRS_UNSPECIFIED))){ 954 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); 955 return -1; 956 } 957 958 if (prdt_len < real_prdt_len) { 959 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no); 960 r = -1; 961 goto out; 962 } 963 964 /* Get entries in the PRDT, init a qemu sglist accordingly */ 965 if (prdtl > 0) { 966 AHCI_SG *tbl = (AHCI_SG *)prdt; 967 sum = 0; 968 for (i = 0; i < prdtl; i++) { 969 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]); 970 if (offset < (sum + tbl_entry_size)) { 971 off_idx = i; 972 off_pos = offset - sum; 973 break; 974 } 975 sum += tbl_entry_size; 976 } 977 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) { 978 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no, 979 off_idx, off_pos); 980 r = -1; 981 goto out; 982 } 983 984 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx), 985 ad->hba->as); 986 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos, 987 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos, 988 limit)); 989 990 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) { 991 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr), 992 MIN(prdt_tbl_entry_size(&tbl[i]), 993 limit - sglist->size)); 994 } 995 } 996 997 out: 998 dma_memory_unmap(ad->hba->as, prdt, prdt_len, 999 DMA_DIRECTION_TO_DEVICE, prdt_len); 1000 return r; 1001 } 1002 1003 static void ncq_err(NCQTransferState *ncq_tfs) 1004 { 1005 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1006 1007 ide_state->error = ABRT_ERR; 1008 ide_state->status = READY_STAT | ERR_STAT; 1009 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); 1010 qemu_sglist_destroy(&ncq_tfs->sglist); 1011 ncq_tfs->used = 0; 1012 } 1013 1014 static void ncq_finish(NCQTransferState *ncq_tfs) 1015 { 1016 /* If we didn't error out, set our finished bit. Errored commands 1017 * do not get a bit set for the SDB FIS ACT register, nor do they 1018 * clear the outstanding bit in scr_act (PxSACT). */ 1019 if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) { 1020 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); 1021 } 1022 1023 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs); 1024 1025 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no, 1026 ncq_tfs->tag); 1027 1028 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk), 1029 &ncq_tfs->acct); 1030 qemu_sglist_destroy(&ncq_tfs->sglist); 1031 ncq_tfs->used = 0; 1032 } 1033 1034 static void ncq_cb(void *opaque, int ret) 1035 { 1036 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque; 1037 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0]; 1038 1039 ncq_tfs->aiocb = NULL; 1040 1041 if (ret < 0) { 1042 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED; 1043 BlockErrorAction action = blk_get_error_action(ide_state->blk, 1044 is_read, -ret); 1045 if (action == BLOCK_ERROR_ACTION_STOP) { 1046 ncq_tfs->halt = true; 1047 ide_state->bus->error_status = IDE_RETRY_HBA; 1048 } else if (action == BLOCK_ERROR_ACTION_REPORT) { 1049 ncq_err(ncq_tfs); 1050 } 1051 blk_error_action(ide_state->blk, action, is_read, -ret); 1052 } else { 1053 ide_state->status = READY_STAT | SEEK_STAT; 1054 } 1055 1056 if (!ncq_tfs->halt) { 1057 ncq_finish(ncq_tfs); 1058 } 1059 } 1060 1061 static int is_ncq(uint8_t ata_cmd) 1062 { 1063 /* Based on SATA 3.2 section 13.6.3.2 */ 1064 switch (ata_cmd) { 1065 case READ_FPDMA_QUEUED: 1066 case WRITE_FPDMA_QUEUED: 1067 case NCQ_NON_DATA: 1068 case RECEIVE_FPDMA_QUEUED: 1069 case SEND_FPDMA_QUEUED: 1070 return 1; 1071 default: 1072 return 0; 1073 } 1074 } 1075 1076 static void execute_ncq_command(NCQTransferState *ncq_tfs) 1077 { 1078 AHCIDevice *ad = ncq_tfs->drive; 1079 IDEState *ide_state = &ad->port.ifs[0]; 1080 int port = ad->port_no; 1081 1082 g_assert(is_ncq(ncq_tfs->cmd)); 1083 ncq_tfs->halt = false; 1084 1085 switch (ncq_tfs->cmd) { 1086 case READ_FPDMA_QUEUED: 1087 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag, 1088 ncq_tfs->sector_count, ncq_tfs->lba); 1089 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1090 &ncq_tfs->sglist, BLOCK_ACCT_READ); 1091 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist, 1092 ncq_tfs->lba << BDRV_SECTOR_BITS, 1093 BDRV_SECTOR_SIZE, 1094 ncq_cb, ncq_tfs); 1095 break; 1096 case WRITE_FPDMA_QUEUED: 1097 trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag, 1098 ncq_tfs->sector_count, ncq_tfs->lba); 1099 dma_acct_start(ide_state->blk, &ncq_tfs->acct, 1100 &ncq_tfs->sglist, BLOCK_ACCT_WRITE); 1101 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist, 1102 ncq_tfs->lba << BDRV_SECTOR_BITS, 1103 BDRV_SECTOR_SIZE, 1104 ncq_cb, ncq_tfs); 1105 break; 1106 default: 1107 trace_execute_ncq_command_unsup(ad->hba, port, 1108 ncq_tfs->tag, ncq_tfs->cmd); 1109 ncq_err(ncq_tfs); 1110 } 1111 } 1112 1113 1114 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, 1115 uint8_t slot) 1116 { 1117 AHCIDevice *ad = &s->dev[port]; 1118 const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis; 1119 uint8_t tag = ncq_fis->tag >> 3; 1120 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag]; 1121 size_t size; 1122 1123 g_assert(is_ncq(ncq_fis->command)); 1124 if (ncq_tfs->used) { 1125 /* error - already in use */ 1126 qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n", 1127 __func__, tag); 1128 return; 1129 } 1130 1131 /* 1132 * A NCQ command clears the bit in PxCI after the command has been QUEUED 1133 * successfully (ERROR not set, BUSY and DRQ cleared). 1134 * 1135 * For NCQ commands, PxCI will always be cleared here. 1136 * 1137 * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with 1138 * the interrupt bit set, which will clear PxSACT and raise an interrupt.) 1139 */ 1140 ahci_clear_cmd_issue(ad, slot); 1141 1142 /* 1143 * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS 1144 * without the interrupt bit set, but since ahci_write_fis_d2h() can raise 1145 * an IRQ on error, we need to call them in reverse order. 1146 */ 1147 ahci_write_fis_d2h(ad, false); 1148 1149 ncq_tfs->used = 1; 1150 ncq_tfs->drive = ad; 1151 ncq_tfs->slot = slot; 1152 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot]; 1153 ncq_tfs->cmd = ncq_fis->command; 1154 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) | 1155 ((uint64_t)ncq_fis->lba4 << 32) | 1156 ((uint64_t)ncq_fis->lba3 << 24) | 1157 ((uint64_t)ncq_fis->lba2 << 16) | 1158 ((uint64_t)ncq_fis->lba1 << 8) | 1159 (uint64_t)ncq_fis->lba0; 1160 ncq_tfs->tag = tag; 1161 1162 /* Sanity-check the NCQ packet */ 1163 if (tag != slot) { 1164 trace_process_ncq_command_mismatch(s, port, tag, slot); 1165 } 1166 1167 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) { 1168 trace_process_ncq_command_aux(s, port, tag); 1169 } 1170 if (ncq_fis->prio || ncq_fis->icc) { 1171 trace_process_ncq_command_prioicc(s, port, tag); 1172 } 1173 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) { 1174 trace_process_ncq_command_fua(s, port, tag); 1175 } 1176 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) { 1177 trace_process_ncq_command_rarc(s, port, tag); 1178 } 1179 1180 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) | 1181 ncq_fis->sector_count_low); 1182 if (!ncq_tfs->sector_count) { 1183 ncq_tfs->sector_count = 0x10000; 1184 } 1185 size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE; 1186 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0); 1187 1188 if (ncq_tfs->sglist.size < size) { 1189 error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") " 1190 "is smaller than the requested size (0x%zx)", 1191 ncq_tfs->sglist.size, size); 1192 ncq_err(ncq_tfs); 1193 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS); 1194 return; 1195 } else if (ncq_tfs->sglist.size != size) { 1196 trace_process_ncq_command_large(s, port, tag, 1197 ncq_tfs->sglist.size, size); 1198 } 1199 1200 trace_process_ncq_command(s, port, tag, 1201 ncq_fis->command, 1202 ncq_tfs->lba, 1203 ncq_tfs->lba + ncq_tfs->sector_count - 1); 1204 execute_ncq_command(ncq_tfs); 1205 } 1206 1207 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot) 1208 { 1209 if (port >= s->ports || slot >= AHCI_MAX_CMDS) { 1210 return NULL; 1211 } 1212 1213 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL; 1214 } 1215 1216 static void handle_reg_h2d_fis(AHCIState *s, int port, 1217 uint8_t slot, const uint8_t *cmd_fis) 1218 { 1219 IDEState *ide_state = &s->dev[port].port.ifs[0]; 1220 AHCICmdHdr *cmd = get_cmd_header(s, port, slot); 1221 AHCIDevice *ad = &s->dev[port]; 1222 uint16_t opts = le16_to_cpu(cmd->opts); 1223 1224 if (cmd_fis[1] & 0x0F) { 1225 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1], 1226 cmd_fis[2], cmd_fis[3]); 1227 return; 1228 } 1229 1230 if (cmd_fis[1] & 0x70) { 1231 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1], 1232 cmd_fis[2], cmd_fis[3]); 1233 return; 1234 } 1235 1236 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) { 1237 switch (s->dev[port].port_state) { 1238 case STATE_RUN: 1239 if (cmd_fis[15] & ATA_SRST) { 1240 s->dev[port].port_state = STATE_RESET; 1241 } 1242 break; 1243 case STATE_RESET: 1244 if (!(cmd_fis[15] & ATA_SRST)) { 1245 ahci_reset_port(s, port); 1246 } 1247 break; 1248 } 1249 return; 1250 } 1251 1252 /* Check for NCQ command */ 1253 if (is_ncq(cmd_fis[2])) { 1254 process_ncq_command(s, port, cmd_fis, slot); 1255 return; 1256 } 1257 1258 /* Decompose the FIS: 1259 * AHCI does not interpret FIS packets, it only forwards them. 1260 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets. 1261 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets. 1262 * 1263 * ATA4 describes sector number for LBA28/CHS commands. 1264 * ATA6 describes sector number for LBA48 commands. 1265 * ATA8 deprecates CHS fully, describing only LBA28/48. 1266 * 1267 * We dutifully convert the FIS into IDE registers, and allow the 1268 * core layer to interpret them as needed. */ 1269 ide_state->feature = cmd_fis[3]; 1270 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */ 1271 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */ 1272 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */ 1273 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */ 1274 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */ 1275 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */ 1276 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */ 1277 ide_state->hob_feature = cmd_fis[11]; 1278 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]); 1279 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */ 1280 /* 15: Only valid when UPDATE_COMMAND not set. */ 1281 1282 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command 1283 * table to ide_state->io_buffer */ 1284 if (opts & AHCI_CMD_ATAPI) { 1285 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10); 1286 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) { 1287 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10); 1288 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis); 1289 g_free(pretty_fis); 1290 } 1291 } 1292 1293 ide_state->error = 0; 1294 s->dev[port].done_first_drq = false; 1295 /* Reset transferred byte counter */ 1296 cmd->status = 0; 1297 1298 /* 1299 * A non-NCQ command clears the bit in PxCI after the command has COMPLETED 1300 * successfully (ERROR not set, BUSY and DRQ cleared). 1301 * 1302 * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). 1303 */ 1304 ad->busy_slot = slot; 1305 1306 /* We're ready to process the command in FIS byte 2. */ 1307 ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); 1308 } 1309 1310 static void handle_cmd(AHCIState *s, int port, uint8_t slot) 1311 { 1312 IDEState *ide_state; 1313 uint64_t tbl_addr; 1314 AHCICmdHdr *cmd; 1315 uint8_t *cmd_fis; 1316 dma_addr_t cmd_len; 1317 1318 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { 1319 /* Engine currently busy, try again later */ 1320 trace_handle_cmd_busy(s, port); 1321 return; 1322 } 1323 1324 if (!s->dev[port].lst) { 1325 trace_handle_cmd_nolist(s, port); 1326 return; 1327 } 1328 cmd = get_cmd_header(s, port, slot); 1329 /* remember current slot handle for later */ 1330 s->dev[port].cur_cmd = cmd; 1331 1332 /* The device we are working for */ 1333 ide_state = &s->dev[port].port.ifs[0]; 1334 if (!ide_state->blk) { 1335 trace_handle_cmd_badport(s, port); 1336 return; 1337 } 1338 1339 tbl_addr = le64_to_cpu(cmd->tbl_addr); 1340 cmd_len = 0x80; 1341 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len, 1342 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); 1343 if (!cmd_fis) { 1344 trace_handle_cmd_badfis(s, port); 1345 return; 1346 } else if (cmd_len != 0x80) { 1347 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); 1348 trace_handle_cmd_badmap(s, port, cmd_len); 1349 goto out; 1350 } 1351 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) { 1352 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80); 1353 trace_handle_cmd_fis_dump(s, port, pretty_fis); 1354 g_free(pretty_fis); 1355 } 1356 switch (cmd_fis[0]) { 1357 case SATA_FIS_TYPE_REGISTER_H2D: 1358 handle_reg_h2d_fis(s, port, slot, cmd_fis); 1359 break; 1360 default: 1361 trace_handle_cmd_unhandled_fis(s, port, 1362 cmd_fis[0], cmd_fis[1], cmd_fis[2]); 1363 break; 1364 } 1365 1366 out: 1367 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, 1368 cmd_len); 1369 } 1370 1371 /* Transfer PIO data between RAM and device */ 1372 static void ahci_pio_transfer(const IDEDMA *dma) 1373 { 1374 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1375 IDEState *s = &ad->port.ifs[0]; 1376 uint32_t size = (uint32_t)(s->data_end - s->data_ptr); 1377 /* write == ram -> device */ 1378 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts); 1379 int is_write = opts & AHCI_CMD_WRITE; 1380 int is_atapi = opts & AHCI_CMD_ATAPI; 1381 int has_sglist = 0; 1382 bool pio_fis_i; 1383 1384 /* The PIO Setup FIS is received prior to transfer, but the interrupt 1385 * is only triggered after data is received. 1386 * 1387 * The device only sets the 'I' bit in the PIO Setup FIS for device->host 1388 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after 1389 * the first (see "DPIOO1"). The latter is consistent with the spec's 1390 * description of the PACKET protocol, where the command part of ATAPI requests 1391 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests 1392 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs. 1393 */ 1394 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write); 1395 ahci_write_fis_pio(ad, size, pio_fis_i); 1396 1397 if (is_atapi && !ad->done_first_drq) { 1398 /* already prepopulated iobuffer */ 1399 goto out; 1400 } 1401 1402 if (ahci_dma_prepare_buf(dma, size)) { 1403 has_sglist = 1; 1404 } 1405 1406 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read", 1407 size, is_atapi ? "atapi" : "ata", 1408 has_sglist ? "" : "o"); 1409 1410 if (has_sglist && size) { 1411 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1412 1413 if (is_write) { 1414 dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs); 1415 } else { 1416 dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs); 1417 } 1418 } 1419 1420 /* Update number of transferred bytes, destroy sglist */ 1421 dma_buf_commit(s, size); 1422 1423 out: 1424 /* declare that we processed everything */ 1425 s->data_ptr = s->data_end; 1426 1427 ad->done_first_drq = true; 1428 if (pio_fis_i) { 1429 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS); 1430 } 1431 } 1432 1433 static void ahci_start_dma(const IDEDMA *dma, IDEState *s, 1434 BlockCompletionFunc *dma_cb) 1435 { 1436 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1437 trace_ahci_start_dma(ad->hba, ad->port_no); 1438 s->io_buffer_offset = 0; 1439 dma_cb(s, 0); 1440 } 1441 1442 static void ahci_restart_dma(const IDEDMA *dma) 1443 { 1444 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */ 1445 } 1446 1447 /** 1448 * IDE/PIO restarts are handled by the core layer, but NCQ commands 1449 * need an extra kick from the AHCI HBA. 1450 */ 1451 static void ahci_restart(const IDEDMA *dma) 1452 { 1453 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1454 int i; 1455 1456 for (i = 0; i < AHCI_MAX_CMDS; i++) { 1457 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i]; 1458 if (ncq_tfs->halt) { 1459 execute_ncq_command(ncq_tfs); 1460 } 1461 } 1462 } 1463 1464 /** 1465 * Called in DMA and PIO R/W chains to read the PRDT. 1466 * Not shared with NCQ pathways. 1467 */ 1468 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit) 1469 { 1470 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1471 IDEState *s = &ad->port.ifs[0]; 1472 1473 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, 1474 limit, s->io_buffer_offset) == -1) { 1475 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no); 1476 return -1; 1477 } 1478 s->io_buffer_size = s->sg.size; 1479 1480 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size); 1481 return s->io_buffer_size; 1482 } 1483 1484 /** 1485 * Updates the command header with a bytes-read value. 1486 * Called via dma_buf_commit, for both DMA and PIO paths. 1487 * sglist destruction is handled within dma_buf_commit. 1488 */ 1489 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes) 1490 { 1491 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1492 1493 tx_bytes += le32_to_cpu(ad->cur_cmd->status); 1494 ad->cur_cmd->status = cpu_to_le32(tx_bytes); 1495 } 1496 1497 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) 1498 { 1499 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1500 IDEState *s = &ad->port.ifs[0]; 1501 uint8_t *p = s->io_buffer + s->io_buffer_index; 1502 int l = s->io_buffer_size - s->io_buffer_index; 1503 1504 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) { 1505 return 0; 1506 } 1507 1508 if (is_write) { 1509 dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1510 } else { 1511 dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED); 1512 } 1513 1514 /* free sglist, update byte count */ 1515 dma_buf_commit(s, l); 1516 s->io_buffer_index += l; 1517 1518 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l); 1519 return 1; 1520 } 1521 1522 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) 1523 { 1524 IDEState *ide_state = &ad->port.ifs[0]; 1525 1526 if (!(ide_state->status & ERR_STAT) && 1527 !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { 1528 ad->port_regs.cmd_issue &= ~(1 << slot); 1529 } 1530 } 1531 1532 /* Non-NCQ command is done - This function is never called for NCQ commands. */ 1533 static void ahci_cmd_done(const IDEDMA *dma) 1534 { 1535 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); 1536 IDEState *ide_state = &ad->port.ifs[0]; 1537 1538 trace_ahci_cmd_done(ad->hba, ad->port_no); 1539 1540 /* no longer busy */ 1541 if (ad->busy_slot != -1) { 1542 ahci_clear_cmd_issue(ad, ad->busy_slot); 1543 ad->busy_slot = -1; 1544 } 1545 1546 /* 1547 * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H 1548 * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise 1549 * an IRQ, we need to call them in reverse order. 1550 */ 1551 ahci_write_fis_d2h(ad, true); 1552 1553 if (!(ide_state->status & ERR_STAT) && 1554 ad->port_regs.cmd_issue && !ad->check_bh) { 1555 ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, 1556 &ad->mem_reentrancy_guard); 1557 qemu_bh_schedule(ad->check_bh); 1558 } 1559 } 1560 1561 static void ahci_irq_set(void *opaque, int n, int level) 1562 { 1563 qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level); 1564 } 1565 1566 static const IDEDMAOps ahci_dma_ops = { 1567 .start_dma = ahci_start_dma, 1568 .restart = ahci_restart, 1569 .restart_dma = ahci_restart_dma, 1570 .pio_transfer = ahci_pio_transfer, 1571 .prepare_buf = ahci_dma_prepare_buf, 1572 .commit_buf = ahci_commit_buf, 1573 .rw_buf = ahci_dma_rw_buf, 1574 .cmd_done = ahci_cmd_done, 1575 }; 1576 1577 void ahci_init(AHCIState *s, DeviceState *qdev) 1578 { 1579 s->container = qdev; 1580 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ 1581 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s, 1582 "ahci", AHCI_MEM_BAR_SIZE); 1583 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s, 1584 "ahci-idp", 32); 1585 } 1586 1587 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) 1588 { 1589 qemu_irq *irqs; 1590 int i; 1591 1592 s->as = as; 1593 s->ports = ports; 1594 s->dev = g_new0(AHCIDevice, ports); 1595 ahci_reg_init(s); 1596 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports); 1597 for (i = 0; i < s->ports; i++) { 1598 AHCIDevice *ad = &s->dev[i]; 1599 1600 ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); 1601 ide_bus_init_output_irq(&ad->port, irqs[i]); 1602 1603 ad->hba = s; 1604 ad->port_no = i; 1605 ad->port.dma = &ad->dma; 1606 ad->port.dma->ops = &ahci_dma_ops; 1607 ide_bus_register_restart_cb(&ad->port); 1608 } 1609 g_free(irqs); 1610 } 1611 1612 void ahci_uninit(AHCIState *s) 1613 { 1614 int i, j; 1615 1616 for (i = 0; i < s->ports; i++) { 1617 AHCIDevice *ad = &s->dev[i]; 1618 1619 for (j = 0; j < 2; j++) { 1620 IDEState *s = &ad->port.ifs[j]; 1621 1622 ide_exit(s); 1623 } 1624 object_unparent(OBJECT(&ad->port)); 1625 } 1626 1627 g_free(s->dev); 1628 } 1629 1630 void ahci_reset(AHCIState *s) 1631 { 1632 AHCIPortRegs *pr; 1633 int i; 1634 1635 trace_ahci_reset(s); 1636 1637 s->control_regs.irqstatus = 0; 1638 /* AHCI Enable (AE) 1639 * The implementation of this bit is dependent upon the value of the 1640 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and 1641 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be 1642 * read-only and shall have a reset value of '1'. 1643 * 1644 * We set HOST_CAP_AHCI so we must enable AHCI at reset. 1645 */ 1646 s->control_regs.ghc = HOST_CTL_AHCI_EN; 1647 1648 for (i = 0; i < s->ports; i++) { 1649 pr = &s->dev[i].port_regs; 1650 pr->irq_stat = 0; 1651 pr->irq_mask = 0; 1652 pr->scr_ctl = 0; 1653 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON; 1654 ahci_reset_port(s, i); 1655 } 1656 } 1657 1658 static const VMStateDescription vmstate_ncq_tfs = { 1659 .name = "ncq state", 1660 .version_id = 1, 1661 .fields = (VMStateField[]) { 1662 VMSTATE_UINT32(sector_count, NCQTransferState), 1663 VMSTATE_UINT64(lba, NCQTransferState), 1664 VMSTATE_UINT8(tag, NCQTransferState), 1665 VMSTATE_UINT8(cmd, NCQTransferState), 1666 VMSTATE_UINT8(slot, NCQTransferState), 1667 VMSTATE_BOOL(used, NCQTransferState), 1668 VMSTATE_BOOL(halt, NCQTransferState), 1669 VMSTATE_END_OF_LIST() 1670 }, 1671 }; 1672 1673 static const VMStateDescription vmstate_ahci_device = { 1674 .name = "ahci port", 1675 .version_id = 1, 1676 .fields = (VMStateField[]) { 1677 VMSTATE_IDE_BUS(port, AHCIDevice), 1678 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice), 1679 VMSTATE_UINT32(port_state, AHCIDevice), 1680 VMSTATE_UINT32(finished, AHCIDevice), 1681 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice), 1682 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice), 1683 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice), 1684 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice), 1685 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice), 1686 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice), 1687 VMSTATE_UINT32(port_regs.cmd, AHCIDevice), 1688 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice), 1689 VMSTATE_UINT32(port_regs.sig, AHCIDevice), 1690 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice), 1691 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice), 1692 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice), 1693 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice), 1694 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice), 1695 VMSTATE_BOOL(done_first_drq, AHCIDevice), 1696 VMSTATE_INT32(busy_slot, AHCIDevice), 1697 VMSTATE_BOOL(init_d2h_sent, AHCIDevice), 1698 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS, 1699 1, vmstate_ncq_tfs, NCQTransferState), 1700 VMSTATE_END_OF_LIST() 1701 }, 1702 }; 1703 1704 static int ahci_state_post_load(void *opaque, int version_id) 1705 { 1706 int i, j; 1707 struct AHCIDevice *ad; 1708 NCQTransferState *ncq_tfs; 1709 AHCIPortRegs *pr; 1710 AHCIState *s = opaque; 1711 1712 for (i = 0; i < s->ports; i++) { 1713 ad = &s->dev[i]; 1714 pr = &ad->port_regs; 1715 1716 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { 1717 error_report("AHCI: DMA engine should be off, but status bit " 1718 "indicates it is still running."); 1719 return -1; 1720 } 1721 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) { 1722 error_report("AHCI: FIS RX engine should be off, but status bit " 1723 "indicates it is still running."); 1724 return -1; 1725 } 1726 1727 /* After a migrate, the DMA/FIS engines are "off" and 1728 * need to be conditionally restarted */ 1729 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON); 1730 if (ahci_cond_start_engines(ad) != 0) { 1731 return -1; 1732 } 1733 1734 for (j = 0; j < AHCI_MAX_CMDS; j++) { 1735 ncq_tfs = &ad->ncq_tfs[j]; 1736 ncq_tfs->drive = ad; 1737 1738 if (ncq_tfs->used != ncq_tfs->halt) { 1739 return -1; 1740 } 1741 if (!ncq_tfs->halt) { 1742 continue; 1743 } 1744 if (!is_ncq(ncq_tfs->cmd)) { 1745 return -1; 1746 } 1747 if (ncq_tfs->slot != ncq_tfs->tag) { 1748 return -1; 1749 } 1750 /* If ncq_tfs->halt is justly set, the engine should be engaged, 1751 * and the command list buffer should be mapped. */ 1752 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot); 1753 if (!ncq_tfs->cmdh) { 1754 return -1; 1755 } 1756 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist, 1757 ncq_tfs->cmdh, 1758 ncq_tfs->sector_count * BDRV_SECTOR_SIZE, 1759 0); 1760 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) { 1761 return -1; 1762 } 1763 } 1764 1765 1766 /* 1767 * If an error is present, ad->busy_slot will be valid and not -1. 1768 * In this case, an operation is waiting to resume and will re-check 1769 * for additional AHCI commands to execute upon completion. 1770 * 1771 * In the case where no error was present, busy_slot will be -1, 1772 * and we should check to see if there are additional commands waiting. 1773 */ 1774 if (ad->busy_slot == -1) { 1775 check_cmd(s, i); 1776 } else { 1777 /* We are in the middle of a command, and may need to access 1778 * the command header in guest memory again. */ 1779 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) { 1780 return -1; 1781 } 1782 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot); 1783 } 1784 } 1785 1786 return 0; 1787 } 1788 1789 const VMStateDescription vmstate_ahci = { 1790 .name = "ahci", 1791 .version_id = 1, 1792 .post_load = ahci_state_post_load, 1793 .fields = (VMStateField[]) { 1794 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports, 1795 vmstate_ahci_device, AHCIDevice), 1796 VMSTATE_UINT32(control_regs.cap, AHCIState), 1797 VMSTATE_UINT32(control_regs.ghc, AHCIState), 1798 VMSTATE_UINT32(control_regs.irqstatus, AHCIState), 1799 VMSTATE_UINT32(control_regs.impl, AHCIState), 1800 VMSTATE_UINT32(control_regs.version, AHCIState), 1801 VMSTATE_UINT32(idp_index, AHCIState), 1802 VMSTATE_INT32_EQUAL(ports, AHCIState, NULL), 1803 VMSTATE_END_OF_LIST() 1804 }, 1805 }; 1806 1807 static const VMStateDescription vmstate_sysbus_ahci = { 1808 .name = "sysbus-ahci", 1809 .fields = (VMStateField[]) { 1810 VMSTATE_AHCI(ahci, SysbusAHCIState), 1811 VMSTATE_END_OF_LIST() 1812 }, 1813 }; 1814 1815 static void sysbus_ahci_reset(DeviceState *dev) 1816 { 1817 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1818 1819 ahci_reset(&s->ahci); 1820 } 1821 1822 static void sysbus_ahci_init(Object *obj) 1823 { 1824 SysbusAHCIState *s = SYSBUS_AHCI(obj); 1825 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1826 1827 ahci_init(&s->ahci, DEVICE(obj)); 1828 1829 sysbus_init_mmio(sbd, &s->ahci.mem); 1830 sysbus_init_irq(sbd, &s->ahci.irq); 1831 } 1832 1833 static void sysbus_ahci_realize(DeviceState *dev, Error **errp) 1834 { 1835 SysbusAHCIState *s = SYSBUS_AHCI(dev); 1836 1837 ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports); 1838 } 1839 1840 static Property sysbus_ahci_properties[] = { 1841 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1), 1842 DEFINE_PROP_END_OF_LIST(), 1843 }; 1844 1845 static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 1846 { 1847 DeviceClass *dc = DEVICE_CLASS(klass); 1848 1849 dc->realize = sysbus_ahci_realize; 1850 dc->vmsd = &vmstate_sysbus_ahci; 1851 device_class_set_props(dc, sysbus_ahci_properties); 1852 dc->reset = sysbus_ahci_reset; 1853 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1854 } 1855 1856 static const TypeInfo sysbus_ahci_info = { 1857 .name = TYPE_SYSBUS_AHCI, 1858 .parent = TYPE_SYS_BUS_DEVICE, 1859 .instance_size = sizeof(SysbusAHCIState), 1860 .instance_init = sysbus_ahci_init, 1861 .class_init = sysbus_ahci_class_init, 1862 }; 1863 1864 static void sysbus_ahci_register_types(void) 1865 { 1866 type_register_static(&sysbus_ahci_info); 1867 } 1868 1869 type_init(sysbus_ahci_register_types) 1870 1871 int32_t ahci_get_num_ports(PCIDevice *dev) 1872 { 1873 AHCIPCIState *d = ICH9_AHCI(dev); 1874 AHCIState *ahci = &d->ahci; 1875 1876 return ahci->ports; 1877 } 1878 1879 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd) 1880 { 1881 AHCIPCIState *d = ICH9_AHCI(dev); 1882 AHCIState *ahci = &d->ahci; 1883 int i; 1884 1885 for (i = 0; i < ahci->ports; i++) { 1886 if (hd[i] == NULL) { 1887 continue; 1888 } 1889 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]); 1890 } 1891 1892 } 1893