xref: /openbmc/qemu/hw/ide/ahci.c (revision 06831001)
1 /*
2  * QEMU AHCI Emulation
3  *
4  * Copyright (c) 2010 qiaochong@loongson.cn
5  * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6  * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7  * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License as published by the Free Software Foundation; either
12  * version 2.1 of the License, or (at your option) any later version.
13  *
14  * This library is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * Lesser General Public License for more details.
18  *
19  * You should have received a copy of the GNU Lesser General Public
20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 
24 #include "qemu/osdep.h"
25 #include "hw/irq.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 
31 #include "qemu/error-report.h"
32 #include "qemu/log.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/module.h"
35 #include "sysemu/block-backend.h"
36 #include "sysemu/dma.h"
37 #include "hw/ide/internal.h"
38 #include "hw/ide/pci.h"
39 #include "ahci_internal.h"
40 
41 #include "trace.h"
42 
43 static void check_cmd(AHCIState *s, int port);
44 static int handle_cmd(AHCIState *s, int port, uint8_t slot);
45 static void ahci_reset_port(AHCIState *s, int port);
46 static bool ahci_write_fis_d2h(AHCIDevice *ad);
47 static void ahci_init_d2h(AHCIDevice *ad);
48 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
49 static bool ahci_map_clb_address(AHCIDevice *ad);
50 static bool ahci_map_fis_address(AHCIDevice *ad);
51 static void ahci_unmap_clb_address(AHCIDevice *ad);
52 static void ahci_unmap_fis_address(AHCIDevice *ad);
53 
54 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = {
55     [AHCI_HOST_REG_CAP]        = "CAP",
56     [AHCI_HOST_REG_CTL]        = "GHC",
57     [AHCI_HOST_REG_IRQ_STAT]   = "IS",
58     [AHCI_HOST_REG_PORTS_IMPL] = "PI",
59     [AHCI_HOST_REG_VERSION]    = "VS",
60     [AHCI_HOST_REG_CCC_CTL]    = "CCC_CTL",
61     [AHCI_HOST_REG_CCC_PORTS]  = "CCC_PORTS",
62     [AHCI_HOST_REG_EM_LOC]     = "EM_LOC",
63     [AHCI_HOST_REG_EM_CTL]     = "EM_CTL",
64     [AHCI_HOST_REG_CAP2]       = "CAP2",
65     [AHCI_HOST_REG_BOHC]       = "BOHC",
66 };
67 
68 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = {
69     [AHCI_PORT_REG_LST_ADDR]    = "PxCLB",
70     [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU",
71     [AHCI_PORT_REG_FIS_ADDR]    = "PxFB",
72     [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU",
73     [AHCI_PORT_REG_IRQ_STAT]    = "PxIS",
74     [AHCI_PORT_REG_IRQ_MASK]    = "PXIE",
75     [AHCI_PORT_REG_CMD]         = "PxCMD",
76     [7]                         = "Reserved",
77     [AHCI_PORT_REG_TFDATA]      = "PxTFD",
78     [AHCI_PORT_REG_SIG]         = "PxSIG",
79     [AHCI_PORT_REG_SCR_STAT]    = "PxSSTS",
80     [AHCI_PORT_REG_SCR_CTL]     = "PxSCTL",
81     [AHCI_PORT_REG_SCR_ERR]     = "PxSERR",
82     [AHCI_PORT_REG_SCR_ACT]     = "PxSACT",
83     [AHCI_PORT_REG_CMD_ISSUE]   = "PxCI",
84     [AHCI_PORT_REG_SCR_NOTIF]   = "PxSNTF",
85     [AHCI_PORT_REG_FIS_CTL]     = "PxFBS",
86     [AHCI_PORT_REG_DEV_SLEEP]   = "PxDEVSLP",
87     [18 ... 27]                 = "Reserved",
88     [AHCI_PORT_REG_VENDOR_1 ...
89      AHCI_PORT_REG_VENDOR_4]    = "PxVS",
90 };
91 
92 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {
93     [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
94     [AHCI_PORT_IRQ_BIT_PSS]  = "PSS",
95     [AHCI_PORT_IRQ_BIT_DSS]  = "DSS",
96     [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
97     [AHCI_PORT_IRQ_BIT_UFS]  = "UFS",
98     [AHCI_PORT_IRQ_BIT_DPS]  = "DPS",
99     [AHCI_PORT_IRQ_BIT_PCS]  = "PCS",
100     [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
101     [8 ... 21]               = "RESERVED",
102     [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
103     [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
104     [AHCI_PORT_IRQ_BIT_OFS]  = "OFS",
105     [25]                     = "RESERVED",
106     [AHCI_PORT_IRQ_BIT_INFS] = "INFS",
107     [AHCI_PORT_IRQ_BIT_IFS]  = "IFS",
108     [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
109     [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
110     [AHCI_PORT_IRQ_BIT_TFES] = "TFES",
111     [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
112 };
113 
114 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
115 {
116     uint32_t val;
117     AHCIPortRegs *pr = &s->dev[port].port_regs;
118     enum AHCIPortReg regnum = offset / sizeof(uint32_t);
119     assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
120 
121     switch (regnum) {
122     case AHCI_PORT_REG_LST_ADDR:
123         val = pr->lst_addr;
124         break;
125     case AHCI_PORT_REG_LST_ADDR_HI:
126         val = pr->lst_addr_hi;
127         break;
128     case AHCI_PORT_REG_FIS_ADDR:
129         val = pr->fis_addr;
130         break;
131     case AHCI_PORT_REG_FIS_ADDR_HI:
132         val = pr->fis_addr_hi;
133         break;
134     case AHCI_PORT_REG_IRQ_STAT:
135         val = pr->irq_stat;
136         break;
137     case AHCI_PORT_REG_IRQ_MASK:
138         val = pr->irq_mask;
139         break;
140     case AHCI_PORT_REG_CMD:
141         val = pr->cmd;
142         break;
143     case AHCI_PORT_REG_TFDATA:
144         val = pr->tfdata;
145         break;
146     case AHCI_PORT_REG_SIG:
147         val = pr->sig;
148         break;
149     case AHCI_PORT_REG_SCR_STAT:
150         if (s->dev[port].port.ifs[0].blk) {
151             val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
152                   SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
153         } else {
154             val = SATA_SCR_SSTATUS_DET_NODEV;
155         }
156         break;
157     case AHCI_PORT_REG_SCR_CTL:
158         val = pr->scr_ctl;
159         break;
160     case AHCI_PORT_REG_SCR_ERR:
161         val = pr->scr_err;
162         break;
163     case AHCI_PORT_REG_SCR_ACT:
164         val = pr->scr_act;
165         break;
166     case AHCI_PORT_REG_CMD_ISSUE:
167         val = pr->cmd_issue;
168         break;
169     default:
170         trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum],
171                                      offset);
172         val = 0;
173     }
174 
175     trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val);
176     return val;
177 }
178 
179 static void ahci_irq_raise(AHCIState *s)
180 {
181     DeviceState *dev_state = s->container;
182     PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
183                                                            TYPE_PCI_DEVICE);
184 
185     trace_ahci_irq_raise(s);
186 
187     if (pci_dev && msi_enabled(pci_dev)) {
188         msi_notify(pci_dev, 0);
189     } else {
190         qemu_irq_raise(s->irq);
191     }
192 }
193 
194 static void ahci_irq_lower(AHCIState *s)
195 {
196     DeviceState *dev_state = s->container;
197     PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
198                                                            TYPE_PCI_DEVICE);
199 
200     trace_ahci_irq_lower(s);
201 
202     if (!pci_dev || !msi_enabled(pci_dev)) {
203         qemu_irq_lower(s->irq);
204     }
205 }
206 
207 static void ahci_check_irq(AHCIState *s)
208 {
209     int i;
210     uint32_t old_irq = s->control_regs.irqstatus;
211 
212     s->control_regs.irqstatus = 0;
213     for (i = 0; i < s->ports; i++) {
214         AHCIPortRegs *pr = &s->dev[i].port_regs;
215         if (pr->irq_stat & pr->irq_mask) {
216             s->control_regs.irqstatus |= (1 << i);
217         }
218     }
219     trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
220     if (s->control_regs.irqstatus &&
221         (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
222             ahci_irq_raise(s);
223     } else {
224         ahci_irq_lower(s);
225     }
226 }
227 
228 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
229                              enum AHCIPortIRQ irqbit)
230 {
231     g_assert((unsigned)irqbit < 32);
232     uint32_t irq = 1U << irqbit;
233     uint32_t irqstat = d->port_regs.irq_stat | irq;
234 
235     trace_ahci_trigger_irq(s, d->port_no,
236                            AHCIPortIRQ_lookup[irqbit], irq,
237                            d->port_regs.irq_stat, irqstat,
238                            irqstat & d->port_regs.irq_mask);
239 
240     d->port_regs.irq_stat = irqstat;
241     ahci_check_irq(s);
242 }
243 
244 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr,
245                      uint32_t wanted)
246 {
247     hwaddr len = wanted;
248 
249     if (*ptr) {
250         dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
251     }
252 
253     *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE,
254                           MEMTXATTRS_UNSPECIFIED);
255     if (len < wanted && *ptr) {
256         dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
257         *ptr = NULL;
258     }
259 }
260 
261 /**
262  * Check the cmd register to see if we should start or stop
263  * the DMA or FIS RX engines.
264  *
265  * @ad: Device to dis/engage.
266  *
267  * @return 0 on success, -1 on error.
268  */
269 static int ahci_cond_start_engines(AHCIDevice *ad)
270 {
271     AHCIPortRegs *pr = &ad->port_regs;
272     bool cmd_start = pr->cmd & PORT_CMD_START;
273     bool cmd_on    = pr->cmd & PORT_CMD_LIST_ON;
274     bool fis_start = pr->cmd & PORT_CMD_FIS_RX;
275     bool fis_on    = pr->cmd & PORT_CMD_FIS_ON;
276 
277     if (cmd_start && !cmd_on) {
278         if (!ahci_map_clb_address(ad)) {
279             pr->cmd &= ~PORT_CMD_START;
280             error_report("AHCI: Failed to start DMA engine: "
281                          "bad command list buffer address");
282             return -1;
283         }
284     } else if (!cmd_start && cmd_on) {
285         ahci_unmap_clb_address(ad);
286     }
287 
288     if (fis_start && !fis_on) {
289         if (!ahci_map_fis_address(ad)) {
290             pr->cmd &= ~PORT_CMD_FIS_RX;
291             error_report("AHCI: Failed to start FIS receive engine: "
292                          "bad FIS receive buffer address");
293             return -1;
294         }
295     } else if (!fis_start && fis_on) {
296         ahci_unmap_fis_address(ad);
297     }
298 
299     return 0;
300 }
301 
302 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
303 {
304     AHCIPortRegs *pr = &s->dev[port].port_regs;
305     enum AHCIPortReg regnum = offset / sizeof(uint32_t);
306     assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
307     trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val);
308 
309     switch (regnum) {
310     case AHCI_PORT_REG_LST_ADDR:
311         pr->lst_addr = val;
312         break;
313     case AHCI_PORT_REG_LST_ADDR_HI:
314         pr->lst_addr_hi = val;
315         break;
316     case AHCI_PORT_REG_FIS_ADDR:
317         pr->fis_addr = val;
318         break;
319     case AHCI_PORT_REG_FIS_ADDR_HI:
320         pr->fis_addr_hi = val;
321         break;
322     case AHCI_PORT_REG_IRQ_STAT:
323         pr->irq_stat &= ~val;
324         ahci_check_irq(s);
325         break;
326     case AHCI_PORT_REG_IRQ_MASK:
327         pr->irq_mask = val & 0xfdc000ff;
328         ahci_check_irq(s);
329         break;
330     case AHCI_PORT_REG_CMD:
331         /* Block any Read-only fields from being set;
332          * including LIST_ON and FIS_ON.
333          * The spec requires to set ICC bits to zero after the ICC change
334          * is done. We don't support ICC state changes, therefore always
335          * force the ICC bits to zero.
336          */
337         pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
338             (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
339 
340         /* Check FIS RX and CLB engines */
341         ahci_cond_start_engines(&s->dev[port]);
342 
343         /* XXX usually the FIS would be pending on the bus here and
344            issuing deferred until the OS enables FIS receival.
345            Instead, we only submit it once - which works in most
346            cases, but is a hack. */
347         if ((pr->cmd & PORT_CMD_FIS_ON) &&
348             !s->dev[port].init_d2h_sent) {
349             ahci_init_d2h(&s->dev[port]);
350         }
351 
352         check_cmd(s, port);
353         break;
354     case AHCI_PORT_REG_TFDATA:
355     case AHCI_PORT_REG_SIG:
356     case AHCI_PORT_REG_SCR_STAT:
357         /* Read Only */
358         break;
359     case AHCI_PORT_REG_SCR_CTL:
360         if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
361             ((val & AHCI_SCR_SCTL_DET) == 0)) {
362             ahci_reset_port(s, port);
363         }
364         pr->scr_ctl = val;
365         break;
366     case AHCI_PORT_REG_SCR_ERR:
367         pr->scr_err &= ~val;
368         break;
369     case AHCI_PORT_REG_SCR_ACT:
370         /* RW1 */
371         pr->scr_act |= val;
372         break;
373     case AHCI_PORT_REG_CMD_ISSUE:
374         pr->cmd_issue |= val;
375         check_cmd(s, port);
376         break;
377     default:
378         trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum],
379                                      offset, val);
380         qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
381                       "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32,
382                       port, AHCIPortReg_lookup[regnum], offset, val);
383         break;
384     }
385 }
386 
387 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
388 {
389     AHCIState *s = opaque;
390     uint32_t val = 0;
391 
392     if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
393         enum AHCIHostReg regnum = addr / 4;
394         assert(regnum < AHCI_HOST_REG__COUNT);
395 
396         switch (regnum) {
397         case AHCI_HOST_REG_CAP:
398             val = s->control_regs.cap;
399             break;
400         case AHCI_HOST_REG_CTL:
401             val = s->control_regs.ghc;
402             break;
403         case AHCI_HOST_REG_IRQ_STAT:
404             val = s->control_regs.irqstatus;
405             break;
406         case AHCI_HOST_REG_PORTS_IMPL:
407             val = s->control_regs.impl;
408             break;
409         case AHCI_HOST_REG_VERSION:
410             val = s->control_regs.version;
411             break;
412         default:
413             trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum],
414                                                 addr);
415         }
416         trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val);
417     } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
418                (addr < (AHCI_PORT_REGS_START_ADDR +
419                 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
420         val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
421                              addr & AHCI_PORT_ADDR_OFFSET_MASK);
422     } else {
423         trace_ahci_mem_read_32_default(s, addr, val);
424     }
425 
426     trace_ahci_mem_read_32(s, addr, val);
427     return val;
428 }
429 
430 
431 /**
432  * AHCI 1.3 section 3 ("HBA Memory Registers")
433  * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
434  * Caller is responsible for masking unwanted higher order bytes.
435  */
436 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
437 {
438     hwaddr aligned = addr & ~0x3;
439     int ofst = addr - aligned;
440     uint64_t lo = ahci_mem_read_32(opaque, aligned);
441     uint64_t hi;
442     uint64_t val;
443 
444     /* if < 8 byte read does not cross 4 byte boundary */
445     if (ofst + size <= 4) {
446         val = lo >> (ofst * 8);
447     } else {
448         g_assert(size > 1);
449 
450         /* If the 64bit read is unaligned, we will produce undefined
451          * results. AHCI does not support unaligned 64bit reads. */
452         hi = ahci_mem_read_32(opaque, aligned + 4);
453         val = (hi << 32 | lo) >> (ofst * 8);
454     }
455 
456     trace_ahci_mem_read(opaque, size, addr, val);
457     return val;
458 }
459 
460 
461 static void ahci_mem_write(void *opaque, hwaddr addr,
462                            uint64_t val, unsigned size)
463 {
464     AHCIState *s = opaque;
465 
466     trace_ahci_mem_write(s, size, addr, val);
467 
468     /* Only aligned reads are allowed on AHCI */
469     if (addr & 3) {
470         qemu_log_mask(LOG_GUEST_ERROR,
471                       "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n",
472                       addr);
473         return;
474     }
475 
476     if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
477         enum AHCIHostReg regnum = addr / 4;
478         assert(regnum < AHCI_HOST_REG__COUNT);
479 
480         switch (regnum) {
481         case AHCI_HOST_REG_CAP: /* R/WO, RO */
482             /* FIXME handle R/WO */
483             break;
484         case AHCI_HOST_REG_CTL: /* R/W */
485             if (val & HOST_CTL_RESET) {
486                 ahci_reset(s);
487             } else {
488                 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
489                 ahci_check_irq(s);
490             }
491             break;
492         case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */
493             s->control_regs.irqstatus &= ~val;
494             ahci_check_irq(s);
495             break;
496         case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */
497             /* FIXME handle R/WO */
498             break;
499         case AHCI_HOST_REG_VERSION: /* RO */
500             /* FIXME report write? */
501             break;
502         default:
503             qemu_log_mask(LOG_UNIMP,
504                           "Attempted write to unimplemented register: "
505                           "AHCI host register %s, "
506                           "offset 0x%"PRIx64": 0x%"PRIx64,
507                           AHCIHostReg_lookup[regnum], addr, val);
508             trace_ahci_mem_write_host_unimpl(s, size,
509                                              AHCIHostReg_lookup[regnum], addr);
510         }
511         trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum],
512                                      addr, val);
513     } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
514                (addr < (AHCI_PORT_REGS_START_ADDR +
515                         (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
516         ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
517                         addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
518     } else {
519         qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
520                       "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64,
521                       addr, val);
522         trace_ahci_mem_write_unimpl(s, size, addr, val);
523     }
524 }
525 
526 static const MemoryRegionOps ahci_mem_ops = {
527     .read = ahci_mem_read,
528     .write = ahci_mem_write,
529     .endianness = DEVICE_LITTLE_ENDIAN,
530 };
531 
532 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
533                               unsigned size)
534 {
535     AHCIState *s = opaque;
536 
537     if (addr == s->idp_offset) {
538         /* index register */
539         return s->idp_index;
540     } else if (addr == s->idp_offset + 4) {
541         /* data register - do memory read at location selected by index */
542         return ahci_mem_read(opaque, s->idp_index, size);
543     } else {
544         return 0;
545     }
546 }
547 
548 static void ahci_idp_write(void *opaque, hwaddr addr,
549                            uint64_t val, unsigned size)
550 {
551     AHCIState *s = opaque;
552 
553     if (addr == s->idp_offset) {
554         /* index register - mask off reserved bits */
555         s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
556     } else if (addr == s->idp_offset + 4) {
557         /* data register - do memory write at location selected by index */
558         ahci_mem_write(opaque, s->idp_index, val, size);
559     }
560 }
561 
562 static const MemoryRegionOps ahci_idp_ops = {
563     .read = ahci_idp_read,
564     .write = ahci_idp_write,
565     .endianness = DEVICE_LITTLE_ENDIAN,
566 };
567 
568 
569 static void ahci_reg_init(AHCIState *s)
570 {
571     int i;
572 
573     s->control_regs.cap = (s->ports - 1) |
574                           (AHCI_NUM_COMMAND_SLOTS << 8) |
575                           (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
576                           HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64;
577 
578     s->control_regs.impl = (1 << s->ports) - 1;
579 
580     s->control_regs.version = AHCI_VERSION_1_0;
581 
582     for (i = 0; i < s->ports; i++) {
583         s->dev[i].port_state = STATE_RUN;
584     }
585 }
586 
587 static void check_cmd(AHCIState *s, int port)
588 {
589     AHCIPortRegs *pr = &s->dev[port].port_regs;
590     uint8_t slot;
591 
592     if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
593         for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
594             if ((pr->cmd_issue & (1U << slot)) &&
595                 !handle_cmd(s, port, slot)) {
596                 pr->cmd_issue &= ~(1U << slot);
597             }
598         }
599     }
600 }
601 
602 static void ahci_check_cmd_bh(void *opaque)
603 {
604     AHCIDevice *ad = opaque;
605 
606     qemu_bh_delete(ad->check_bh);
607     ad->check_bh = NULL;
608 
609     check_cmd(ad->hba, ad->port_no);
610 }
611 
612 static void ahci_init_d2h(AHCIDevice *ad)
613 {
614     IDEState *ide_state = &ad->port.ifs[0];
615     AHCIPortRegs *pr = &ad->port_regs;
616 
617     if (ad->init_d2h_sent) {
618         return;
619     }
620 
621     if (ahci_write_fis_d2h(ad)) {
622         ad->init_d2h_sent = true;
623         /* We're emulating receiving the first Reg H2D Fis from the device;
624          * Update the SIG register, but otherwise proceed as normal. */
625         pr->sig = ((uint32_t)ide_state->hcyl << 24) |
626             (ide_state->lcyl << 16) |
627             (ide_state->sector << 8) |
628             (ide_state->nsector & 0xFF);
629     }
630 }
631 
632 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig)
633 {
634     IDEState *s = &ad->port.ifs[0];
635     s->hcyl = sig >> 24 & 0xFF;
636     s->lcyl = sig >> 16 & 0xFF;
637     s->sector = sig >> 8 & 0xFF;
638     s->nsector = sig & 0xFF;
639 
640     trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector,
641                              s->lcyl, s->hcyl, sig);
642 }
643 
644 static void ahci_reset_port(AHCIState *s, int port)
645 {
646     AHCIDevice *d = &s->dev[port];
647     AHCIPortRegs *pr = &d->port_regs;
648     IDEState *ide_state = &d->port.ifs[0];
649     int i;
650 
651     trace_ahci_reset_port(s, port);
652 
653     ide_bus_reset(&d->port);
654     ide_state->ncq_queues = AHCI_MAX_CMDS;
655 
656     pr->scr_stat = 0;
657     pr->scr_err = 0;
658     pr->scr_act = 0;
659     pr->tfdata = 0x7F;
660     pr->sig = 0xFFFFFFFF;
661     d->busy_slot = -1;
662     d->init_d2h_sent = false;
663 
664     ide_state = &s->dev[port].port.ifs[0];
665     if (!ide_state->blk) {
666         return;
667     }
668 
669     /* reset ncq queue */
670     for (i = 0; i < AHCI_MAX_CMDS; i++) {
671         NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
672         ncq_tfs->halt = false;
673         if (!ncq_tfs->used) {
674             continue;
675         }
676 
677         if (ncq_tfs->aiocb) {
678             blk_aio_cancel(ncq_tfs->aiocb);
679             ncq_tfs->aiocb = NULL;
680         }
681 
682         /* Maybe we just finished the request thanks to blk_aio_cancel() */
683         if (!ncq_tfs->used) {
684             continue;
685         }
686 
687         qemu_sglist_destroy(&ncq_tfs->sglist);
688         ncq_tfs->used = 0;
689     }
690 
691     s->dev[port].port_state = STATE_RUN;
692     if (ide_state->drive_kind == IDE_CD) {
693         ahci_set_signature(d, SATA_SIGNATURE_CDROM);\
694         ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
695     } else {
696         ahci_set_signature(d, SATA_SIGNATURE_DISK);
697         ide_state->status = SEEK_STAT | WRERR_STAT;
698     }
699 
700     ide_state->error = 1;
701     ahci_init_d2h(d);
702 }
703 
704 /* Buffer pretty output based on a raw FIS structure. */
705 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len)
706 {
707     int i;
708     GString *s = g_string_new("FIS:");
709 
710     for (i = 0; i < cmd_len; i++) {
711         if ((i & 0xf) == 0) {
712             g_string_append_printf(s, "\n0x%02x: ", i);
713         }
714         g_string_append_printf(s, "%02x ", fis[i]);
715     }
716     g_string_append_c(s, '\n');
717 
718     return g_string_free(s, FALSE);
719 }
720 
721 static bool ahci_map_fis_address(AHCIDevice *ad)
722 {
723     AHCIPortRegs *pr = &ad->port_regs;
724     map_page(ad->hba->as, &ad->res_fis,
725              ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
726     if (ad->res_fis != NULL) {
727         pr->cmd |= PORT_CMD_FIS_ON;
728         return true;
729     }
730 
731     pr->cmd &= ~PORT_CMD_FIS_ON;
732     return false;
733 }
734 
735 static void ahci_unmap_fis_address(AHCIDevice *ad)
736 {
737     if (ad->res_fis == NULL) {
738         trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no);
739         return;
740     }
741     ad->port_regs.cmd &= ~PORT_CMD_FIS_ON;
742     dma_memory_unmap(ad->hba->as, ad->res_fis, 256,
743                      DMA_DIRECTION_FROM_DEVICE, 256);
744     ad->res_fis = NULL;
745 }
746 
747 static bool ahci_map_clb_address(AHCIDevice *ad)
748 {
749     AHCIPortRegs *pr = &ad->port_regs;
750     ad->cur_cmd = NULL;
751     map_page(ad->hba->as, &ad->lst,
752              ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
753     if (ad->lst != NULL) {
754         pr->cmd |= PORT_CMD_LIST_ON;
755         return true;
756     }
757 
758     pr->cmd &= ~PORT_CMD_LIST_ON;
759     return false;
760 }
761 
762 static void ahci_unmap_clb_address(AHCIDevice *ad)
763 {
764     if (ad->lst == NULL) {
765         trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no);
766         return;
767     }
768     ad->port_regs.cmd &= ~PORT_CMD_LIST_ON;
769     dma_memory_unmap(ad->hba->as, ad->lst, 1024,
770                      DMA_DIRECTION_FROM_DEVICE, 1024);
771     ad->lst = NULL;
772 }
773 
774 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)
775 {
776     AHCIDevice *ad = ncq_tfs->drive;
777     AHCIPortRegs *pr = &ad->port_regs;
778     IDEState *ide_state;
779     SDBFIS *sdb_fis;
780 
781     if (!ad->res_fis ||
782         !(pr->cmd & PORT_CMD_FIS_RX)) {
783         return;
784     }
785 
786     sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS];
787     ide_state = &ad->port.ifs[0];
788 
789     sdb_fis->type = SATA_FIS_TYPE_SDB;
790     /* Interrupt pending & Notification bit */
791     sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */
792     sdb_fis->status = ide_state->status & 0x77;
793     sdb_fis->error = ide_state->error;
794     /* update SAct field in SDB_FIS */
795     sdb_fis->payload = cpu_to_le32(ad->finished);
796 
797     /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
798     pr->tfdata = (ad->port.ifs[0].error << 8) |
799         (ad->port.ifs[0].status & 0x77) |
800         (pr->tfdata & 0x88);
801     pr->scr_act &= ~ad->finished;
802     ad->finished = 0;
803 
804     /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
805     if (sdb_fis->flags & 0x40) {
806         ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
807     }
808 }
809 
810 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i)
811 {
812     AHCIPortRegs *pr = &ad->port_regs;
813     uint8_t *pio_fis;
814     IDEState *s = &ad->port.ifs[0];
815 
816     if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
817         return;
818     }
819 
820     pio_fis = &ad->res_fis[RES_FIS_PSFIS];
821 
822     pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
823     pio_fis[1] = (pio_fis_i ? (1 << 6) : 0);
824     pio_fis[2] = s->status;
825     pio_fis[3] = s->error;
826 
827     pio_fis[4] = s->sector;
828     pio_fis[5] = s->lcyl;
829     pio_fis[6] = s->hcyl;
830     pio_fis[7] = s->select;
831     pio_fis[8] = s->hob_sector;
832     pio_fis[9] = s->hob_lcyl;
833     pio_fis[10] = s->hob_hcyl;
834     pio_fis[11] = 0;
835     pio_fis[12] = s->nsector & 0xFF;
836     pio_fis[13] = (s->nsector >> 8) & 0xFF;
837     pio_fis[14] = 0;
838     pio_fis[15] = s->status;
839     pio_fis[16] = len & 255;
840     pio_fis[17] = len >> 8;
841     pio_fis[18] = 0;
842     pio_fis[19] = 0;
843 
844     /* Update shadow registers: */
845     pr->tfdata = (ad->port.ifs[0].error << 8) |
846         ad->port.ifs[0].status;
847 
848     if (pio_fis[2] & ERR_STAT) {
849         ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
850     }
851 }
852 
853 static bool ahci_write_fis_d2h(AHCIDevice *ad)
854 {
855     AHCIPortRegs *pr = &ad->port_regs;
856     uint8_t *d2h_fis;
857     int i;
858     IDEState *s = &ad->port.ifs[0];
859 
860     if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
861         return false;
862     }
863 
864     d2h_fis = &ad->res_fis[RES_FIS_RFIS];
865 
866     d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
867     d2h_fis[1] = (1 << 6); /* interrupt bit */
868     d2h_fis[2] = s->status;
869     d2h_fis[3] = s->error;
870 
871     d2h_fis[4] = s->sector;
872     d2h_fis[5] = s->lcyl;
873     d2h_fis[6] = s->hcyl;
874     d2h_fis[7] = s->select;
875     d2h_fis[8] = s->hob_sector;
876     d2h_fis[9] = s->hob_lcyl;
877     d2h_fis[10] = s->hob_hcyl;
878     d2h_fis[11] = 0;
879     d2h_fis[12] = s->nsector & 0xFF;
880     d2h_fis[13] = (s->nsector >> 8) & 0xFF;
881     for (i = 14; i < 20; i++) {
882         d2h_fis[i] = 0;
883     }
884 
885     /* Update shadow registers: */
886     pr->tfdata = (ad->port.ifs[0].error << 8) |
887         ad->port.ifs[0].status;
888 
889     if (d2h_fis[2] & ERR_STAT) {
890         ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
891     }
892 
893     ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
894     return true;
895 }
896 
897 static int prdt_tbl_entry_size(const AHCI_SG *tbl)
898 {
899     /* flags_size is zero-based */
900     return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
901 }
902 
903 /**
904  * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
905  * @ad: The AHCIDevice for whom we are building the SGList.
906  * @sglist: The SGList target to add PRD entries to.
907  * @cmd: The AHCI Command Header that describes where the PRDT is.
908  * @limit: The remaining size of the S/ATA transaction, in bytes.
909  * @offset: The number of bytes already transferred, in bytes.
910  *
911  * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
912  * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
913  * building the sglist from the PRDT as soon as we hit @limit bytes,
914  * which is <= INT32_MAX/2GiB.
915  */
916 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
917                                 AHCICmdHdr *cmd, int64_t limit, uint64_t offset)
918 {
919     uint16_t opts = le16_to_cpu(cmd->opts);
920     uint16_t prdtl = le16_to_cpu(cmd->prdtl);
921     uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr);
922     uint64_t prdt_addr = cfis_addr + 0x80;
923     dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG));
924     dma_addr_t real_prdt_len = prdt_len;
925     uint8_t *prdt;
926     int i;
927     int r = 0;
928     uint64_t sum = 0;
929     int off_idx = -1;
930     int64_t off_pos = -1;
931     int tbl_entry_size;
932     IDEBus *bus = &ad->port;
933     BusState *qbus = BUS(bus);
934 
935     trace_ahci_populate_sglist(ad->hba, ad->port_no);
936 
937     if (!prdtl) {
938         trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts);
939         return -1;
940     }
941 
942     /* map PRDT */
943     if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
944                                 DMA_DIRECTION_TO_DEVICE,
945                                 MEMTXATTRS_UNSPECIFIED))){
946         trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no);
947         return -1;
948     }
949 
950     if (prdt_len < real_prdt_len) {
951         trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no);
952         r = -1;
953         goto out;
954     }
955 
956     /* Get entries in the PRDT, init a qemu sglist accordingly */
957     if (prdtl > 0) {
958         AHCI_SG *tbl = (AHCI_SG *)prdt;
959         sum = 0;
960         for (i = 0; i < prdtl; i++) {
961             tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);
962             if (offset < (sum + tbl_entry_size)) {
963                 off_idx = i;
964                 off_pos = offset - sum;
965                 break;
966             }
967             sum += tbl_entry_size;
968         }
969         if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
970             trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no,
971                                                   off_idx, off_pos);
972             r = -1;
973             goto out;
974         }
975 
976         qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx),
977                          ad->hba->as);
978         qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos,
979                         MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos,
980                             limit));
981 
982         for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) {
983             qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
984                             MIN(prdt_tbl_entry_size(&tbl[i]),
985                                 limit - sglist->size));
986         }
987     }
988 
989 out:
990     dma_memory_unmap(ad->hba->as, prdt, prdt_len,
991                      DMA_DIRECTION_TO_DEVICE, prdt_len);
992     return r;
993 }
994 
995 static void ncq_err(NCQTransferState *ncq_tfs)
996 {
997     IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
998 
999     ide_state->error = ABRT_ERR;
1000     ide_state->status = READY_STAT | ERR_STAT;
1001     ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
1002     qemu_sglist_destroy(&ncq_tfs->sglist);
1003     ncq_tfs->used = 0;
1004 }
1005 
1006 static void ncq_finish(NCQTransferState *ncq_tfs)
1007 {
1008     /* If we didn't error out, set our finished bit. Errored commands
1009      * do not get a bit set for the SDB FIS ACT register, nor do they
1010      * clear the outstanding bit in scr_act (PxSACT). */
1011     if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) {
1012         ncq_tfs->drive->finished |= (1 << ncq_tfs->tag);
1013     }
1014 
1015     ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);
1016 
1017     trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
1018                      ncq_tfs->tag);
1019 
1020     block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
1021                     &ncq_tfs->acct);
1022     qemu_sglist_destroy(&ncq_tfs->sglist);
1023     ncq_tfs->used = 0;
1024 }
1025 
1026 static void ncq_cb(void *opaque, int ret)
1027 {
1028     NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
1029     IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
1030 
1031     ncq_tfs->aiocb = NULL;
1032 
1033     if (ret < 0) {
1034         bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED;
1035         BlockErrorAction action = blk_get_error_action(ide_state->blk,
1036                                                        is_read, -ret);
1037         if (action == BLOCK_ERROR_ACTION_STOP) {
1038             ncq_tfs->halt = true;
1039             ide_state->bus->error_status = IDE_RETRY_HBA;
1040         } else if (action == BLOCK_ERROR_ACTION_REPORT) {
1041             ncq_err(ncq_tfs);
1042         }
1043         blk_error_action(ide_state->blk, action, is_read, -ret);
1044     } else {
1045         ide_state->status = READY_STAT | SEEK_STAT;
1046     }
1047 
1048     if (!ncq_tfs->halt) {
1049         ncq_finish(ncq_tfs);
1050     }
1051 }
1052 
1053 static int is_ncq(uint8_t ata_cmd)
1054 {
1055     /* Based on SATA 3.2 section 13.6.3.2 */
1056     switch (ata_cmd) {
1057     case READ_FPDMA_QUEUED:
1058     case WRITE_FPDMA_QUEUED:
1059     case NCQ_NON_DATA:
1060     case RECEIVE_FPDMA_QUEUED:
1061     case SEND_FPDMA_QUEUED:
1062         return 1;
1063     default:
1064         return 0;
1065     }
1066 }
1067 
1068 static void execute_ncq_command(NCQTransferState *ncq_tfs)
1069 {
1070     AHCIDevice *ad = ncq_tfs->drive;
1071     IDEState *ide_state = &ad->port.ifs[0];
1072     int port = ad->port_no;
1073 
1074     g_assert(is_ncq(ncq_tfs->cmd));
1075     ncq_tfs->halt = false;
1076 
1077     switch (ncq_tfs->cmd) {
1078     case READ_FPDMA_QUEUED:
1079         trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
1080                                        ncq_tfs->sector_count, ncq_tfs->lba);
1081         dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1082                        &ncq_tfs->sglist, BLOCK_ACCT_READ);
1083         ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,
1084                                       ncq_tfs->lba << BDRV_SECTOR_BITS,
1085                                       BDRV_SECTOR_SIZE,
1086                                       ncq_cb, ncq_tfs);
1087         break;
1088     case WRITE_FPDMA_QUEUED:
1089         trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag,
1090                                         ncq_tfs->sector_count, ncq_tfs->lba);
1091         dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1092                        &ncq_tfs->sglist, BLOCK_ACCT_WRITE);
1093         ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
1094                                        ncq_tfs->lba << BDRV_SECTOR_BITS,
1095                                        BDRV_SECTOR_SIZE,
1096                                        ncq_cb, ncq_tfs);
1097         break;
1098     default:
1099         trace_execute_ncq_command_unsup(ad->hba, port,
1100                                         ncq_tfs->tag, ncq_tfs->cmd);
1101         ncq_err(ncq_tfs);
1102     }
1103 }
1104 
1105 
1106 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis,
1107                                 uint8_t slot)
1108 {
1109     AHCIDevice *ad = &s->dev[port];
1110     const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis;
1111     uint8_t tag = ncq_fis->tag >> 3;
1112     NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];
1113     size_t size;
1114 
1115     g_assert(is_ncq(ncq_fis->command));
1116     if (ncq_tfs->used) {
1117         /* error - already in use */
1118         qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n",
1119                       __func__, tag);
1120         return;
1121     }
1122 
1123     ncq_tfs->used = 1;
1124     ncq_tfs->drive = ad;
1125     ncq_tfs->slot = slot;
1126     ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot];
1127     ncq_tfs->cmd = ncq_fis->command;
1128     ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
1129                    ((uint64_t)ncq_fis->lba4 << 32) |
1130                    ((uint64_t)ncq_fis->lba3 << 24) |
1131                    ((uint64_t)ncq_fis->lba2 << 16) |
1132                    ((uint64_t)ncq_fis->lba1 << 8) |
1133                    (uint64_t)ncq_fis->lba0;
1134     ncq_tfs->tag = tag;
1135 
1136     /* Sanity-check the NCQ packet */
1137     if (tag != slot) {
1138         trace_process_ncq_command_mismatch(s, port, tag, slot);
1139     }
1140 
1141     if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {
1142         trace_process_ncq_command_aux(s, port, tag);
1143     }
1144     if (ncq_fis->prio || ncq_fis->icc) {
1145         trace_process_ncq_command_prioicc(s, port, tag);
1146     }
1147     if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {
1148         trace_process_ncq_command_fua(s, port, tag);
1149     }
1150     if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {
1151         trace_process_ncq_command_rarc(s, port, tag);
1152     }
1153 
1154     ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |
1155                              ncq_fis->sector_count_low);
1156     if (!ncq_tfs->sector_count) {
1157         ncq_tfs->sector_count = 0x10000;
1158     }
1159     size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE;
1160     ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0);
1161 
1162     if (ncq_tfs->sglist.size < size) {
1163         error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") "
1164                      "is smaller than the requested size (0x%zx)",
1165                      ncq_tfs->sglist.size, size);
1166         ncq_err(ncq_tfs);
1167         ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
1168         return;
1169     } else if (ncq_tfs->sglist.size != size) {
1170         trace_process_ncq_command_large(s, port, tag,
1171                                         ncq_tfs->sglist.size, size);
1172     }
1173 
1174     trace_process_ncq_command(s, port, tag,
1175                               ncq_fis->command,
1176                               ncq_tfs->lba,
1177                               ncq_tfs->lba + ncq_tfs->sector_count - 1);
1178     execute_ncq_command(ncq_tfs);
1179 }
1180 
1181 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot)
1182 {
1183     if (port >= s->ports || slot >= AHCI_MAX_CMDS) {
1184         return NULL;
1185     }
1186 
1187     return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL;
1188 }
1189 
1190 static void handle_reg_h2d_fis(AHCIState *s, int port,
1191                                uint8_t slot, const uint8_t *cmd_fis)
1192 {
1193     IDEState *ide_state = &s->dev[port].port.ifs[0];
1194     AHCICmdHdr *cmd = get_cmd_header(s, port, slot);
1195     uint16_t opts = le16_to_cpu(cmd->opts);
1196 
1197     if (cmd_fis[1] & 0x0F) {
1198         trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1],
1199                                      cmd_fis[2], cmd_fis[3]);
1200         return;
1201     }
1202 
1203     if (cmd_fis[1] & 0x70) {
1204         trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1],
1205                                      cmd_fis[2], cmd_fis[3]);
1206         return;
1207     }
1208 
1209     if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) {
1210         switch (s->dev[port].port_state) {
1211         case STATE_RUN:
1212             if (cmd_fis[15] & ATA_SRST) {
1213                 s->dev[port].port_state = STATE_RESET;
1214             }
1215             break;
1216         case STATE_RESET:
1217             if (!(cmd_fis[15] & ATA_SRST)) {
1218                 ahci_reset_port(s, port);
1219             }
1220             break;
1221         }
1222         return;
1223     }
1224 
1225     /* Check for NCQ command */
1226     if (is_ncq(cmd_fis[2])) {
1227         process_ncq_command(s, port, cmd_fis, slot);
1228         return;
1229     }
1230 
1231     /* Decompose the FIS:
1232      * AHCI does not interpret FIS packets, it only forwards them.
1233      * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1234      * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1235      *
1236      * ATA4 describes sector number for LBA28/CHS commands.
1237      * ATA6 describes sector number for LBA48 commands.
1238      * ATA8 deprecates CHS fully, describing only LBA28/48.
1239      *
1240      * We dutifully convert the FIS into IDE registers, and allow the
1241      * core layer to interpret them as needed. */
1242     ide_state->feature = cmd_fis[3];
1243     ide_state->sector = cmd_fis[4];      /* LBA 7:0 */
1244     ide_state->lcyl = cmd_fis[5];        /* LBA 15:8  */
1245     ide_state->hcyl = cmd_fis[6];        /* LBA 23:16 */
1246     ide_state->select = cmd_fis[7];      /* LBA 27:24 (LBA28) */
1247     ide_state->hob_sector = cmd_fis[8];  /* LBA 31:24 */
1248     ide_state->hob_lcyl = cmd_fis[9];    /* LBA 39:32 */
1249     ide_state->hob_hcyl = cmd_fis[10];   /* LBA 47:40 */
1250     ide_state->hob_feature = cmd_fis[11];
1251     ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
1252     /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1253     /* 15: Only valid when UPDATE_COMMAND not set. */
1254 
1255     /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1256      * table to ide_state->io_buffer */
1257     if (opts & AHCI_CMD_ATAPI) {
1258         memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
1259         if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) {
1260             char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10);
1261             trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
1262             g_free(pretty_fis);
1263         }
1264     }
1265 
1266     ide_state->error = 0;
1267     s->dev[port].done_first_drq = false;
1268     /* Reset transferred byte counter */
1269     cmd->status = 0;
1270 
1271     /* We're ready to process the command in FIS byte 2. */
1272     ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]);
1273 }
1274 
1275 static int handle_cmd(AHCIState *s, int port, uint8_t slot)
1276 {
1277     IDEState *ide_state;
1278     uint64_t tbl_addr;
1279     AHCICmdHdr *cmd;
1280     uint8_t *cmd_fis;
1281     dma_addr_t cmd_len;
1282 
1283     if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1284         /* Engine currently busy, try again later */
1285         trace_handle_cmd_busy(s, port);
1286         return -1;
1287     }
1288 
1289     if (!s->dev[port].lst) {
1290         trace_handle_cmd_nolist(s, port);
1291         return -1;
1292     }
1293     cmd = get_cmd_header(s, port, slot);
1294     /* remember current slot handle for later */
1295     s->dev[port].cur_cmd = cmd;
1296 
1297     /* The device we are working for */
1298     ide_state = &s->dev[port].port.ifs[0];
1299     if (!ide_state->blk) {
1300         trace_handle_cmd_badport(s, port);
1301         return -1;
1302     }
1303 
1304     tbl_addr = le64_to_cpu(cmd->tbl_addr);
1305     cmd_len = 0x80;
1306     cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
1307                              DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
1308     if (!cmd_fis) {
1309         trace_handle_cmd_badfis(s, port);
1310         return -1;
1311     } else if (cmd_len != 0x80) {
1312         ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);
1313         trace_handle_cmd_badmap(s, port, cmd_len);
1314         goto out;
1315     }
1316     if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) {
1317         char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80);
1318         trace_handle_cmd_fis_dump(s, port, pretty_fis);
1319         g_free(pretty_fis);
1320     }
1321     switch (cmd_fis[0]) {
1322         case SATA_FIS_TYPE_REGISTER_H2D:
1323             handle_reg_h2d_fis(s, port, slot, cmd_fis);
1324             break;
1325         default:
1326             trace_handle_cmd_unhandled_fis(s, port,
1327                                            cmd_fis[0], cmd_fis[1], cmd_fis[2]);
1328             break;
1329     }
1330 
1331 out:
1332     dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE,
1333                      cmd_len);
1334 
1335     if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1336         /* async command, complete later */
1337         s->dev[port].busy_slot = slot;
1338         return -1;
1339     }
1340 
1341     /* done handling the command */
1342     return 0;
1343 }
1344 
1345 /* Transfer PIO data between RAM and device */
1346 static void ahci_pio_transfer(const IDEDMA *dma)
1347 {
1348     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1349     IDEState *s = &ad->port.ifs[0];
1350     uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
1351     /* write == ram -> device */
1352     uint16_t opts = le16_to_cpu(ad->cur_cmd->opts);
1353     int is_write = opts & AHCI_CMD_WRITE;
1354     int is_atapi = opts & AHCI_CMD_ATAPI;
1355     int has_sglist = 0;
1356     bool pio_fis_i;
1357 
1358     /* The PIO Setup FIS is received prior to transfer, but the interrupt
1359      * is only triggered after data is received.
1360      *
1361      * The device only sets the 'I' bit in the PIO Setup FIS for device->host
1362      * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after
1363      * the first (see "DPIOO1").  The latter is consistent with the spec's
1364      * description of the PACKET protocol, where the command part of ATAPI requests
1365      * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests
1366      * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs.
1367      */
1368     pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write);
1369     ahci_write_fis_pio(ad, size, pio_fis_i);
1370 
1371     if (is_atapi && !ad->done_first_drq) {
1372         /* already prepopulated iobuffer */
1373         goto out;
1374     }
1375 
1376     if (ahci_dma_prepare_buf(dma, size)) {
1377         has_sglist = 1;
1378     }
1379 
1380     trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
1381                             size, is_atapi ? "atapi" : "ata",
1382                             has_sglist ? "" : "o");
1383 
1384     if (has_sglist && size) {
1385         const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
1386 
1387         if (is_write) {
1388             dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs);
1389         } else {
1390             dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs);
1391         }
1392     }
1393 
1394     /* Update number of transferred bytes, destroy sglist */
1395     dma_buf_commit(s, size);
1396 
1397 out:
1398     /* declare that we processed everything */
1399     s->data_ptr = s->data_end;
1400 
1401     ad->done_first_drq = true;
1402     if (pio_fis_i) {
1403         ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
1404     }
1405 }
1406 
1407 static void ahci_start_dma(const IDEDMA *dma, IDEState *s,
1408                            BlockCompletionFunc *dma_cb)
1409 {
1410     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1411     trace_ahci_start_dma(ad->hba, ad->port_no);
1412     s->io_buffer_offset = 0;
1413     dma_cb(s, 0);
1414 }
1415 
1416 static void ahci_restart_dma(const IDEDMA *dma)
1417 {
1418     /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset.  */
1419 }
1420 
1421 /**
1422  * IDE/PIO restarts are handled by the core layer, but NCQ commands
1423  * need an extra kick from the AHCI HBA.
1424  */
1425 static void ahci_restart(const IDEDMA *dma)
1426 {
1427     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1428     int i;
1429 
1430     for (i = 0; i < AHCI_MAX_CMDS; i++) {
1431         NCQTransferState *ncq_tfs = &ad->ncq_tfs[i];
1432         if (ncq_tfs->halt) {
1433             execute_ncq_command(ncq_tfs);
1434         }
1435     }
1436 }
1437 
1438 /**
1439  * Called in DMA and PIO R/W chains to read the PRDT.
1440  * Not shared with NCQ pathways.
1441  */
1442 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit)
1443 {
1444     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1445     IDEState *s = &ad->port.ifs[0];
1446 
1447     if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,
1448                              limit, s->io_buffer_offset) == -1) {
1449         trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no);
1450         return -1;
1451     }
1452     s->io_buffer_size = s->sg.size;
1453 
1454     trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size);
1455     return s->io_buffer_size;
1456 }
1457 
1458 /**
1459  * Updates the command header with a bytes-read value.
1460  * Called via dma_buf_commit, for both DMA and PIO paths.
1461  * sglist destruction is handled within dma_buf_commit.
1462  */
1463 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes)
1464 {
1465     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1466 
1467     tx_bytes += le32_to_cpu(ad->cur_cmd->status);
1468     ad->cur_cmd->status = cpu_to_le32(tx_bytes);
1469 }
1470 
1471 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
1472 {
1473     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1474     IDEState *s = &ad->port.ifs[0];
1475     uint8_t *p = s->io_buffer + s->io_buffer_index;
1476     int l = s->io_buffer_size - s->io_buffer_index;
1477 
1478     if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) {
1479         return 0;
1480     }
1481 
1482     if (is_write) {
1483         dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
1484     } else {
1485         dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
1486     }
1487 
1488     /* free sglist, update byte count */
1489     dma_buf_commit(s, l);
1490     s->io_buffer_index += l;
1491 
1492     trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l);
1493     return 1;
1494 }
1495 
1496 static void ahci_cmd_done(const IDEDMA *dma)
1497 {
1498     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1499 
1500     trace_ahci_cmd_done(ad->hba, ad->port_no);
1501 
1502     /* no longer busy */
1503     if (ad->busy_slot != -1) {
1504         ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
1505         ad->busy_slot = -1;
1506     }
1507 
1508     /* update d2h status */
1509     ahci_write_fis_d2h(ad);
1510 
1511     if (ad->port_regs.cmd_issue && !ad->check_bh) {
1512         ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad,
1513                                            &ad->mem_reentrancy_guard);
1514         qemu_bh_schedule(ad->check_bh);
1515     }
1516 }
1517 
1518 static void ahci_irq_set(void *opaque, int n, int level)
1519 {
1520     qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level);
1521 }
1522 
1523 static const IDEDMAOps ahci_dma_ops = {
1524     .start_dma = ahci_start_dma,
1525     .restart = ahci_restart,
1526     .restart_dma = ahci_restart_dma,
1527     .pio_transfer = ahci_pio_transfer,
1528     .prepare_buf = ahci_dma_prepare_buf,
1529     .commit_buf = ahci_commit_buf,
1530     .rw_buf = ahci_dma_rw_buf,
1531     .cmd_done = ahci_cmd_done,
1532 };
1533 
1534 void ahci_init(AHCIState *s, DeviceState *qdev)
1535 {
1536     s->container = qdev;
1537     /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1538     memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1539                           "ahci", AHCI_MEM_BAR_SIZE);
1540     memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1541                           "ahci-idp", 32);
1542 }
1543 
1544 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1545 {
1546     qemu_irq *irqs;
1547     int i;
1548 
1549     s->as = as;
1550     s->ports = ports;
1551     s->dev = g_new0(AHCIDevice, ports);
1552     ahci_reg_init(s);
1553     irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1554     for (i = 0; i < s->ports; i++) {
1555         AHCIDevice *ad = &s->dev[i];
1556 
1557         ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
1558         ide_bus_init_output_irq(&ad->port, irqs[i]);
1559 
1560         ad->hba = s;
1561         ad->port_no = i;
1562         ad->port.dma = &ad->dma;
1563         ad->port.dma->ops = &ahci_dma_ops;
1564         ide_bus_register_restart_cb(&ad->port);
1565     }
1566     g_free(irqs);
1567 }
1568 
1569 void ahci_uninit(AHCIState *s)
1570 {
1571     int i, j;
1572 
1573     for (i = 0; i < s->ports; i++) {
1574         AHCIDevice *ad = &s->dev[i];
1575 
1576         for (j = 0; j < 2; j++) {
1577             IDEState *s = &ad->port.ifs[j];
1578 
1579             ide_exit(s);
1580         }
1581         object_unparent(OBJECT(&ad->port));
1582     }
1583 
1584     g_free(s->dev);
1585 }
1586 
1587 void ahci_reset(AHCIState *s)
1588 {
1589     AHCIPortRegs *pr;
1590     int i;
1591 
1592     trace_ahci_reset(s);
1593 
1594     s->control_regs.irqstatus = 0;
1595     /* AHCI Enable (AE)
1596      * The implementation of this bit is dependent upon the value of the
1597      * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1598      * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1599      * read-only and shall have a reset value of '1'.
1600      *
1601      * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1602      */
1603     s->control_regs.ghc = HOST_CTL_AHCI_EN;
1604 
1605     for (i = 0; i < s->ports; i++) {
1606         pr = &s->dev[i].port_regs;
1607         pr->irq_stat = 0;
1608         pr->irq_mask = 0;
1609         pr->scr_ctl = 0;
1610         pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1611         ahci_reset_port(s, i);
1612     }
1613 }
1614 
1615 static const VMStateDescription vmstate_ncq_tfs = {
1616     .name = "ncq state",
1617     .version_id = 1,
1618     .fields = (VMStateField[]) {
1619         VMSTATE_UINT32(sector_count, NCQTransferState),
1620         VMSTATE_UINT64(lba, NCQTransferState),
1621         VMSTATE_UINT8(tag, NCQTransferState),
1622         VMSTATE_UINT8(cmd, NCQTransferState),
1623         VMSTATE_UINT8(slot, NCQTransferState),
1624         VMSTATE_BOOL(used, NCQTransferState),
1625         VMSTATE_BOOL(halt, NCQTransferState),
1626         VMSTATE_END_OF_LIST()
1627     },
1628 };
1629 
1630 static const VMStateDescription vmstate_ahci_device = {
1631     .name = "ahci port",
1632     .version_id = 1,
1633     .fields = (VMStateField[]) {
1634         VMSTATE_IDE_BUS(port, AHCIDevice),
1635         VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice),
1636         VMSTATE_UINT32(port_state, AHCIDevice),
1637         VMSTATE_UINT32(finished, AHCIDevice),
1638         VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
1639         VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
1640         VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
1641         VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
1642         VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
1643         VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
1644         VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
1645         VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
1646         VMSTATE_UINT32(port_regs.sig, AHCIDevice),
1647         VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
1648         VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
1649         VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
1650         VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
1651         VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
1652         VMSTATE_BOOL(done_first_drq, AHCIDevice),
1653         VMSTATE_INT32(busy_slot, AHCIDevice),
1654         VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
1655         VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,
1656                              1, vmstate_ncq_tfs, NCQTransferState),
1657         VMSTATE_END_OF_LIST()
1658     },
1659 };
1660 
1661 static int ahci_state_post_load(void *opaque, int version_id)
1662 {
1663     int i, j;
1664     struct AHCIDevice *ad;
1665     NCQTransferState *ncq_tfs;
1666     AHCIPortRegs *pr;
1667     AHCIState *s = opaque;
1668 
1669     for (i = 0; i < s->ports; i++) {
1670         ad = &s->dev[i];
1671         pr = &ad->port_regs;
1672 
1673         if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) {
1674             error_report("AHCI: DMA engine should be off, but status bit "
1675                          "indicates it is still running.");
1676             return -1;
1677         }
1678         if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) {
1679             error_report("AHCI: FIS RX engine should be off, but status bit "
1680                          "indicates it is still running.");
1681             return -1;
1682         }
1683 
1684         /* After a migrate, the DMA/FIS engines are "off" and
1685          * need to be conditionally restarted */
1686         pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
1687         if (ahci_cond_start_engines(ad) != 0) {
1688             return -1;
1689         }
1690 
1691         for (j = 0; j < AHCI_MAX_CMDS; j++) {
1692             ncq_tfs = &ad->ncq_tfs[j];
1693             ncq_tfs->drive = ad;
1694 
1695             if (ncq_tfs->used != ncq_tfs->halt) {
1696                 return -1;
1697             }
1698             if (!ncq_tfs->halt) {
1699                 continue;
1700             }
1701             if (!is_ncq(ncq_tfs->cmd)) {
1702                 return -1;
1703             }
1704             if (ncq_tfs->slot != ncq_tfs->tag) {
1705                 return -1;
1706             }
1707             /* If ncq_tfs->halt is justly set, the engine should be engaged,
1708              * and the command list buffer should be mapped. */
1709             ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot);
1710             if (!ncq_tfs->cmdh) {
1711                 return -1;
1712             }
1713             ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist,
1714                                  ncq_tfs->cmdh,
1715                                  ncq_tfs->sector_count * BDRV_SECTOR_SIZE,
1716                                  0);
1717             if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) {
1718                 return -1;
1719             }
1720         }
1721 
1722 
1723         /*
1724          * If an error is present, ad->busy_slot will be valid and not -1.
1725          * In this case, an operation is waiting to resume and will re-check
1726          * for additional AHCI commands to execute upon completion.
1727          *
1728          * In the case where no error was present, busy_slot will be -1,
1729          * and we should check to see if there are additional commands waiting.
1730          */
1731         if (ad->busy_slot == -1) {
1732             check_cmd(s, i);
1733         } else {
1734             /* We are in the middle of a command, and may need to access
1735              * the command header in guest memory again. */
1736             if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) {
1737                 return -1;
1738             }
1739             ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot);
1740         }
1741     }
1742 
1743     return 0;
1744 }
1745 
1746 const VMStateDescription vmstate_ahci = {
1747     .name = "ahci",
1748     .version_id = 1,
1749     .post_load = ahci_state_post_load,
1750     .fields = (VMStateField[]) {
1751         VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
1752                                      vmstate_ahci_device, AHCIDevice),
1753         VMSTATE_UINT32(control_regs.cap, AHCIState),
1754         VMSTATE_UINT32(control_regs.ghc, AHCIState),
1755         VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
1756         VMSTATE_UINT32(control_regs.impl, AHCIState),
1757         VMSTATE_UINT32(control_regs.version, AHCIState),
1758         VMSTATE_UINT32(idp_index, AHCIState),
1759         VMSTATE_INT32_EQUAL(ports, AHCIState, NULL),
1760         VMSTATE_END_OF_LIST()
1761     },
1762 };
1763 
1764 static const VMStateDescription vmstate_sysbus_ahci = {
1765     .name = "sysbus-ahci",
1766     .fields = (VMStateField[]) {
1767         VMSTATE_AHCI(ahci, SysbusAHCIState),
1768         VMSTATE_END_OF_LIST()
1769     },
1770 };
1771 
1772 static void sysbus_ahci_reset(DeviceState *dev)
1773 {
1774     SysbusAHCIState *s = SYSBUS_AHCI(dev);
1775 
1776     ahci_reset(&s->ahci);
1777 }
1778 
1779 static void sysbus_ahci_init(Object *obj)
1780 {
1781     SysbusAHCIState *s = SYSBUS_AHCI(obj);
1782     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1783 
1784     ahci_init(&s->ahci, DEVICE(obj));
1785 
1786     sysbus_init_mmio(sbd, &s->ahci.mem);
1787     sysbus_init_irq(sbd, &s->ahci.irq);
1788 }
1789 
1790 static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1791 {
1792     SysbusAHCIState *s = SYSBUS_AHCI(dev);
1793 
1794     ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
1795 }
1796 
1797 static Property sysbus_ahci_properties[] = {
1798     DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1799     DEFINE_PROP_END_OF_LIST(),
1800 };
1801 
1802 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1803 {
1804     DeviceClass *dc = DEVICE_CLASS(klass);
1805 
1806     dc->realize = sysbus_ahci_realize;
1807     dc->vmsd = &vmstate_sysbus_ahci;
1808     device_class_set_props(dc, sysbus_ahci_properties);
1809     dc->reset = sysbus_ahci_reset;
1810     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1811 }
1812 
1813 static const TypeInfo sysbus_ahci_info = {
1814     .name          = TYPE_SYSBUS_AHCI,
1815     .parent        = TYPE_SYS_BUS_DEVICE,
1816     .instance_size = sizeof(SysbusAHCIState),
1817     .instance_init = sysbus_ahci_init,
1818     .class_init    = sysbus_ahci_class_init,
1819 };
1820 
1821 static void sysbus_ahci_register_types(void)
1822 {
1823     type_register_static(&sysbus_ahci_info);
1824 }
1825 
1826 type_init(sysbus_ahci_register_types)
1827 
1828 int32_t ahci_get_num_ports(PCIDevice *dev)
1829 {
1830     AHCIPCIState *d = ICH9_AHCI(dev);
1831     AHCIState *ahci = &d->ahci;
1832 
1833     return ahci->ports;
1834 }
1835 
1836 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
1837 {
1838     AHCIPCIState *d = ICH9_AHCI(dev);
1839     AHCIState *ahci = &d->ahci;
1840     int i;
1841 
1842     for (i = 0; i < ahci->ports; i++) {
1843         if (hd[i] == NULL) {
1844             continue;
1845         }
1846         ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
1847     }
1848 
1849 }
1850