1 /* 2 * ASPEED I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2023 Google LLC 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/log.h" 13 #include "qemu/error-report.h" 14 #include "hw/i3c/aspeed_i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 /* I3C Controller Registers */ 22 REG32(I3C1_REG0, 0x10) 23 REG32(I3C1_REG1, 0x14) 24 FIELD(I3C1_REG1, I2C_MODE, 0, 1) 25 FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1) 26 FIELD(I3C1_REG1, ACT_MODE, 2, 2) 27 FIELD(I3C1_REG1, PENDING_INT, 4, 4) 28 FIELD(I3C1_REG1, SA, 8, 7) 29 FIELD(I3C1_REG1, SA_EN, 15, 1) 30 FIELD(I3C1_REG1, INST_ID, 16, 4) 31 REG32(I3C2_REG0, 0x20) 32 REG32(I3C2_REG1, 0x24) 33 FIELD(I3C2_REG1, I2C_MODE, 0, 1) 34 FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1) 35 FIELD(I3C2_REG1, ACT_MODE, 2, 2) 36 FIELD(I3C2_REG1, PENDING_INT, 4, 4) 37 FIELD(I3C2_REG1, SA, 8, 7) 38 FIELD(I3C2_REG1, SA_EN, 15, 1) 39 FIELD(I3C2_REG1, INST_ID, 16, 4) 40 REG32(I3C3_REG0, 0x30) 41 REG32(I3C3_REG1, 0x34) 42 FIELD(I3C3_REG1, I2C_MODE, 0, 1) 43 FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1) 44 FIELD(I3C3_REG1, ACT_MODE, 2, 2) 45 FIELD(I3C3_REG1, PENDING_INT, 4, 4) 46 FIELD(I3C3_REG1, SA, 8, 7) 47 FIELD(I3C3_REG1, SA_EN, 15, 1) 48 FIELD(I3C3_REG1, INST_ID, 16, 4) 49 REG32(I3C4_REG0, 0x40) 50 REG32(I3C4_REG1, 0x44) 51 FIELD(I3C4_REG1, I2C_MODE, 0, 1) 52 FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1) 53 FIELD(I3C4_REG1, ACT_MODE, 2, 2) 54 FIELD(I3C4_REG1, PENDING_INT, 4, 4) 55 FIELD(I3C4_REG1, SA, 8, 7) 56 FIELD(I3C4_REG1, SA_EN, 15, 1) 57 FIELD(I3C4_REG1, INST_ID, 16, 4) 58 REG32(I3C5_REG0, 0x50) 59 REG32(I3C5_REG1, 0x54) 60 FIELD(I3C5_REG1, I2C_MODE, 0, 1) 61 FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1) 62 FIELD(I3C5_REG1, ACT_MODE, 2, 2) 63 FIELD(I3C5_REG1, PENDING_INT, 4, 4) 64 FIELD(I3C5_REG1, SA, 8, 7) 65 FIELD(I3C5_REG1, SA_EN, 15, 1) 66 FIELD(I3C5_REG1, INST_ID, 16, 4) 67 REG32(I3C6_REG0, 0x60) 68 REG32(I3C6_REG1, 0x64) 69 FIELD(I3C6_REG1, I2C_MODE, 0, 1) 70 FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1) 71 FIELD(I3C6_REG1, ACT_MODE, 2, 2) 72 FIELD(I3C6_REG1, PENDING_INT, 4, 4) 73 FIELD(I3C6_REG1, SA, 8, 7) 74 FIELD(I3C6_REG1, SA_EN, 15, 1) 75 FIELD(I3C6_REG1, INST_ID, 16, 4) 76 77 /* I3C Device Registers */ 78 REG32(DEVICE_CTRL, 0x00) 79 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 80 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 81 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 82 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 83 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 84 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 85 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 86 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 87 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 88 REG32(DEVICE_ADDR, 0x04) 89 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 90 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 91 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 92 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 93 REG32(HW_CAPABILITY, 0x08) 94 FIELD(HW_CAPABILITY, ENTDAA, 0, 1) 95 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 96 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 97 REG32(COMMAND_QUEUE_PORT, 0x0c) 98 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 99 /* Transfer command structure */ 100 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 101 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 102 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 103 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 104 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 105 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 106 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 107 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 108 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 109 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 110 /* Transfer argument data structure */ 111 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 112 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 113 /* Short data argument data structure */ 114 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 115 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 116 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 117 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 118 /* Address assignment command structure */ 119 /* 120 * bits 3..21 and 26..31 are the same as the transfer command structure, or 121 * marked as reserved. 122 */ 123 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 124 REG32(RESPONSE_QUEUE_PORT, 0x10) 125 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 126 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 127 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 128 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 129 REG32(RX_TX_DATA_PORT, 0x14) 130 REG32(IBI_QUEUE_STATUS, 0x18) 131 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 132 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 133 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 134 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 135 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 136 REG32(IBI_QUEUE_DATA, 0x18) 137 REG32(QUEUE_THLD_CTRL, 0x1c) 138 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 139 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 140 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 141 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 142 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 143 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 144 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 145 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 146 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 147 REG32(IBI_QUEUE_CTRL, 0x24) 148 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 149 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 150 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 151 REG32(IBI_MR_REQ_REJECT, 0x2c) 152 REG32(IBI_SIR_REQ_REJECT, 0x30) 153 REG32(RESET_CTRL, 0x34) 154 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 155 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 156 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 157 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 158 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 159 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 160 REG32(SLV_EVENT_CTRL, 0x38) 161 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 162 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 163 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 164 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 165 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 166 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 167 REG32(INTR_STATUS, 0x3c) 168 FIELD(INTR_STATUS, TX_THLD, 0, 1) 169 FIELD(INTR_STATUS, RX_THLD, 1, 1) 170 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 171 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 172 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 173 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 174 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 175 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 176 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 177 FIELD(INTR_STATUS, DEFSLV, 10, 1) 178 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 179 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 180 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 181 REG32(INTR_STATUS_EN, 0x40) 182 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 183 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 184 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 185 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 186 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 187 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 188 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 189 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 190 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 191 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 192 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 193 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 194 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 195 REG32(INTR_SIGNAL_EN, 0x44) 196 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 197 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 198 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 199 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 200 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 201 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 202 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 203 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 204 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 205 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 206 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 207 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 208 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 209 REG32(INTR_FORCE, 0x48) 210 FIELD(INTR_FORCE, TX_THLD, 0, 1) 211 FIELD(INTR_FORCE, RX_THLD, 1, 1) 212 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 213 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 214 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 215 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 216 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 217 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 218 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 219 FIELD(INTR_FORCE, DEFSLV, 10, 1) 220 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 221 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 222 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 223 REG32(QUEUE_STATUS_LEVEL, 0x4c) 224 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 225 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 226 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 227 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 228 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 229 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 230 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 231 REG32(PRESENT_STATE, 0x54) 232 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 233 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 234 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 235 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 236 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 237 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 238 REG32(CCC_DEVICE_STATUS, 0x58) 239 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 240 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 241 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 242 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 243 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 244 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 245 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 246 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 247 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 248 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 249 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 250 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 251 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 252 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 253 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 254 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 255 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 256 REG32(SLV_MIPI_PID_VALUE, 0x70) 257 REG32(SLV_PID_VALUE, 0x74) 258 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 259 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 260 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 261 REG32(SLV_CHAR_CTRL, 0x78) 262 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 263 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 264 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 265 REG32(SLV_MAX_LEN, 0x7c) 266 FIELD(SLV_MAX_LEN, MWL, 0, 16) 267 FIELD(SLV_MAX_LEN, MRL, 16, 16) 268 REG32(MAX_READ_TURNAROUND, 0x80) 269 REG32(MAX_DATA_SPEED, 0x84) 270 REG32(SLV_DEBUG_STATUS, 0x88) 271 REG32(SLV_INTR_REQ, 0x8c) 272 FIELD(SLV_INTR_REQ, SIR, 0, 1) 273 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 274 FIELD(SLV_INTR_REQ, MIR, 3, 1) 275 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 276 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 277 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 278 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 279 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 280 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 281 REG32(SCL_I3C_OD_TIMING, 0xb4) 282 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 283 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 284 REG32(SCL_I3C_PP_TIMING, 0xb8) 285 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 286 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 287 REG32(SCL_I2C_FM_TIMING, 0xbc) 288 REG32(SCL_I2C_FMP_TIMING, 0xc0) 289 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 290 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 291 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 292 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 293 REG32(BUS_FREE_TIMING, 0xd4) 294 REG32(BUS_IDLE_TIMING, 0xd8) 295 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 296 REG32(I3C_VER_ID, 0xe0) 297 REG32(I3C_VER_TYPE, 0xe4) 298 REG32(EXTENDED_CAPABILITY, 0xe8) 299 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 300 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 301 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 302 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 303 REG32(SLAVE_CONFIG, 0xec) 304 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 305 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 306 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 307 /* Device characteristic table fields */ 308 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 309 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 310 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 311 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 312 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 313 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 314 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 315 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 316 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 317 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 318 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 319 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 320 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 321 /* Dev addr table fields */ 322 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 323 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 324 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 325 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 326 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 327 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 328 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 329 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 330 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 331 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 332 333 static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { 334 [R_HW_CAPABILITY] = 0x000e00bf, 335 [R_QUEUE_THLD_CTRL] = 0x01000101, 336 [R_I3C_VER_ID] = 0x3130302a, 337 [R_I3C_VER_TYPE] = 0x6c633033, 338 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 339 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 340 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 341 [R_SLV_MAX_LEN] = 0x00ff00ff, 342 }; 343 344 static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, 345 unsigned size) 346 { 347 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 348 uint32_t addr = offset >> 2; 349 uint64_t value; 350 351 switch (addr) { 352 case R_COMMAND_QUEUE_PORT: 353 value = 0; 354 break; 355 default: 356 value = s->regs[addr]; 357 break; 358 } 359 360 trace_aspeed_i3c_device_read(s->id, offset, value); 361 362 return value; 363 } 364 365 static void aspeed_i3c_device_write(void *opaque, hwaddr offset, 366 uint64_t value, unsigned size) 367 { 368 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 369 uint32_t addr = offset >> 2; 370 371 trace_aspeed_i3c_device_write(s->id, offset, value); 372 373 switch (addr) { 374 case R_HW_CAPABILITY: 375 case R_RESPONSE_QUEUE_PORT: 376 case R_IBI_QUEUE_DATA: 377 case R_QUEUE_STATUS_LEVEL: 378 case R_PRESENT_STATE: 379 case R_CCC_DEVICE_STATUS: 380 case R_DEVICE_ADDR_TABLE_POINTER: 381 case R_VENDOR_SPECIFIC_REG_POINTER: 382 case R_SLV_CHAR_CTRL: 383 case R_SLV_MAX_LEN: 384 case R_MAX_READ_TURNAROUND: 385 case R_I3C_VER_ID: 386 case R_I3C_VER_TYPE: 387 case R_EXTENDED_CAPABILITY: 388 qemu_log_mask(LOG_GUEST_ERROR, 389 "%s: write to readonly register[0x%02" HWADDR_PRIx 390 "] = 0x%08" PRIx64 "\n", 391 __func__, offset, value); 392 break; 393 case R_RX_TX_DATA_PORT: 394 break; 395 case R_RESET_CTRL: 396 break; 397 default: 398 s->regs[addr] = value; 399 break; 400 } 401 } 402 403 static const VMStateDescription aspeed_i3c_device_vmstate = { 404 .name = TYPE_ASPEED_I3C, 405 .version_id = 1, 406 .minimum_version_id = 1, 407 .fields = (const VMStateField[]){ 408 VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), 409 VMSTATE_END_OF_LIST(), 410 } 411 }; 412 413 static const MemoryRegionOps aspeed_i3c_device_ops = { 414 .read = aspeed_i3c_device_read, 415 .write = aspeed_i3c_device_write, 416 .endianness = DEVICE_LITTLE_ENDIAN, 417 }; 418 419 static void aspeed_i3c_device_reset(DeviceState *dev) 420 { 421 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 422 423 memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); 424 } 425 426 static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) 427 { 428 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 429 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", 430 s->id); 431 432 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 433 434 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, 435 s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); 436 } 437 438 static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) 439 { 440 AspeedI3CState *s = ASPEED_I3C(opaque); 441 uint64_t val = 0; 442 443 val = s->regs[addr >> 2]; 444 445 trace_aspeed_i3c_read(addr, val); 446 447 return val; 448 } 449 450 static void aspeed_i3c_write(void *opaque, 451 hwaddr addr, 452 uint64_t data, 453 unsigned int size) 454 { 455 AspeedI3CState *s = ASPEED_I3C(opaque); 456 457 trace_aspeed_i3c_write(addr, data); 458 459 addr >>= 2; 460 461 /* I3C controller register */ 462 switch (addr) { 463 case R_I3C1_REG1: 464 case R_I3C2_REG1: 465 case R_I3C3_REG1: 466 case R_I3C4_REG1: 467 case R_I3C5_REG1: 468 case R_I3C6_REG1: 469 if (data & R_I3C1_REG1_I2C_MODE_MASK) { 470 qemu_log_mask(LOG_UNIMP, 471 "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx 472 "]=%08" PRIx64 "\n", 473 __func__, addr << 2, data); 474 break; 475 } 476 if (data & R_I3C1_REG1_SA_EN_MASK) { 477 qemu_log_mask(LOG_UNIMP, 478 "%s: Unsupported slave mode [%08" HWADDR_PRIx 479 "]=0x%08" PRIx64 "\n", 480 __func__, addr << 2, data); 481 break; 482 } 483 s->regs[addr] = data; 484 break; 485 default: 486 s->regs[addr] = data; 487 break; 488 } 489 } 490 491 static const MemoryRegionOps aspeed_i3c_ops = { 492 .read = aspeed_i3c_read, 493 .write = aspeed_i3c_write, 494 .endianness = DEVICE_LITTLE_ENDIAN, 495 .valid = { 496 .min_access_size = 1, 497 .max_access_size = 4, 498 } 499 }; 500 501 static void aspeed_i3c_reset(DeviceState *dev) 502 { 503 AspeedI3CState *s = ASPEED_I3C(dev); 504 memset(s->regs, 0, sizeof(s->regs)); 505 } 506 507 static void aspeed_i3c_instance_init(Object *obj) 508 { 509 AspeedI3CState *s = ASPEED_I3C(obj); 510 int i; 511 512 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 513 object_initialize_child(obj, "device[*]", &s->devices[i], 514 TYPE_ASPEED_I3C_DEVICE); 515 } 516 } 517 518 static void aspeed_i3c_realize(DeviceState *dev, Error **errp) 519 { 520 int i; 521 AspeedI3CState *s = ASPEED_I3C(dev); 522 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 523 524 memory_region_init(&s->iomem_container, OBJECT(s), 525 TYPE_ASPEED_I3C ".container", 0x8000); 526 527 sysbus_init_mmio(sbd, &s->iomem_container); 528 529 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s, 530 TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2); 531 532 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); 533 534 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 535 Object *i3c_dev = OBJECT(&s->devices[i]); 536 537 if (!object_property_set_uint(i3c_dev, "device-id", i, errp)) { 538 return; 539 } 540 541 if (!sysbus_realize(SYS_BUS_DEVICE(i3c_dev), errp)) { 542 return; 543 } 544 545 /* 546 * Register Address of I3CX Device = 547 * (Base Address of Global Register) + (Offset of I3CX) + Offset 548 * X = 0, 1, 2, 3, 4, 5 549 * Offset of I3C0 = 0x2000 550 * Offset of I3C1 = 0x3000 551 * Offset of I3C2 = 0x4000 552 * Offset of I3C3 = 0x5000 553 * Offset of I3C4 = 0x6000 554 * Offset of I3C5 = 0x7000 555 */ 556 memory_region_add_subregion(&s->iomem_container, 557 0x2000 + i * 0x1000, &s->devices[i].mr); 558 } 559 560 } 561 562 static Property aspeed_i3c_device_properties[] = { 563 DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), 564 DEFINE_PROP_END_OF_LIST(), 565 }; 566 567 static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) 568 { 569 DeviceClass *dc = DEVICE_CLASS(klass); 570 571 dc->desc = "Aspeed I3C Device"; 572 dc->realize = aspeed_i3c_device_realize; 573 device_class_set_legacy_reset(dc, aspeed_i3c_device_reset); 574 device_class_set_props(dc, aspeed_i3c_device_properties); 575 } 576 577 static const TypeInfo aspeed_i3c_device_info = { 578 .name = TYPE_ASPEED_I3C_DEVICE, 579 .parent = TYPE_SYS_BUS_DEVICE, 580 .instance_size = sizeof(AspeedI3CDevice), 581 .class_init = aspeed_i3c_device_class_init, 582 }; 583 584 static const VMStateDescription vmstate_aspeed_i3c = { 585 .name = TYPE_ASPEED_I3C, 586 .version_id = 1, 587 .minimum_version_id = 1, 588 .fields = (const VMStateField[]) { 589 VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), 590 VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, 591 aspeed_i3c_device_vmstate, AspeedI3CDevice), 592 VMSTATE_END_OF_LIST(), 593 } 594 }; 595 596 static void aspeed_i3c_class_init(ObjectClass *klass, void *data) 597 { 598 DeviceClass *dc = DEVICE_CLASS(klass); 599 600 dc->realize = aspeed_i3c_realize; 601 device_class_set_legacy_reset(dc, aspeed_i3c_reset); 602 dc->desc = "Aspeed I3C Controller"; 603 dc->vmsd = &vmstate_aspeed_i3c; 604 } 605 606 static const TypeInfo aspeed_i3c_info = { 607 .name = TYPE_ASPEED_I3C, 608 .parent = TYPE_SYS_BUS_DEVICE, 609 .instance_init = aspeed_i3c_instance_init, 610 .instance_size = sizeof(AspeedI3CState), 611 .class_init = aspeed_i3c_class_init, 612 }; 613 614 static void aspeed_i3c_register_types(void) 615 { 616 type_register_static(&aspeed_i3c_device_info); 617 type_register_static(&aspeed_i3c_info); 618 } 619 620 type_init(aspeed_i3c_register_types); 621