1 /* 2 * ASPEED I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2023 Google LLC 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/log.h" 13 #include "qemu/error-report.h" 14 #include "hw/i3c/aspeed_i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 /* I3C Controller Registers */ 22 REG32(I3C1_REG0, 0x10) 23 REG32(I3C1_REG1, 0x14) 24 FIELD(I3C1_REG1, I2C_MODE, 0, 1) 25 FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1) 26 FIELD(I3C1_REG1, ACT_MODE, 2, 2) 27 FIELD(I3C1_REG1, PENDING_INT, 4, 4) 28 FIELD(I3C1_REG1, SA, 8, 7) 29 FIELD(I3C1_REG1, SA_EN, 15, 1) 30 FIELD(I3C1_REG1, INST_ID, 16, 4) 31 REG32(I3C2_REG0, 0x20) 32 REG32(I3C2_REG1, 0x24) 33 FIELD(I3C2_REG1, I2C_MODE, 0, 1) 34 FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1) 35 FIELD(I3C2_REG1, ACT_MODE, 2, 2) 36 FIELD(I3C2_REG1, PENDING_INT, 4, 4) 37 FIELD(I3C2_REG1, SA, 8, 7) 38 FIELD(I3C2_REG1, SA_EN, 15, 1) 39 FIELD(I3C2_REG1, INST_ID, 16, 4) 40 REG32(I3C3_REG0, 0x30) 41 REG32(I3C3_REG1, 0x34) 42 FIELD(I3C3_REG1, I2C_MODE, 0, 1) 43 FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1) 44 FIELD(I3C3_REG1, ACT_MODE, 2, 2) 45 FIELD(I3C3_REG1, PENDING_INT, 4, 4) 46 FIELD(I3C3_REG1, SA, 8, 7) 47 FIELD(I3C3_REG1, SA_EN, 15, 1) 48 FIELD(I3C3_REG1, INST_ID, 16, 4) 49 REG32(I3C4_REG0, 0x40) 50 REG32(I3C4_REG1, 0x44) 51 FIELD(I3C4_REG1, I2C_MODE, 0, 1) 52 FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1) 53 FIELD(I3C4_REG1, ACT_MODE, 2, 2) 54 FIELD(I3C4_REG1, PENDING_INT, 4, 4) 55 FIELD(I3C4_REG1, SA, 8, 7) 56 FIELD(I3C4_REG1, SA_EN, 15, 1) 57 FIELD(I3C4_REG1, INST_ID, 16, 4) 58 REG32(I3C5_REG0, 0x50) 59 REG32(I3C5_REG1, 0x54) 60 FIELD(I3C5_REG1, I2C_MODE, 0, 1) 61 FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1) 62 FIELD(I3C5_REG1, ACT_MODE, 2, 2) 63 FIELD(I3C5_REG1, PENDING_INT, 4, 4) 64 FIELD(I3C5_REG1, SA, 8, 7) 65 FIELD(I3C5_REG1, SA_EN, 15, 1) 66 FIELD(I3C5_REG1, INST_ID, 16, 4) 67 REG32(I3C6_REG0, 0x60) 68 REG32(I3C6_REG1, 0x64) 69 FIELD(I3C6_REG1, I2C_MODE, 0, 1) 70 FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1) 71 FIELD(I3C6_REG1, ACT_MODE, 2, 2) 72 FIELD(I3C6_REG1, PENDING_INT, 4, 4) 73 FIELD(I3C6_REG1, SA, 8, 7) 74 FIELD(I3C6_REG1, SA_EN, 15, 1) 75 FIELD(I3C6_REG1, INST_ID, 16, 4) 76 77 /* I3C Device Registers */ 78 REG32(DEVICE_CTRL, 0x00) 79 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 80 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 81 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 82 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 83 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 84 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 85 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 86 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 87 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 88 REG32(DEVICE_ADDR, 0x04) 89 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 90 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 91 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 92 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 93 REG32(HW_CAPABILITY, 0x08) 94 FIELD(HW_CAPABILITY, ENTDAA, 0, 1) 95 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 96 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 97 REG32(COMMAND_QUEUE_PORT, 0x0c) 98 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 99 /* Transfer command structure */ 100 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 101 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 102 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 103 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 104 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 105 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 106 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 107 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 108 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 109 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 110 /* Transfer argument data structure */ 111 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 112 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 113 /* Short data argument data structure */ 114 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 115 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 116 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 117 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 118 /* Address assignment command structure */ 119 /* 120 * bits 3..21 and 26..31 are the same as the transfer command structure, or 121 * marked as reserved. 122 */ 123 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 124 REG32(RESPONSE_QUEUE_PORT, 0x10) 125 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 126 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 127 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 128 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 129 REG32(RX_TX_DATA_PORT, 0x14) 130 REG32(IBI_QUEUE_STATUS, 0x18) 131 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 132 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 133 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 134 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 135 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 136 REG32(IBI_QUEUE_DATA, 0x18) 137 REG32(QUEUE_THLD_CTRL, 0x1c) 138 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 139 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 140 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 141 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 142 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 143 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 144 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 145 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 146 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 147 REG32(IBI_QUEUE_CTRL, 0x24) 148 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 149 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 150 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 151 REG32(IBI_MR_REQ_REJECT, 0x2c) 152 REG32(IBI_SIR_REQ_REJECT, 0x30) 153 REG32(RESET_CTRL, 0x34) 154 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 155 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 156 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 157 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 158 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 159 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 160 REG32(SLV_EVENT_CTRL, 0x38) 161 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 162 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 163 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 164 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 165 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 166 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 167 REG32(INTR_STATUS, 0x3c) 168 FIELD(INTR_STATUS, TX_THLD, 0, 1) 169 FIELD(INTR_STATUS, RX_THLD, 1, 1) 170 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 171 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 172 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 173 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 174 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 175 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 176 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 177 FIELD(INTR_STATUS, DEFSLV, 10, 1) 178 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 179 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 180 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 181 REG32(INTR_STATUS_EN, 0x40) 182 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 183 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 184 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 185 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 186 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 187 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 188 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 189 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 190 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 191 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 192 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 193 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 194 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 195 REG32(INTR_SIGNAL_EN, 0x44) 196 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 197 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 198 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 199 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 200 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 201 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 202 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 203 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 204 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 205 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 206 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 207 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 208 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 209 REG32(INTR_FORCE, 0x48) 210 FIELD(INTR_FORCE, TX_THLD, 0, 1) 211 FIELD(INTR_FORCE, RX_THLD, 1, 1) 212 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 213 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 214 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 215 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 216 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 217 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 218 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 219 FIELD(INTR_FORCE, DEFSLV, 10, 1) 220 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 221 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 222 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 223 REG32(QUEUE_STATUS_LEVEL, 0x4c) 224 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 225 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 226 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 227 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 228 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 229 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 230 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 231 REG32(PRESENT_STATE, 0x54) 232 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 233 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 234 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 235 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 236 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 237 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 238 REG32(CCC_DEVICE_STATUS, 0x58) 239 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 240 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 241 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 242 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 243 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 244 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 245 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 246 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 247 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 248 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 249 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 250 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 251 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 252 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 253 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 254 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 255 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 256 REG32(SLV_MIPI_PID_VALUE, 0x70) 257 REG32(SLV_PID_VALUE, 0x74) 258 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 259 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 260 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 261 REG32(SLV_CHAR_CTRL, 0x78) 262 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 263 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 264 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 265 REG32(SLV_MAX_LEN, 0x7c) 266 FIELD(SLV_MAX_LEN, MWL, 0, 16) 267 FIELD(SLV_MAX_LEN, MRL, 16, 16) 268 REG32(MAX_READ_TURNAROUND, 0x80) 269 REG32(MAX_DATA_SPEED, 0x84) 270 REG32(SLV_DEBUG_STATUS, 0x88) 271 REG32(SLV_INTR_REQ, 0x8c) 272 FIELD(SLV_INTR_REQ, SIR, 0, 1) 273 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 274 FIELD(SLV_INTR_REQ, MIR, 3, 1) 275 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 276 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 277 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 278 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 279 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 280 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 281 REG32(SCL_I3C_OD_TIMING, 0xb4) 282 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 283 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 284 REG32(SCL_I3C_PP_TIMING, 0xb8) 285 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 286 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 287 REG32(SCL_I2C_FM_TIMING, 0xbc) 288 REG32(SCL_I2C_FMP_TIMING, 0xc0) 289 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 290 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 291 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 292 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 293 REG32(BUS_FREE_TIMING, 0xd4) 294 REG32(BUS_IDLE_TIMING, 0xd8) 295 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 296 REG32(I3C_VER_ID, 0xe0) 297 REG32(I3C_VER_TYPE, 0xe4) 298 REG32(EXTENDED_CAPABILITY, 0xe8) 299 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 300 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 301 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 302 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 303 REG32(SLAVE_CONFIG, 0xec) 304 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 305 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 306 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 307 /* Device characteristic table fields */ 308 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 309 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 310 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 311 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 312 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 313 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 314 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 315 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 316 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 317 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 318 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 319 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 320 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 321 /* Dev addr table fields */ 322 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 323 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 324 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 325 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 326 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 327 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 328 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 329 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 330 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 331 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 332 333 static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_DEVICE_NR_REGS] = { 334 [R_I3C1_REG0] = 0xfc000000, 335 [R_I3C1_REG1] = 0xfff00000, 336 [R_I3C2_REG0] = 0xfc000000, 337 [R_I3C2_REG1] = 0xfff00000, 338 [R_I3C3_REG0] = 0xfc000000, 339 [R_I3C3_REG1] = 0xfff00000, 340 [R_I3C4_REG0] = 0xfc000000, 341 [R_I3C4_REG1] = 0xfff00000, 342 [R_I3C5_REG0] = 0xfc000000, 343 [R_I3C5_REG1] = 0xfff00000, 344 [R_I3C6_REG0] = 0xfc000000, 345 [R_I3C6_REG1] = 0xfff00000, 346 }; 347 348 static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { 349 [R_HW_CAPABILITY] = 0x000e00bf, 350 [R_QUEUE_THLD_CTRL] = 0x01000101, 351 [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, 352 [R_SLV_EVENT_CTRL] = 0x0000000b, 353 [R_QUEUE_STATUS_LEVEL] = 0x00000002, 354 [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, 355 [R_PRESENT_STATE] = 0x00000003, 356 [R_I3C_VER_ID] = 0x3130302a, 357 [R_I3C_VER_TYPE] = 0x6c633033, 358 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 359 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 360 [R_SLV_CHAR_CTRL] = 0x00010000, 361 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 362 [R_SLV_MAX_LEN] = 0x00ff00ff, 363 [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, 364 [R_SCL_I3C_OD_TIMING] = 0x000a0010, 365 [R_SCL_I3C_PP_TIMING] = 0x000a000a, 366 [R_SCL_I2C_FM_TIMING] = 0x00100010, 367 [R_SCL_I2C_FMP_TIMING] = 0x00100010, 368 [R_SCL_EXT_LCNT_TIMING] = 0x20202020, 369 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, 370 [R_BUS_FREE_TIMING] = 0x00200020, 371 [R_BUS_IDLE_TIMING] = 0x00000020, 372 [R_EXTENDED_CAPABILITY] = 0x00000239, 373 [R_SLAVE_CONFIG] = 0x00000023, 374 }; 375 376 static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = { 377 [R_DEVICE_CTRL] = 0x04fffe00, 378 [R_DEVICE_ADDR] = 0x7f807f80, 379 [R_HW_CAPABILITY] = 0xffffffff, 380 [R_IBI_QUEUE_STATUS] = 0xffffffff, 381 [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, 382 [R_IBI_QUEUE_CTRL] = 0xfffffff0, 383 [R_RESET_CTRL] = 0xffffffc0, 384 [R_SLV_EVENT_CTRL] = 0xffffff3f, 385 [R_INTR_STATUS] = 0xffff809f, 386 [R_INTR_STATUS_EN] = 0xffff8080, 387 [R_INTR_SIGNAL_EN] = 0xffff8080, 388 [R_INTR_FORCE] = 0xffff8000, 389 [R_QUEUE_STATUS_LEVEL] = 0xffffffff, 390 [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, 391 [R_PRESENT_STATE] = 0xffffffff, 392 [R_CCC_DEVICE_STATUS] = 0xffffffff, 393 [R_I3C_VER_ID] = 0xffffffff, 394 [R_I3C_VER_TYPE] = 0xffffffff, 395 [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, 396 [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, 397 [R_SLV_PID_VALUE] = 0xffff0fff, 398 [R_SLV_CHAR_CTRL] = 0xffffffff, 399 [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, 400 [R_SLV_MAX_LEN] = 0xffffffff, 401 [R_MAX_READ_TURNAROUND] = 0xffffffff, 402 [R_MAX_DATA_SPEED] = 0xffffffff, 403 [R_SLV_INTR_REQ] = 0xfffffff0, 404 [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, 405 [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, 406 [R_SCL_I3C_OD_TIMING] = 0xff00ff00, 407 [R_SCL_I3C_PP_TIMING] = 0xff00ff00, 408 [R_SCL_I2C_FMP_TIMING] = 0xff000000, 409 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, 410 [R_BUS_IDLE_TIMING] = 0xfff00000, 411 [R_EXTENDED_CAPABILITY] = 0xffffffff, 412 [R_SLAVE_CONFIG] = 0xffffffff, 413 }; 414 415 static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, 416 unsigned size) 417 { 418 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 419 uint32_t addr = offset >> 2; 420 uint64_t value; 421 422 switch (addr) { 423 /* RAZ */ 424 case R_COMMAND_QUEUE_PORT: 425 case R_RESET_CTRL: 426 case R_INTR_FORCE: 427 value = 0; 428 break; 429 default: 430 value = s->regs[addr]; 431 break; 432 } 433 434 trace_aspeed_i3c_device_read(s->id, offset, value); 435 436 return value; 437 } 438 439 static void aspeed_i3c_device_write(void *opaque, hwaddr offset, 440 uint64_t value, unsigned size) 441 { 442 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 443 uint32_t addr = offset >> 2; 444 uint32_t val32 = (uint32_t)value; 445 446 trace_aspeed_i3c_device_write(s->id, offset, value); 447 448 val32 &= ~ast2600_i3c_device_ro[addr]; 449 switch (addr) { 450 case R_HW_CAPABILITY: 451 case R_RESPONSE_QUEUE_PORT: 452 case R_IBI_QUEUE_DATA: 453 case R_QUEUE_STATUS_LEVEL: 454 case R_PRESENT_STATE: 455 case R_CCC_DEVICE_STATUS: 456 case R_DEVICE_ADDR_TABLE_POINTER: 457 case R_VENDOR_SPECIFIC_REG_POINTER: 458 case R_SLV_CHAR_CTRL: 459 case R_SLV_MAX_LEN: 460 case R_MAX_READ_TURNAROUND: 461 case R_I3C_VER_ID: 462 case R_I3C_VER_TYPE: 463 case R_EXTENDED_CAPABILITY: 464 qemu_log_mask(LOG_GUEST_ERROR, 465 "%s: write to readonly register[0x%02" HWADDR_PRIx 466 "] = 0x%08" PRIx64 "\n", 467 __func__, offset, value); 468 break; 469 case R_RX_TX_DATA_PORT: 470 break; 471 case R_RESET_CTRL: 472 break; 473 default: 474 s->regs[addr] = val32; 475 break; 476 } 477 } 478 479 static const VMStateDescription aspeed_i3c_device_vmstate = { 480 .name = TYPE_ASPEED_I3C, 481 .version_id = 1, 482 .minimum_version_id = 1, 483 .fields = (const VMStateField[]){ 484 VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), 485 VMSTATE_END_OF_LIST(), 486 } 487 }; 488 489 static const MemoryRegionOps aspeed_i3c_device_ops = { 490 .read = aspeed_i3c_device_read, 491 .write = aspeed_i3c_device_write, 492 .endianness = DEVICE_LITTLE_ENDIAN, 493 }; 494 495 static void aspeed_i3c_device_reset(DeviceState *dev) 496 { 497 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 498 499 memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); 500 } 501 502 static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) 503 { 504 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 505 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", 506 s->id); 507 508 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 509 510 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, 511 s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); 512 } 513 514 static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) 515 { 516 AspeedI3CState *s = ASPEED_I3C(opaque); 517 uint64_t val = 0; 518 519 val = s->regs[addr >> 2]; 520 521 trace_aspeed_i3c_read(addr, val); 522 523 return val; 524 } 525 526 static void aspeed_i3c_write(void *opaque, 527 hwaddr addr, 528 uint64_t data, 529 unsigned int size) 530 { 531 AspeedI3CState *s = ASPEED_I3C(opaque); 532 533 trace_aspeed_i3c_write(addr, data); 534 535 addr >>= 2; 536 537 data &= ~ast2600_i3c_controller_ro[addr]; 538 /* I3C controller register */ 539 switch (addr) { 540 case R_I3C1_REG1: 541 case R_I3C2_REG1: 542 case R_I3C3_REG1: 543 case R_I3C4_REG1: 544 case R_I3C5_REG1: 545 case R_I3C6_REG1: 546 if (data & R_I3C1_REG1_I2C_MODE_MASK) { 547 qemu_log_mask(LOG_UNIMP, 548 "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx 549 "]=%08" PRIx64 "\n", 550 __func__, addr << 2, data); 551 break; 552 } 553 if (data & R_I3C1_REG1_SA_EN_MASK) { 554 qemu_log_mask(LOG_UNIMP, 555 "%s: Unsupported slave mode [%08" HWADDR_PRIx 556 "]=0x%08" PRIx64 "\n", 557 __func__, addr << 2, data); 558 break; 559 } 560 s->regs[addr] = data; 561 break; 562 default: 563 s->regs[addr] = data; 564 break; 565 } 566 } 567 568 static const MemoryRegionOps aspeed_i3c_ops = { 569 .read = aspeed_i3c_read, 570 .write = aspeed_i3c_write, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 .valid = { 573 .min_access_size = 1, 574 .max_access_size = 4, 575 } 576 }; 577 578 static void aspeed_i3c_reset(DeviceState *dev) 579 { 580 AspeedI3CState *s = ASPEED_I3C(dev); 581 memset(s->regs, 0, sizeof(s->regs)); 582 } 583 584 static void aspeed_i3c_instance_init(Object *obj) 585 { 586 AspeedI3CState *s = ASPEED_I3C(obj); 587 int i; 588 589 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 590 object_initialize_child(obj, "device[*]", &s->devices[i], 591 TYPE_ASPEED_I3C_DEVICE); 592 } 593 } 594 595 static void aspeed_i3c_realize(DeviceState *dev, Error **errp) 596 { 597 int i; 598 AspeedI3CState *s = ASPEED_I3C(dev); 599 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 600 601 memory_region_init(&s->iomem_container, OBJECT(s), 602 TYPE_ASPEED_I3C ".container", 0x8000); 603 604 sysbus_init_mmio(sbd, &s->iomem_container); 605 606 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s, 607 TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2); 608 609 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); 610 611 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 612 Object *i3c_dev = OBJECT(&s->devices[i]); 613 614 if (!object_property_set_uint(i3c_dev, "device-id", i, errp)) { 615 return; 616 } 617 618 if (!sysbus_realize(SYS_BUS_DEVICE(i3c_dev), errp)) { 619 return; 620 } 621 622 /* 623 * Register Address of I3CX Device = 624 * (Base Address of Global Register) + (Offset of I3CX) + Offset 625 * X = 0, 1, 2, 3, 4, 5 626 * Offset of I3C0 = 0x2000 627 * Offset of I3C1 = 0x3000 628 * Offset of I3C2 = 0x4000 629 * Offset of I3C3 = 0x5000 630 * Offset of I3C4 = 0x6000 631 * Offset of I3C5 = 0x7000 632 */ 633 memory_region_add_subregion(&s->iomem_container, 634 0x2000 + i * 0x1000, &s->devices[i].mr); 635 } 636 637 } 638 639 static Property aspeed_i3c_device_properties[] = { 640 DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), 641 DEFINE_PROP_END_OF_LIST(), 642 }; 643 644 static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) 645 { 646 DeviceClass *dc = DEVICE_CLASS(klass); 647 648 dc->desc = "Aspeed I3C Device"; 649 dc->realize = aspeed_i3c_device_realize; 650 device_class_set_legacy_reset(dc, aspeed_i3c_device_reset); 651 device_class_set_props(dc, aspeed_i3c_device_properties); 652 } 653 654 static const TypeInfo aspeed_i3c_device_info = { 655 .name = TYPE_ASPEED_I3C_DEVICE, 656 .parent = TYPE_SYS_BUS_DEVICE, 657 .instance_size = sizeof(AspeedI3CDevice), 658 .class_init = aspeed_i3c_device_class_init, 659 }; 660 661 static const VMStateDescription vmstate_aspeed_i3c = { 662 .name = TYPE_ASPEED_I3C, 663 .version_id = 1, 664 .minimum_version_id = 1, 665 .fields = (const VMStateField[]) { 666 VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), 667 VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, 668 aspeed_i3c_device_vmstate, AspeedI3CDevice), 669 VMSTATE_END_OF_LIST(), 670 } 671 }; 672 673 static void aspeed_i3c_class_init(ObjectClass *klass, void *data) 674 { 675 DeviceClass *dc = DEVICE_CLASS(klass); 676 677 dc->realize = aspeed_i3c_realize; 678 device_class_set_legacy_reset(dc, aspeed_i3c_reset); 679 dc->desc = "Aspeed I3C Controller"; 680 dc->vmsd = &vmstate_aspeed_i3c; 681 } 682 683 static const TypeInfo aspeed_i3c_info = { 684 .name = TYPE_ASPEED_I3C, 685 .parent = TYPE_SYS_BUS_DEVICE, 686 .instance_init = aspeed_i3c_instance_init, 687 .instance_size = sizeof(AspeedI3CState), 688 .class_init = aspeed_i3c_class_init, 689 }; 690 691 static void aspeed_i3c_register_types(void) 692 { 693 type_register_static(&aspeed_i3c_device_info); 694 type_register_static(&aspeed_i3c_info); 695 } 696 697 type_init(aspeed_i3c_register_types); 698