1 /* 2 * ASPEED I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2023 Google LLC 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/log.h" 13 #include "qemu/error-report.h" 14 #include "hw/i3c/aspeed_i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 #include "hw/i3c/i3c.h" 21 #include "hw/irq.h" 22 23 /* I3C Controller Registers */ 24 REG32(I3C1_REG0, 0x10) 25 REG32(I3C1_REG1, 0x14) 26 FIELD(I3C1_REG1, I2C_MODE, 0, 1) 27 FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1) 28 FIELD(I3C1_REG1, ACT_MODE, 2, 2) 29 FIELD(I3C1_REG1, PENDING_INT, 4, 4) 30 FIELD(I3C1_REG1, SA, 8, 7) 31 FIELD(I3C1_REG1, SA_EN, 15, 1) 32 FIELD(I3C1_REG1, INST_ID, 16, 4) 33 REG32(I3C2_REG0, 0x20) 34 REG32(I3C2_REG1, 0x24) 35 FIELD(I3C2_REG1, I2C_MODE, 0, 1) 36 FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1) 37 FIELD(I3C2_REG1, ACT_MODE, 2, 2) 38 FIELD(I3C2_REG1, PENDING_INT, 4, 4) 39 FIELD(I3C2_REG1, SA, 8, 7) 40 FIELD(I3C2_REG1, SA_EN, 15, 1) 41 FIELD(I3C2_REG1, INST_ID, 16, 4) 42 REG32(I3C3_REG0, 0x30) 43 REG32(I3C3_REG1, 0x34) 44 FIELD(I3C3_REG1, I2C_MODE, 0, 1) 45 FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1) 46 FIELD(I3C3_REG1, ACT_MODE, 2, 2) 47 FIELD(I3C3_REG1, PENDING_INT, 4, 4) 48 FIELD(I3C3_REG1, SA, 8, 7) 49 FIELD(I3C3_REG1, SA_EN, 15, 1) 50 FIELD(I3C3_REG1, INST_ID, 16, 4) 51 REG32(I3C4_REG0, 0x40) 52 REG32(I3C4_REG1, 0x44) 53 FIELD(I3C4_REG1, I2C_MODE, 0, 1) 54 FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1) 55 FIELD(I3C4_REG1, ACT_MODE, 2, 2) 56 FIELD(I3C4_REG1, PENDING_INT, 4, 4) 57 FIELD(I3C4_REG1, SA, 8, 7) 58 FIELD(I3C4_REG1, SA_EN, 15, 1) 59 FIELD(I3C4_REG1, INST_ID, 16, 4) 60 REG32(I3C5_REG0, 0x50) 61 REG32(I3C5_REG1, 0x54) 62 FIELD(I3C5_REG1, I2C_MODE, 0, 1) 63 FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1) 64 FIELD(I3C5_REG1, ACT_MODE, 2, 2) 65 FIELD(I3C5_REG1, PENDING_INT, 4, 4) 66 FIELD(I3C5_REG1, SA, 8, 7) 67 FIELD(I3C5_REG1, SA_EN, 15, 1) 68 FIELD(I3C5_REG1, INST_ID, 16, 4) 69 REG32(I3C6_REG0, 0x60) 70 REG32(I3C6_REG1, 0x64) 71 FIELD(I3C6_REG1, I2C_MODE, 0, 1) 72 FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1) 73 FIELD(I3C6_REG1, ACT_MODE, 2, 2) 74 FIELD(I3C6_REG1, PENDING_INT, 4, 4) 75 FIELD(I3C6_REG1, SA, 8, 7) 76 FIELD(I3C6_REG1, SA_EN, 15, 1) 77 FIELD(I3C6_REG1, INST_ID, 16, 4) 78 79 /* I3C Device Registers */ 80 REG32(DEVICE_CTRL, 0x00) 81 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 82 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 83 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 84 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 85 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 86 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 87 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 88 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 89 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 90 REG32(DEVICE_ADDR, 0x04) 91 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 92 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 93 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 94 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 95 REG32(HW_CAPABILITY, 0x08) 96 FIELD(HW_CAPABILITY, ENTDAA, 0, 1) 97 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 98 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 99 REG32(COMMAND_QUEUE_PORT, 0x0c) 100 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 101 /* Transfer command structure */ 102 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 103 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 104 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 105 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 106 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 107 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 108 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 109 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 110 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 111 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 112 /* Transfer argument data structure */ 113 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 114 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 115 /* Short data argument data structure */ 116 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 117 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 118 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 119 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 120 /* Address assignment command structure */ 121 /* 122 * bits 3..21 and 26..31 are the same as the transfer command structure, or 123 * marked as reserved. 124 */ 125 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 126 REG32(RESPONSE_QUEUE_PORT, 0x10) 127 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 128 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 129 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 130 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 131 REG32(RX_TX_DATA_PORT, 0x14) 132 REG32(IBI_QUEUE_STATUS, 0x18) 133 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 134 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 135 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 136 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 137 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 138 REG32(IBI_QUEUE_DATA, 0x18) 139 REG32(QUEUE_THLD_CTRL, 0x1c) 140 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 141 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 142 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 143 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 144 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 145 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 146 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 147 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 148 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 149 REG32(IBI_QUEUE_CTRL, 0x24) 150 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 151 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 152 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 153 REG32(IBI_MR_REQ_REJECT, 0x2c) 154 REG32(IBI_SIR_REQ_REJECT, 0x30) 155 REG32(RESET_CTRL, 0x34) 156 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 157 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 158 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 159 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 160 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 161 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 162 REG32(SLV_EVENT_CTRL, 0x38) 163 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 164 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 165 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 166 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 167 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 168 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 169 REG32(INTR_STATUS, 0x3c) 170 FIELD(INTR_STATUS, TX_THLD, 0, 1) 171 FIELD(INTR_STATUS, RX_THLD, 1, 1) 172 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 173 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 174 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 175 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 176 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 177 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 178 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 179 FIELD(INTR_STATUS, DEFSLV, 10, 1) 180 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 181 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 182 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 183 REG32(INTR_STATUS_EN, 0x40) 184 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 185 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 186 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 187 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 188 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 189 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 190 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 191 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 192 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 193 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 194 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 195 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 196 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 197 REG32(INTR_SIGNAL_EN, 0x44) 198 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 199 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 200 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 201 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 202 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 203 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 204 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 205 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 206 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 207 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 208 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 209 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 210 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 211 REG32(INTR_FORCE, 0x48) 212 FIELD(INTR_FORCE, TX_THLD, 0, 1) 213 FIELD(INTR_FORCE, RX_THLD, 1, 1) 214 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 215 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 216 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 217 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 218 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 219 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 220 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 221 FIELD(INTR_FORCE, DEFSLV, 10, 1) 222 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 223 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 224 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 225 REG32(QUEUE_STATUS_LEVEL, 0x4c) 226 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 227 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 228 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 229 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 230 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 231 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 232 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 233 REG32(PRESENT_STATE, 0x54) 234 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 235 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 236 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 237 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 238 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 239 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 240 REG32(CCC_DEVICE_STATUS, 0x58) 241 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 242 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 243 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 244 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 245 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 246 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 247 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 248 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 249 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 250 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 251 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 252 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 253 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 254 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 255 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 256 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 257 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 258 REG32(SLV_MIPI_PID_VALUE, 0x70) 259 REG32(SLV_PID_VALUE, 0x74) 260 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 261 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 262 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 263 REG32(SLV_CHAR_CTRL, 0x78) 264 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 265 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 266 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 267 REG32(SLV_MAX_LEN, 0x7c) 268 FIELD(SLV_MAX_LEN, MWL, 0, 16) 269 FIELD(SLV_MAX_LEN, MRL, 16, 16) 270 REG32(MAX_READ_TURNAROUND, 0x80) 271 REG32(MAX_DATA_SPEED, 0x84) 272 REG32(SLV_DEBUG_STATUS, 0x88) 273 REG32(SLV_INTR_REQ, 0x8c) 274 FIELD(SLV_INTR_REQ, SIR, 0, 1) 275 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 276 FIELD(SLV_INTR_REQ, MIR, 3, 1) 277 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 278 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 279 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 280 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 281 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 282 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 283 REG32(SCL_I3C_OD_TIMING, 0xb4) 284 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 285 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 286 REG32(SCL_I3C_PP_TIMING, 0xb8) 287 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 288 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 289 REG32(SCL_I2C_FM_TIMING, 0xbc) 290 REG32(SCL_I2C_FMP_TIMING, 0xc0) 291 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 292 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 293 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 294 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 295 REG32(BUS_FREE_TIMING, 0xd4) 296 REG32(BUS_IDLE_TIMING, 0xd8) 297 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 298 REG32(I3C_VER_ID, 0xe0) 299 REG32(I3C_VER_TYPE, 0xe4) 300 REG32(EXTENDED_CAPABILITY, 0xe8) 301 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 302 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 303 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 304 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 305 REG32(SLAVE_CONFIG, 0xec) 306 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 307 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 308 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 309 /* Device characteristic table fields */ 310 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 311 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 312 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 313 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 314 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 315 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 316 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 317 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 318 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 319 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 320 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 321 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 322 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 323 /* Dev addr table fields */ 324 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 325 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 326 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 327 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 328 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 329 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 330 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 331 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 332 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 333 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 334 335 static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_DEVICE_NR_REGS] = { 336 [R_I3C1_REG0] = 0xfc000000, 337 [R_I3C1_REG1] = 0xfff00000, 338 [R_I3C2_REG0] = 0xfc000000, 339 [R_I3C2_REG1] = 0xfff00000, 340 [R_I3C3_REG0] = 0xfc000000, 341 [R_I3C3_REG1] = 0xfff00000, 342 [R_I3C4_REG0] = 0xfc000000, 343 [R_I3C4_REG1] = 0xfff00000, 344 [R_I3C5_REG0] = 0xfc000000, 345 [R_I3C5_REG1] = 0xfff00000, 346 [R_I3C6_REG0] = 0xfc000000, 347 [R_I3C6_REG1] = 0xfff00000, 348 }; 349 350 static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { 351 [R_HW_CAPABILITY] = 0x000e00bf, 352 [R_QUEUE_THLD_CTRL] = 0x01000101, 353 [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, 354 [R_SLV_EVENT_CTRL] = 0x0000000b, 355 [R_QUEUE_STATUS_LEVEL] = 0x00000002, 356 [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, 357 [R_PRESENT_STATE] = 0x00000003, 358 [R_I3C_VER_ID] = 0x3130302a, 359 [R_I3C_VER_TYPE] = 0x6c633033, 360 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 361 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 362 [R_SLV_CHAR_CTRL] = 0x00010000, 363 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 364 [R_SLV_MAX_LEN] = 0x00ff00ff, 365 [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, 366 [R_SCL_I3C_OD_TIMING] = 0x000a0010, 367 [R_SCL_I3C_PP_TIMING] = 0x000a000a, 368 [R_SCL_I2C_FM_TIMING] = 0x00100010, 369 [R_SCL_I2C_FMP_TIMING] = 0x00100010, 370 [R_SCL_EXT_LCNT_TIMING] = 0x20202020, 371 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, 372 [R_BUS_FREE_TIMING] = 0x00200020, 373 [R_BUS_IDLE_TIMING] = 0x00000020, 374 [R_EXTENDED_CAPABILITY] = 0x00000239, 375 [R_SLAVE_CONFIG] = 0x00000023, 376 }; 377 378 static const uint32_t ast2600_i3c_device_ro[ASPEED_I3C_DEVICE_NR_REGS] = { 379 [R_DEVICE_CTRL] = 0x04fffe00, 380 [R_DEVICE_ADDR] = 0x7f807f80, 381 [R_HW_CAPABILITY] = 0xffffffff, 382 [R_IBI_QUEUE_STATUS] = 0xffffffff, 383 [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, 384 [R_IBI_QUEUE_CTRL] = 0xfffffff0, 385 [R_RESET_CTRL] = 0xffffffc0, 386 [R_SLV_EVENT_CTRL] = 0xffffff3f, 387 [R_INTR_STATUS] = 0xffff809f, 388 [R_INTR_STATUS_EN] = 0xffff8080, 389 [R_INTR_SIGNAL_EN] = 0xffff8080, 390 [R_INTR_FORCE] = 0xffff8000, 391 [R_QUEUE_STATUS_LEVEL] = 0xffffffff, 392 [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, 393 [R_PRESENT_STATE] = 0xffffffff, 394 [R_CCC_DEVICE_STATUS] = 0xffffffff, 395 [R_I3C_VER_ID] = 0xffffffff, 396 [R_I3C_VER_TYPE] = 0xffffffff, 397 [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, 398 [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, 399 [R_SLV_PID_VALUE] = 0xffff0fff, 400 [R_SLV_CHAR_CTRL] = 0xffffffff, 401 [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, 402 [R_SLV_MAX_LEN] = 0xffffffff, 403 [R_MAX_READ_TURNAROUND] = 0xffffffff, 404 [R_MAX_DATA_SPEED] = 0xffffffff, 405 [R_SLV_INTR_REQ] = 0xfffffff0, 406 [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, 407 [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, 408 [R_SCL_I3C_OD_TIMING] = 0xff00ff00, 409 [R_SCL_I3C_PP_TIMING] = 0xff00ff00, 410 [R_SCL_I2C_FMP_TIMING] = 0xff000000, 411 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, 412 [R_BUS_IDLE_TIMING] = 0xfff00000, 413 [R_EXTENDED_CAPABILITY] = 0xffffffff, 414 [R_SLAVE_CONFIG] = 0xffffffff, 415 }; 416 417 static void aspeed_i3c_device_update_irq(AspeedI3CDevice *s) 418 { 419 bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); 420 qemu_set_irq(s->irq, level); 421 } 422 423 static uint32_t aspeed_i3c_device_intr_status_r(AspeedI3CDevice *s) 424 { 425 /* Only return the status whose corresponding EN bits are set. */ 426 return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; 427 } 428 429 static void aspeed_i3c_device_intr_status_w(AspeedI3CDevice *s, uint32_t val) 430 { 431 /* INTR_STATUS[13:5] is w1c, other bits are RO. */ 432 val &= 0x3fe0; 433 s->regs[R_INTR_STATUS] &= ~val; 434 435 aspeed_i3c_device_update_irq(s); 436 } 437 438 static void aspeed_i3c_device_intr_status_en_w(AspeedI3CDevice *s, uint32_t val) 439 { 440 s->regs[R_INTR_STATUS_EN] = val; 441 aspeed_i3c_device_update_irq(s); 442 } 443 444 static void aspeed_i3c_device_intr_signal_en_w(AspeedI3CDevice *s, uint32_t val) 445 { 446 s->regs[R_INTR_SIGNAL_EN] = val; 447 aspeed_i3c_device_update_irq(s); 448 } 449 450 static void aspeed_i3c_device_intr_force_w(AspeedI3CDevice *s, uint32_t val) 451 { 452 /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ 453 s->regs[R_INTR_STATUS] = val; 454 aspeed_i3c_device_update_irq(s); 455 } 456 457 static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, 458 unsigned size) 459 { 460 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 461 uint32_t addr = offset >> 2; 462 uint64_t value; 463 464 switch (addr) { 465 /* RAZ */ 466 case R_COMMAND_QUEUE_PORT: 467 case R_RESET_CTRL: 468 case R_INTR_FORCE: 469 value = 0; 470 break; 471 case R_INTR_STATUS: 472 value = aspeed_i3c_device_intr_status_r(s); 473 break; 474 default: 475 value = s->regs[addr]; 476 break; 477 } 478 479 trace_aspeed_i3c_device_read(s->id, offset, value); 480 481 return value; 482 } 483 484 static void aspeed_i3c_device_write(void *opaque, hwaddr offset, 485 uint64_t value, unsigned size) 486 { 487 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); 488 uint32_t addr = offset >> 2; 489 uint32_t val32 = (uint32_t)value; 490 491 trace_aspeed_i3c_device_write(s->id, offset, value); 492 493 val32 &= ~ast2600_i3c_device_ro[addr]; 494 switch (addr) { 495 case R_HW_CAPABILITY: 496 case R_RESPONSE_QUEUE_PORT: 497 case R_IBI_QUEUE_DATA: 498 case R_QUEUE_STATUS_LEVEL: 499 case R_PRESENT_STATE: 500 case R_CCC_DEVICE_STATUS: 501 case R_DEVICE_ADDR_TABLE_POINTER: 502 case R_VENDOR_SPECIFIC_REG_POINTER: 503 case R_SLV_CHAR_CTRL: 504 case R_SLV_MAX_LEN: 505 case R_MAX_READ_TURNAROUND: 506 case R_I3C_VER_ID: 507 case R_I3C_VER_TYPE: 508 case R_EXTENDED_CAPABILITY: 509 qemu_log_mask(LOG_GUEST_ERROR, 510 "%s: write to readonly register[0x%02" HWADDR_PRIx 511 "] = 0x%08" PRIx64 "\n", 512 __func__, offset, value); 513 break; 514 case R_RX_TX_DATA_PORT: 515 break; 516 case R_RESET_CTRL: 517 break; 518 case R_INTR_STATUS: 519 aspeed_i3c_device_intr_status_w(s, val32); 520 break; 521 case R_INTR_STATUS_EN: 522 aspeed_i3c_device_intr_status_en_w(s, val32); 523 break; 524 case R_INTR_SIGNAL_EN: 525 aspeed_i3c_device_intr_signal_en_w(s, val32); 526 break; 527 case R_INTR_FORCE: 528 aspeed_i3c_device_intr_force_w(s, val32); 529 break; 530 default: 531 s->regs[addr] = val32; 532 break; 533 } 534 } 535 536 static const VMStateDescription aspeed_i3c_device_vmstate = { 537 .name = TYPE_ASPEED_I3C, 538 .version_id = 1, 539 .minimum_version_id = 1, 540 .fields = (const VMStateField[]){ 541 VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), 542 VMSTATE_END_OF_LIST(), 543 } 544 }; 545 546 static const MemoryRegionOps aspeed_i3c_device_ops = { 547 .read = aspeed_i3c_device_read, 548 .write = aspeed_i3c_device_write, 549 .endianness = DEVICE_LITTLE_ENDIAN, 550 }; 551 552 static void aspeed_i3c_device_reset(DeviceState *dev) 553 { 554 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 555 556 memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); 557 } 558 559 static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) 560 { 561 AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); 562 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", 563 s->id); 564 565 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 566 567 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, 568 s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); 569 } 570 571 static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) 572 { 573 AspeedI3CState *s = ASPEED_I3C(opaque); 574 uint64_t val = 0; 575 576 val = s->regs[addr >> 2]; 577 578 trace_aspeed_i3c_read(addr, val); 579 580 return val; 581 } 582 583 static void aspeed_i3c_write(void *opaque, 584 hwaddr addr, 585 uint64_t data, 586 unsigned int size) 587 { 588 AspeedI3CState *s = ASPEED_I3C(opaque); 589 590 trace_aspeed_i3c_write(addr, data); 591 592 addr >>= 2; 593 594 data &= ~ast2600_i3c_controller_ro[addr]; 595 /* I3C controller register */ 596 switch (addr) { 597 case R_I3C1_REG1: 598 case R_I3C2_REG1: 599 case R_I3C3_REG1: 600 case R_I3C4_REG1: 601 case R_I3C5_REG1: 602 case R_I3C6_REG1: 603 if (data & R_I3C1_REG1_I2C_MODE_MASK) { 604 qemu_log_mask(LOG_UNIMP, 605 "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx 606 "]=%08" PRIx64 "\n", 607 __func__, addr << 2, data); 608 break; 609 } 610 if (data & R_I3C1_REG1_SA_EN_MASK) { 611 qemu_log_mask(LOG_UNIMP, 612 "%s: Unsupported slave mode [%08" HWADDR_PRIx 613 "]=0x%08" PRIx64 "\n", 614 __func__, addr << 2, data); 615 break; 616 } 617 s->regs[addr] = data; 618 break; 619 default: 620 s->regs[addr] = data; 621 break; 622 } 623 } 624 625 static const MemoryRegionOps aspeed_i3c_ops = { 626 .read = aspeed_i3c_read, 627 .write = aspeed_i3c_write, 628 .endianness = DEVICE_LITTLE_ENDIAN, 629 .valid = { 630 .min_access_size = 1, 631 .max_access_size = 4, 632 } 633 }; 634 635 static void aspeed_i3c_reset(DeviceState *dev) 636 { 637 AspeedI3CState *s = ASPEED_I3C(dev); 638 memset(s->regs, 0, sizeof(s->regs)); 639 } 640 641 static void aspeed_i3c_instance_init(Object *obj) 642 { 643 AspeedI3CState *s = ASPEED_I3C(obj); 644 int i; 645 646 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 647 object_initialize_child(obj, "device[*]", &s->devices[i], 648 TYPE_ASPEED_I3C_DEVICE); 649 } 650 } 651 652 static void aspeed_i3c_realize(DeviceState *dev, Error **errp) 653 { 654 int i; 655 AspeedI3CState *s = ASPEED_I3C(dev); 656 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 657 658 memory_region_init(&s->iomem_container, OBJECT(s), 659 TYPE_ASPEED_I3C ".container", 0x8000); 660 661 sysbus_init_mmio(sbd, &s->iomem_container); 662 663 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s, 664 TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2); 665 666 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); 667 668 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { 669 Object *i3c_dev = OBJECT(&s->devices[i]); 670 671 if (!object_property_set_uint(i3c_dev, "device-id", i, errp)) { 672 return; 673 } 674 675 if (!sysbus_realize(SYS_BUS_DEVICE(i3c_dev), errp)) { 676 return; 677 } 678 679 /* 680 * Register Address of I3CX Device = 681 * (Base Address of Global Register) + (Offset of I3CX) + Offset 682 * X = 0, 1, 2, 3, 4, 5 683 * Offset of I3C0 = 0x2000 684 * Offset of I3C1 = 0x3000 685 * Offset of I3C2 = 0x4000 686 * Offset of I3C3 = 0x5000 687 * Offset of I3C4 = 0x6000 688 * Offset of I3C5 = 0x7000 689 */ 690 memory_region_add_subregion(&s->iomem_container, 691 0x2000 + i * 0x1000, &s->devices[i].mr); 692 } 693 694 } 695 696 static Property aspeed_i3c_device_properties[] = { 697 DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), 698 DEFINE_PROP_END_OF_LIST(), 699 }; 700 701 static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) 702 { 703 DeviceClass *dc = DEVICE_CLASS(klass); 704 705 dc->desc = "Aspeed I3C Device"; 706 dc->realize = aspeed_i3c_device_realize; 707 device_class_set_legacy_reset(dc, aspeed_i3c_device_reset); 708 device_class_set_props(dc, aspeed_i3c_device_properties); 709 } 710 711 static const TypeInfo aspeed_i3c_device_info = { 712 .name = TYPE_ASPEED_I3C_DEVICE, 713 .parent = TYPE_SYS_BUS_DEVICE, 714 .instance_size = sizeof(AspeedI3CDevice), 715 .class_init = aspeed_i3c_device_class_init, 716 }; 717 718 static const VMStateDescription vmstate_aspeed_i3c = { 719 .name = TYPE_ASPEED_I3C, 720 .version_id = 1, 721 .minimum_version_id = 1, 722 .fields = (const VMStateField[]) { 723 VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), 724 VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, 725 aspeed_i3c_device_vmstate, AspeedI3CDevice), 726 VMSTATE_END_OF_LIST(), 727 } 728 }; 729 730 static void aspeed_i3c_class_init(ObjectClass *klass, void *data) 731 { 732 DeviceClass *dc = DEVICE_CLASS(klass); 733 734 dc->realize = aspeed_i3c_realize; 735 device_class_set_legacy_reset(dc, aspeed_i3c_reset); 736 dc->desc = "Aspeed I3C Controller"; 737 dc->vmsd = &vmstate_aspeed_i3c; 738 } 739 740 static const TypeInfo aspeed_i3c_info = { 741 .name = TYPE_ASPEED_I3C, 742 .parent = TYPE_SYS_BUS_DEVICE, 743 .instance_init = aspeed_i3c_instance_init, 744 .instance_size = sizeof(AspeedI3CState), 745 .class_init = aspeed_i3c_class_init, 746 }; 747 748 static void aspeed_i3c_register_types(void) 749 { 750 type_register_static(&aspeed_i3c_device_info); 751 type_register_static(&aspeed_i3c_info); 752 } 753 754 type_init(aspeed_i3c_register_types); 755