1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu/datadir.h" 29 #include "qapi/error.h" 30 #include "qapi/qmp/qerror.h" 31 #include "qapi/qapi-visit-common.h" 32 #include "qapi/clone-visitor.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/whpx.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/replay.h" 39 #include "sysemu/sysemu.h" 40 #include "sysemu/cpu-timers.h" 41 #include "trace.h" 42 43 #include "hw/i386/x86.h" 44 #include "target/i386/cpu.h" 45 #include "hw/i386/topology.h" 46 #include "hw/i386/fw_cfg.h" 47 #include "hw/intc/i8259.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "target/i386/sev.h" 50 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "hw/irq.h" 53 #include "hw/nmi.h" 54 #include "hw/loader.h" 55 #include "multiboot.h" 56 #include "elf.h" 57 #include "standard-headers/asm-x86/bootparam.h" 58 #include CONFIG_DEVICES 59 #include "kvm/kvm_i386.h" 60 61 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 62 static size_t pvh_start_addr; 63 64 inline void init_topo_info(X86CPUTopoInfo *topo_info, 65 const X86MachineState *x86ms) 66 { 67 MachineState *ms = MACHINE(x86ms); 68 69 topo_info->dies_per_pkg = ms->smp.dies; 70 topo_info->cores_per_die = ms->smp.cores; 71 topo_info->threads_per_core = ms->smp.threads; 72 } 73 74 /* 75 * Calculates initial APIC ID for a specific CPU index 76 * 77 * Currently we need to be able to calculate the APIC ID from the CPU index 78 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 79 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 80 * all CPUs up to max_cpus. 81 */ 82 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 83 unsigned int cpu_index) 84 { 85 X86CPUTopoInfo topo_info; 86 87 init_topo_info(&topo_info, x86ms); 88 89 return x86_apicid_from_cpu_idx(&topo_info, cpu_index); 90 } 91 92 93 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 94 { 95 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 96 97 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 98 goto out; 99 } 100 qdev_realize(DEVICE(cpu), NULL, errp); 101 102 out: 103 object_unref(cpu); 104 } 105 106 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 107 { 108 int i; 109 const CPUArchIdList *possible_cpus; 110 MachineState *ms = MACHINE(x86ms); 111 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 112 113 x86_cpu_set_default_version(default_cpu_version); 114 115 /* 116 * Calculates the limit to CPU APIC ID values 117 * 118 * Limit for the APIC ID value, so that all 119 * CPU APIC IDs are < x86ms->apic_id_limit. 120 * 121 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 122 */ 123 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 124 ms->smp.max_cpus - 1) + 1; 125 possible_cpus = mc->possible_cpu_arch_ids(ms); 126 for (i = 0; i < ms->smp.cpus; i++) { 127 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 128 } 129 } 130 131 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 132 { 133 if (cpus_count > 0xff) { 134 /* 135 * If the number of CPUs can't be represented in 8 bits, the 136 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 137 * to make old BIOSes fail more predictably. 138 */ 139 rtc_set_memory(rtc, 0x5f, 0); 140 } else { 141 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 142 } 143 } 144 145 static int x86_apic_cmp(const void *a, const void *b) 146 { 147 CPUArchId *apic_a = (CPUArchId *)a; 148 CPUArchId *apic_b = (CPUArchId *)b; 149 150 return apic_a->arch_id - apic_b->arch_id; 151 } 152 153 /* 154 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 155 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 156 * entry corresponding to CPU's apic_id returns NULL. 157 */ 158 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 159 { 160 CPUArchId apic_id, *found_cpu; 161 162 apic_id.arch_id = id; 163 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 164 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 165 x86_apic_cmp); 166 if (found_cpu && idx) { 167 *idx = found_cpu - ms->possible_cpus->cpus; 168 } 169 return found_cpu; 170 } 171 172 void x86_cpu_plug(HotplugHandler *hotplug_dev, 173 DeviceState *dev, Error **errp) 174 { 175 CPUArchId *found_cpu; 176 Error *local_err = NULL; 177 X86CPU *cpu = X86_CPU(dev); 178 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 179 180 if (x86ms->acpi_dev) { 181 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 182 if (local_err) { 183 goto out; 184 } 185 } 186 187 /* increment the number of CPUs */ 188 x86ms->boot_cpus++; 189 if (x86ms->rtc) { 190 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 191 } 192 if (x86ms->fw_cfg) { 193 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 194 } 195 196 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 197 found_cpu->cpu = OBJECT(dev); 198 out: 199 error_propagate(errp, local_err); 200 } 201 202 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 203 DeviceState *dev, Error **errp) 204 { 205 int idx = -1; 206 X86CPU *cpu = X86_CPU(dev); 207 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 208 209 if (!x86ms->acpi_dev) { 210 error_setg(errp, "CPU hot unplug not supported without ACPI"); 211 return; 212 } 213 214 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 215 assert(idx != -1); 216 if (idx == 0) { 217 error_setg(errp, "Boot CPU is unpluggable"); 218 return; 219 } 220 221 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 222 errp); 223 } 224 225 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 226 DeviceState *dev, Error **errp) 227 { 228 CPUArchId *found_cpu; 229 Error *local_err = NULL; 230 X86CPU *cpu = X86_CPU(dev); 231 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 232 233 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 234 if (local_err) { 235 goto out; 236 } 237 238 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 239 found_cpu->cpu = NULL; 240 qdev_unrealize(dev); 241 242 /* decrement the number of CPUs */ 243 x86ms->boot_cpus--; 244 /* Update the number of CPUs in CMOS */ 245 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 246 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 247 out: 248 error_propagate(errp, local_err); 249 } 250 251 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 252 DeviceState *dev, Error **errp) 253 { 254 int idx; 255 CPUState *cs; 256 CPUArchId *cpu_slot; 257 X86CPUTopoIDs topo_ids; 258 X86CPU *cpu = X86_CPU(dev); 259 CPUX86State *env = &cpu->env; 260 MachineState *ms = MACHINE(hotplug_dev); 261 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 262 unsigned int smp_cores = ms->smp.cores; 263 unsigned int smp_threads = ms->smp.threads; 264 X86CPUTopoInfo topo_info; 265 266 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 267 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 268 ms->cpu_type); 269 return; 270 } 271 272 if (x86ms->acpi_dev) { 273 Error *local_err = NULL; 274 275 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 276 &local_err); 277 if (local_err) { 278 error_propagate(errp, local_err); 279 return; 280 } 281 } 282 283 init_topo_info(&topo_info, x86ms); 284 285 env->nr_dies = ms->smp.dies; 286 287 /* 288 * If APIC ID is not set, 289 * set it based on socket/die/core/thread properties. 290 */ 291 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 292 int max_socket = (ms->smp.max_cpus - 1) / 293 smp_threads / smp_cores / ms->smp.dies; 294 295 /* 296 * die-id was optional in QEMU 4.0 and older, so keep it optional 297 * if there's only one die per socket. 298 */ 299 if (cpu->die_id < 0 && ms->smp.dies == 1) { 300 cpu->die_id = 0; 301 } 302 303 if (cpu->socket_id < 0) { 304 error_setg(errp, "CPU socket-id is not set"); 305 return; 306 } else if (cpu->socket_id > max_socket) { 307 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 308 cpu->socket_id, max_socket); 309 return; 310 } 311 if (cpu->die_id < 0) { 312 error_setg(errp, "CPU die-id is not set"); 313 return; 314 } else if (cpu->die_id > ms->smp.dies - 1) { 315 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 316 cpu->die_id, ms->smp.dies - 1); 317 return; 318 } 319 if (cpu->core_id < 0) { 320 error_setg(errp, "CPU core-id is not set"); 321 return; 322 } else if (cpu->core_id > (smp_cores - 1)) { 323 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 324 cpu->core_id, smp_cores - 1); 325 return; 326 } 327 if (cpu->thread_id < 0) { 328 error_setg(errp, "CPU thread-id is not set"); 329 return; 330 } else if (cpu->thread_id > (smp_threads - 1)) { 331 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 332 cpu->thread_id, smp_threads - 1); 333 return; 334 } 335 336 topo_ids.pkg_id = cpu->socket_id; 337 topo_ids.die_id = cpu->die_id; 338 topo_ids.core_id = cpu->core_id; 339 topo_ids.smt_id = cpu->thread_id; 340 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 341 } 342 343 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 344 if (!cpu_slot) { 345 MachineState *ms = MACHINE(x86ms); 346 347 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 348 error_setg(errp, 349 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 350 " APIC ID %" PRIu32 ", valid index range 0:%d", 351 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 352 cpu->apic_id, ms->possible_cpus->len - 1); 353 return; 354 } 355 356 if (cpu_slot->cpu) { 357 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 358 idx, cpu->apic_id); 359 return; 360 } 361 362 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 363 * so that machine_query_hotpluggable_cpus would show correct values 364 */ 365 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 366 * once -smp refactoring is complete and there will be CPU private 367 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 368 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 369 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 370 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 371 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 372 topo_ids.pkg_id); 373 return; 374 } 375 cpu->socket_id = topo_ids.pkg_id; 376 377 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 378 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 379 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 380 return; 381 } 382 cpu->die_id = topo_ids.die_id; 383 384 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 385 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 386 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 387 topo_ids.core_id); 388 return; 389 } 390 cpu->core_id = topo_ids.core_id; 391 392 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 393 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 394 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 395 topo_ids.smt_id); 396 return; 397 } 398 cpu->thread_id = topo_ids.smt_id; 399 400 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 401 !kvm_hv_vpindex_settable()) { 402 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 403 return; 404 } 405 406 cs = CPU(cpu); 407 cs->cpu_index = idx; 408 409 numa_cpu_pre_plug(cpu_slot, dev, errp); 410 } 411 412 CpuInstanceProperties 413 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 414 { 415 MachineClass *mc = MACHINE_GET_CLASS(ms); 416 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 417 418 assert(cpu_index < possible_cpus->len); 419 return possible_cpus->cpus[cpu_index].props; 420 } 421 422 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 423 { 424 X86CPUTopoIDs topo_ids; 425 X86MachineState *x86ms = X86_MACHINE(ms); 426 X86CPUTopoInfo topo_info; 427 428 init_topo_info(&topo_info, x86ms); 429 430 assert(idx < ms->possible_cpus->len); 431 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 432 &topo_info, &topo_ids); 433 return topo_ids.pkg_id % ms->numa_state->num_nodes; 434 } 435 436 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 437 { 438 X86MachineState *x86ms = X86_MACHINE(ms); 439 unsigned int max_cpus = ms->smp.max_cpus; 440 X86CPUTopoInfo topo_info; 441 int i; 442 443 if (ms->possible_cpus) { 444 /* 445 * make sure that max_cpus hasn't changed since the first use, i.e. 446 * -smp hasn't been parsed after it 447 */ 448 assert(ms->possible_cpus->len == max_cpus); 449 return ms->possible_cpus; 450 } 451 452 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 453 sizeof(CPUArchId) * max_cpus); 454 ms->possible_cpus->len = max_cpus; 455 456 init_topo_info(&topo_info, x86ms); 457 458 for (i = 0; i < ms->possible_cpus->len; i++) { 459 X86CPUTopoIDs topo_ids; 460 461 ms->possible_cpus->cpus[i].type = ms->cpu_type; 462 ms->possible_cpus->cpus[i].vcpus_count = 1; 463 ms->possible_cpus->cpus[i].arch_id = 464 x86_cpu_apic_id_from_index(x86ms, i); 465 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 466 &topo_info, &topo_ids); 467 ms->possible_cpus->cpus[i].props.has_socket_id = true; 468 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 469 if (ms->smp.dies > 1) { 470 ms->possible_cpus->cpus[i].props.has_die_id = true; 471 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 472 } 473 ms->possible_cpus->cpus[i].props.has_core_id = true; 474 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 475 ms->possible_cpus->cpus[i].props.has_thread_id = true; 476 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 477 } 478 return ms->possible_cpus; 479 } 480 481 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 482 { 483 /* cpu index isn't used */ 484 CPUState *cs; 485 486 CPU_FOREACH(cs) { 487 X86CPU *cpu = X86_CPU(cs); 488 489 if (!cpu->apic_state) { 490 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 491 } else { 492 apic_deliver_nmi(cpu->apic_state); 493 } 494 } 495 } 496 497 static long get_file_size(FILE *f) 498 { 499 long where, size; 500 501 /* XXX: on Unix systems, using fstat() probably makes more sense */ 502 503 where = ftell(f); 504 fseek(f, 0, SEEK_END); 505 size = ftell(f); 506 fseek(f, where, SEEK_SET); 507 508 return size; 509 } 510 511 /* TSC handling */ 512 uint64_t cpu_get_tsc(CPUX86State *env) 513 { 514 return cpus_get_elapsed_ticks(); 515 } 516 517 /* IRQ handling */ 518 static void pic_irq_request(void *opaque, int irq, int level) 519 { 520 CPUState *cs = first_cpu; 521 X86CPU *cpu = X86_CPU(cs); 522 523 trace_x86_pic_interrupt(irq, level); 524 if (cpu->apic_state && !kvm_irqchip_in_kernel() && 525 !whpx_apic_in_platform()) { 526 CPU_FOREACH(cs) { 527 cpu = X86_CPU(cs); 528 if (apic_accept_pic_intr(cpu->apic_state)) { 529 apic_deliver_pic_intr(cpu->apic_state, level); 530 } 531 } 532 } else { 533 if (level) { 534 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 535 } else { 536 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 537 } 538 } 539 } 540 541 qemu_irq x86_allocate_cpu_irq(void) 542 { 543 return qemu_allocate_irq(pic_irq_request, NULL, 0); 544 } 545 546 int cpu_get_pic_interrupt(CPUX86State *env) 547 { 548 X86CPU *cpu = env_archcpu(env); 549 int intno; 550 551 if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { 552 intno = apic_get_interrupt(cpu->apic_state); 553 if (intno >= 0) { 554 return intno; 555 } 556 /* read the irq from the PIC */ 557 if (!apic_accept_pic_intr(cpu->apic_state)) { 558 return -1; 559 } 560 } 561 562 intno = pic_read_irq(isa_pic); 563 return intno; 564 } 565 566 DeviceState *cpu_get_current_apic(void) 567 { 568 if (current_cpu) { 569 X86CPU *cpu = X86_CPU(current_cpu); 570 return cpu->apic_state; 571 } else { 572 return NULL; 573 } 574 } 575 576 void gsi_handler(void *opaque, int n, int level) 577 { 578 GSIState *s = opaque; 579 580 trace_x86_gsi_interrupt(n, level); 581 switch (n) { 582 case 0 ... ISA_NUM_IRQS - 1: 583 if (s->i8259_irq[n]) { 584 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 585 qemu_set_irq(s->i8259_irq[n], level); 586 } 587 /* fall through */ 588 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 589 qemu_set_irq(s->ioapic_irq[n], level); 590 break; 591 case IO_APIC_SECONDARY_IRQBASE 592 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 593 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 594 break; 595 } 596 } 597 598 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 599 { 600 DeviceState *dev; 601 SysBusDevice *d; 602 unsigned int i; 603 604 assert(parent_name); 605 if (kvm_ioapic_in_kernel()) { 606 dev = qdev_new(TYPE_KVM_IOAPIC); 607 } else { 608 dev = qdev_new(TYPE_IOAPIC); 609 } 610 object_property_add_child(object_resolve_path(parent_name, NULL), 611 "ioapic", OBJECT(dev)); 612 d = SYS_BUS_DEVICE(dev); 613 sysbus_realize_and_unref(d, &error_fatal); 614 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 615 616 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 617 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 618 } 619 } 620 621 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 622 { 623 DeviceState *dev; 624 SysBusDevice *d; 625 unsigned int i; 626 627 dev = qdev_new(TYPE_IOAPIC); 628 d = SYS_BUS_DEVICE(dev); 629 sysbus_realize_and_unref(d, &error_fatal); 630 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 631 632 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 633 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 634 } 635 return dev; 636 } 637 638 struct setup_data { 639 uint64_t next; 640 uint32_t type; 641 uint32_t len; 642 uint8_t data[]; 643 } __attribute__((packed)); 644 645 646 /* 647 * The entry point into the kernel for PVH boot is different from 648 * the native entry point. The PVH entry is defined by the x86/HVM 649 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 650 * 651 * This function is passed to load_elf() when it is called from 652 * load_elfboot() which then additionally checks for an ELF Note of 653 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 654 * parse the PVH entry address from the ELF Note. 655 * 656 * Due to trickery in elf_opts.h, load_elf() is actually available as 657 * load_elf32() or load_elf64() and this routine needs to be able 658 * to deal with being called as 32 or 64 bit. 659 * 660 * The address of the PVH entry point is saved to the 'pvh_start_addr' 661 * global variable. (although the entry point is 32-bit, the kernel 662 * binary can be either 32-bit or 64-bit). 663 */ 664 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 665 { 666 size_t *elf_note_data_addr; 667 668 /* Check if ELF Note header passed in is valid */ 669 if (arg1 == NULL) { 670 return 0; 671 } 672 673 if (is64) { 674 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 675 uint64_t nhdr_size64 = sizeof(struct elf64_note); 676 uint64_t phdr_align = *(uint64_t *)arg2; 677 uint64_t nhdr_namesz = nhdr64->n_namesz; 678 679 elf_note_data_addr = 680 ((void *)nhdr64) + nhdr_size64 + 681 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 682 683 pvh_start_addr = *elf_note_data_addr; 684 } else { 685 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 686 uint32_t nhdr_size32 = sizeof(struct elf32_note); 687 uint32_t phdr_align = *(uint32_t *)arg2; 688 uint32_t nhdr_namesz = nhdr32->n_namesz; 689 690 elf_note_data_addr = 691 ((void *)nhdr32) + nhdr_size32 + 692 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 693 694 pvh_start_addr = *(uint32_t *)elf_note_data_addr; 695 } 696 697 return pvh_start_addr; 698 } 699 700 static bool load_elfboot(const char *kernel_filename, 701 int kernel_file_size, 702 uint8_t *header, 703 size_t pvh_xen_start_addr, 704 FWCfgState *fw_cfg) 705 { 706 uint32_t flags = 0; 707 uint32_t mh_load_addr = 0; 708 uint32_t elf_kernel_size = 0; 709 uint64_t elf_entry; 710 uint64_t elf_low, elf_high; 711 int kernel_size; 712 713 if (ldl_p(header) != 0x464c457f) { 714 return false; /* no elfboot */ 715 } 716 717 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 718 flags = elf_is64 ? 719 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 720 721 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 722 error_report("elfboot unsupported flags = %x", flags); 723 exit(1); 724 } 725 726 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 727 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 728 NULL, &elf_note_type, &elf_entry, 729 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 730 0, 0); 731 732 if (kernel_size < 0) { 733 error_report("Error while loading elf kernel"); 734 exit(1); 735 } 736 mh_load_addr = elf_low; 737 elf_kernel_size = elf_high - elf_low; 738 739 if (pvh_start_addr == 0) { 740 error_report("Error loading uncompressed kernel without PVH ELF Note"); 741 exit(1); 742 } 743 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 744 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 745 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 746 747 return true; 748 } 749 750 void x86_load_linux(X86MachineState *x86ms, 751 FWCfgState *fw_cfg, 752 int acpi_data_size, 753 bool pvh_enabled) 754 { 755 bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; 756 uint16_t protocol; 757 int setup_size, kernel_size, cmdline_size; 758 int dtb_size, setup_data_offset; 759 uint32_t initrd_max; 760 uint8_t header[8192], *setup, *kernel; 761 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 762 FILE *f; 763 char *vmode; 764 MachineState *machine = MACHINE(x86ms); 765 struct setup_data *setup_data; 766 const char *kernel_filename = machine->kernel_filename; 767 const char *initrd_filename = machine->initrd_filename; 768 const char *dtb_filename = machine->dtb; 769 const char *kernel_cmdline = machine->kernel_cmdline; 770 SevKernelLoaderContext sev_load_ctx = {}; 771 772 /* Align to 16 bytes as a paranoia measure */ 773 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; 774 775 /* load the kernel header */ 776 f = fopen(kernel_filename, "rb"); 777 if (!f) { 778 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 779 kernel_filename, strerror(errno)); 780 exit(1); 781 } 782 783 kernel_size = get_file_size(f); 784 if (!kernel_size || 785 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 786 MIN(ARRAY_SIZE(header), kernel_size)) { 787 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 788 kernel_filename, strerror(errno)); 789 exit(1); 790 } 791 792 /* kernel protocol version */ 793 if (ldl_p(header + 0x202) == 0x53726448) { 794 protocol = lduw_p(header + 0x206); 795 } else { 796 /* 797 * This could be a multiboot kernel. If it is, let's stop treating it 798 * like a Linux kernel. 799 * Note: some multiboot images could be in the ELF format (the same of 800 * PVH), so we try multiboot first since we check the multiboot magic 801 * header before to load it. 802 */ 803 if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, 804 kernel_cmdline, kernel_size, header)) { 805 return; 806 } 807 /* 808 * Check if the file is an uncompressed kernel file (ELF) and load it, 809 * saving the PVH entry point used by the x86/HVM direct boot ABI. 810 * If load_elfboot() is successful, populate the fw_cfg info. 811 */ 812 if (pvh_enabled && 813 load_elfboot(kernel_filename, kernel_size, 814 header, pvh_start_addr, fw_cfg)) { 815 fclose(f); 816 817 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 818 strlen(kernel_cmdline) + 1); 819 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 820 821 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 822 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 823 header, sizeof(header)); 824 825 /* load initrd */ 826 if (initrd_filename) { 827 GMappedFile *mapped_file; 828 gsize initrd_size; 829 gchar *initrd_data; 830 GError *gerr = NULL; 831 832 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 833 if (!mapped_file) { 834 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 835 initrd_filename, gerr->message); 836 exit(1); 837 } 838 x86ms->initrd_mapped_file = mapped_file; 839 840 initrd_data = g_mapped_file_get_contents(mapped_file); 841 initrd_size = g_mapped_file_get_length(mapped_file); 842 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 843 if (initrd_size >= initrd_max) { 844 fprintf(stderr, "qemu: initrd is too large, cannot support." 845 "(max: %"PRIu32", need %"PRId64")\n", 846 initrd_max, (uint64_t)initrd_size); 847 exit(1); 848 } 849 850 initrd_addr = (initrd_max - initrd_size) & ~4095; 851 852 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 853 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 854 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 855 initrd_size); 856 } 857 858 option_rom[nb_option_roms].bootindex = 0; 859 option_rom[nb_option_roms].name = "pvh.bin"; 860 nb_option_roms++; 861 862 return; 863 } 864 protocol = 0; 865 } 866 867 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 868 /* Low kernel */ 869 real_addr = 0x90000; 870 cmdline_addr = 0x9a000 - cmdline_size; 871 prot_addr = 0x10000; 872 } else if (protocol < 0x202) { 873 /* High but ancient kernel */ 874 real_addr = 0x90000; 875 cmdline_addr = 0x9a000 - cmdline_size; 876 prot_addr = 0x100000; 877 } else { 878 /* High and recent kernel */ 879 real_addr = 0x10000; 880 cmdline_addr = 0x20000; 881 prot_addr = 0x100000; 882 } 883 884 /* highest address for loading the initrd */ 885 if (protocol >= 0x20c && 886 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 887 /* 888 * Linux has supported initrd up to 4 GB for a very long time (2007, 889 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 890 * though it only sets initrd_max to 2 GB to "work around bootloader 891 * bugs". Luckily, QEMU firmware(which does something like bootloader) 892 * has supported this. 893 * 894 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 895 * be loaded into any address. 896 * 897 * In addition, initrd_max is uint32_t simply because QEMU doesn't 898 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 899 * field). 900 * 901 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 902 */ 903 initrd_max = UINT32_MAX; 904 } else if (protocol >= 0x203) { 905 initrd_max = ldl_p(header + 0x22c); 906 } else { 907 initrd_max = 0x37ffffff; 908 } 909 910 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 911 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 912 } 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); 916 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 917 sev_load_ctx.cmdline_data = (char *)kernel_cmdline; 918 sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; 919 920 if (protocol >= 0x202) { 921 stl_p(header + 0x228, cmdline_addr); 922 } else { 923 stw_p(header + 0x20, 0xA33F); 924 stw_p(header + 0x22, cmdline_addr - real_addr); 925 } 926 927 /* handle vga= parameter */ 928 vmode = strstr(kernel_cmdline, "vga="); 929 if (vmode) { 930 unsigned int video_mode; 931 const char *end; 932 int ret; 933 /* skip "vga=" */ 934 vmode += 4; 935 if (!strncmp(vmode, "normal", 6)) { 936 video_mode = 0xffff; 937 } else if (!strncmp(vmode, "ext", 3)) { 938 video_mode = 0xfffe; 939 } else if (!strncmp(vmode, "ask", 3)) { 940 video_mode = 0xfffd; 941 } else { 942 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 943 if (ret != 0 || (*end && *end != ' ')) { 944 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 945 exit(1); 946 } 947 } 948 stw_p(header + 0x1fa, video_mode); 949 } 950 951 /* loader type */ 952 /* 953 * High nybble = B reserved for QEMU; low nybble is revision number. 954 * If this code is substantially changed, you may want to consider 955 * incrementing the revision. 956 */ 957 if (protocol >= 0x200) { 958 header[0x210] = 0xB0; 959 } 960 /* heap */ 961 if (protocol >= 0x201) { 962 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 963 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 964 } 965 966 /* load initrd */ 967 if (initrd_filename) { 968 GMappedFile *mapped_file; 969 gsize initrd_size; 970 gchar *initrd_data; 971 GError *gerr = NULL; 972 973 if (protocol < 0x200) { 974 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 975 exit(1); 976 } 977 978 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 979 if (!mapped_file) { 980 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 981 initrd_filename, gerr->message); 982 exit(1); 983 } 984 x86ms->initrd_mapped_file = mapped_file; 985 986 initrd_data = g_mapped_file_get_contents(mapped_file); 987 initrd_size = g_mapped_file_get_length(mapped_file); 988 if (initrd_size >= initrd_max) { 989 fprintf(stderr, "qemu: initrd is too large, cannot support." 990 "(max: %"PRIu32", need %"PRId64")\n", 991 initrd_max, (uint64_t)initrd_size); 992 exit(1); 993 } 994 995 initrd_addr = (initrd_max - initrd_size) & ~4095; 996 997 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 998 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 999 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1000 sev_load_ctx.initrd_data = initrd_data; 1001 sev_load_ctx.initrd_size = initrd_size; 1002 1003 stl_p(header + 0x218, initrd_addr); 1004 stl_p(header + 0x21c, initrd_size); 1005 } 1006 1007 /* load kernel and setup */ 1008 setup_size = header[0x1f1]; 1009 if (setup_size == 0) { 1010 setup_size = 4; 1011 } 1012 setup_size = (setup_size + 1) * 512; 1013 if (setup_size > kernel_size) { 1014 fprintf(stderr, "qemu: invalid kernel header\n"); 1015 exit(1); 1016 } 1017 kernel_size -= setup_size; 1018 1019 setup = g_malloc(setup_size); 1020 kernel = g_malloc(kernel_size); 1021 fseek(f, 0, SEEK_SET); 1022 if (fread(setup, 1, setup_size, f) != setup_size) { 1023 fprintf(stderr, "fread() failed\n"); 1024 exit(1); 1025 } 1026 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1027 fprintf(stderr, "fread() failed\n"); 1028 exit(1); 1029 } 1030 fclose(f); 1031 1032 /* append dtb to kernel */ 1033 if (dtb_filename) { 1034 if (protocol < 0x209) { 1035 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1036 exit(1); 1037 } 1038 1039 dtb_size = get_image_size(dtb_filename); 1040 if (dtb_size <= 0) { 1041 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1042 dtb_filename, strerror(errno)); 1043 exit(1); 1044 } 1045 1046 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1047 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1048 kernel = g_realloc(kernel, kernel_size); 1049 1050 stq_p(header + 0x250, prot_addr + setup_data_offset); 1051 1052 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1053 setup_data->next = 0; 1054 setup_data->type = cpu_to_le32(SETUP_DTB); 1055 setup_data->len = cpu_to_le32(dtb_size); 1056 1057 load_image_size(dtb_filename, setup_data->data, dtb_size); 1058 } 1059 1060 /* 1061 * If we're starting an encrypted VM, it will be OVMF based, which uses the 1062 * efi stub for booting and doesn't require any values to be placed in the 1063 * kernel header. We therefore don't update the header so the hash of the 1064 * kernel on the other side of the fw_cfg interface matches the hash of the 1065 * file the user passed in. 1066 */ 1067 if (!sev_enabled()) { 1068 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1069 } 1070 1071 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1072 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1073 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1074 sev_load_ctx.kernel_data = (char *)kernel; 1075 sev_load_ctx.kernel_size = kernel_size; 1076 1077 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1078 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1079 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1080 sev_load_ctx.setup_data = (char *)setup; 1081 sev_load_ctx.setup_size = setup_size; 1082 1083 if (sev_enabled()) { 1084 sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); 1085 } 1086 1087 option_rom[nb_option_roms].bootindex = 0; 1088 option_rom[nb_option_roms].name = "linuxboot.bin"; 1089 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1090 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1091 } 1092 nb_option_roms++; 1093 } 1094 1095 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 1096 MemoryRegion *rom_memory, bool isapc_ram_fw) 1097 { 1098 const char *bios_name; 1099 char *filename; 1100 MemoryRegion *bios, *isa_bios; 1101 int bios_size, isa_bios_size; 1102 int ret; 1103 1104 /* BIOS load */ 1105 bios_name = ms->firmware ?: default_firmware; 1106 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1107 if (filename) { 1108 bios_size = get_image_size(filename); 1109 } else { 1110 bios_size = -1; 1111 } 1112 if (bios_size <= 0 || 1113 (bios_size % 65536) != 0) { 1114 goto bios_error; 1115 } 1116 bios = g_malloc(sizeof(*bios)); 1117 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1118 if (!isapc_ram_fw) { 1119 memory_region_set_readonly(bios, true); 1120 } 1121 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1122 if (ret != 0) { 1123 bios_error: 1124 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1125 exit(1); 1126 } 1127 g_free(filename); 1128 1129 /* map the last 128KB of the BIOS in ISA space */ 1130 isa_bios_size = MIN(bios_size, 128 * KiB); 1131 isa_bios = g_malloc(sizeof(*isa_bios)); 1132 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1133 bios_size - isa_bios_size, isa_bios_size); 1134 memory_region_add_subregion_overlap(rom_memory, 1135 0x100000 - isa_bios_size, 1136 isa_bios, 1137 1); 1138 if (!isapc_ram_fw) { 1139 memory_region_set_readonly(isa_bios, true); 1140 } 1141 1142 /* map all the bios at the top of memory */ 1143 memory_region_add_subregion(rom_memory, 1144 (uint32_t)(-bios_size), 1145 bios); 1146 } 1147 1148 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1149 { 1150 bool smm_available = false; 1151 1152 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1153 return false; 1154 } 1155 1156 if (tcg_enabled() || qtest_enabled()) { 1157 smm_available = true; 1158 } else if (kvm_enabled()) { 1159 smm_available = kvm_has_smm(); 1160 } 1161 1162 if (smm_available) { 1163 return true; 1164 } 1165 1166 if (x86ms->smm == ON_OFF_AUTO_ON) { 1167 error_report("System Management Mode not supported by this hypervisor."); 1168 exit(1); 1169 } 1170 return false; 1171 } 1172 1173 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1174 void *opaque, Error **errp) 1175 { 1176 X86MachineState *x86ms = X86_MACHINE(obj); 1177 OnOffAuto smm = x86ms->smm; 1178 1179 visit_type_OnOffAuto(v, name, &smm, errp); 1180 } 1181 1182 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1183 void *opaque, Error **errp) 1184 { 1185 X86MachineState *x86ms = X86_MACHINE(obj); 1186 1187 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1188 } 1189 1190 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1191 { 1192 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1193 return false; 1194 } 1195 return true; 1196 } 1197 1198 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1199 void *opaque, Error **errp) 1200 { 1201 X86MachineState *x86ms = X86_MACHINE(obj); 1202 OnOffAuto acpi = x86ms->acpi; 1203 1204 visit_type_OnOffAuto(v, name, &acpi, errp); 1205 } 1206 1207 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1208 void *opaque, Error **errp) 1209 { 1210 X86MachineState *x86ms = X86_MACHINE(obj); 1211 1212 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1213 } 1214 1215 static char *x86_machine_get_oem_id(Object *obj, Error **errp) 1216 { 1217 X86MachineState *x86ms = X86_MACHINE(obj); 1218 1219 return g_strdup(x86ms->oem_id); 1220 } 1221 1222 static void x86_machine_set_oem_id(Object *obj, const char *value, Error **errp) 1223 { 1224 X86MachineState *x86ms = X86_MACHINE(obj); 1225 size_t len = strlen(value); 1226 1227 if (len > 6) { 1228 error_setg(errp, 1229 "User specified "X86_MACHINE_OEM_ID" value is bigger than " 1230 "6 bytes in size"); 1231 return; 1232 } 1233 1234 strncpy(x86ms->oem_id, value, 6); 1235 } 1236 1237 static char *x86_machine_get_oem_table_id(Object *obj, Error **errp) 1238 { 1239 X86MachineState *x86ms = X86_MACHINE(obj); 1240 1241 return g_strdup(x86ms->oem_table_id); 1242 } 1243 1244 static void x86_machine_set_oem_table_id(Object *obj, const char *value, 1245 Error **errp) 1246 { 1247 X86MachineState *x86ms = X86_MACHINE(obj); 1248 size_t len = strlen(value); 1249 1250 if (len > 8) { 1251 error_setg(errp, 1252 "User specified "X86_MACHINE_OEM_TABLE_ID 1253 " value is bigger than " 1254 "8 bytes in size"); 1255 return; 1256 } 1257 strncpy(x86ms->oem_table_id, value, 8); 1258 } 1259 1260 static void x86_machine_get_bus_lock_ratelimit(Object *obj, Visitor *v, 1261 const char *name, void *opaque, Error **errp) 1262 { 1263 X86MachineState *x86ms = X86_MACHINE(obj); 1264 uint64_t bus_lock_ratelimit = x86ms->bus_lock_ratelimit; 1265 1266 visit_type_uint64(v, name, &bus_lock_ratelimit, errp); 1267 } 1268 1269 static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, 1270 const char *name, void *opaque, Error **errp) 1271 { 1272 X86MachineState *x86ms = X86_MACHINE(obj); 1273 1274 visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); 1275 } 1276 1277 static void machine_get_sgx_epc(Object *obj, Visitor *v, const char *name, 1278 void *opaque, Error **errp) 1279 { 1280 X86MachineState *x86ms = X86_MACHINE(obj); 1281 SgxEPCList *list = x86ms->sgx_epc_list; 1282 1283 visit_type_SgxEPCList(v, name, &list, errp); 1284 } 1285 1286 static void machine_set_sgx_epc(Object *obj, Visitor *v, const char *name, 1287 void *opaque, Error **errp) 1288 { 1289 X86MachineState *x86ms = X86_MACHINE(obj); 1290 SgxEPCList *list; 1291 1292 list = x86ms->sgx_epc_list; 1293 visit_type_SgxEPCList(v, name, &x86ms->sgx_epc_list, errp); 1294 1295 qapi_free_SgxEPCList(list); 1296 } 1297 1298 static void x86_machine_initfn(Object *obj) 1299 { 1300 X86MachineState *x86ms = X86_MACHINE(obj); 1301 1302 x86ms->smm = ON_OFF_AUTO_AUTO; 1303 x86ms->acpi = ON_OFF_AUTO_AUTO; 1304 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1305 x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1306 x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1307 x86ms->bus_lock_ratelimit = 0; 1308 } 1309 1310 static void x86_machine_class_init(ObjectClass *oc, void *data) 1311 { 1312 MachineClass *mc = MACHINE_CLASS(oc); 1313 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1314 NMIClass *nc = NMI_CLASS(oc); 1315 1316 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1317 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1318 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1319 x86mc->save_tsc_khz = true; 1320 x86mc->fwcfg_dma_enabled = true; 1321 nc->nmi_monitor_handler = x86_nmi; 1322 1323 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1324 x86_machine_get_smm, x86_machine_set_smm, 1325 NULL, NULL); 1326 object_class_property_set_description(oc, X86_MACHINE_SMM, 1327 "Enable SMM"); 1328 1329 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1330 x86_machine_get_acpi, x86_machine_set_acpi, 1331 NULL, NULL); 1332 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1333 "Enable ACPI"); 1334 1335 object_class_property_add_str(oc, X86_MACHINE_OEM_ID, 1336 x86_machine_get_oem_id, 1337 x86_machine_set_oem_id); 1338 object_class_property_set_description(oc, X86_MACHINE_OEM_ID, 1339 "Override the default value of field OEMID " 1340 "in ACPI table header." 1341 "The string may be up to 6 bytes in size"); 1342 1343 1344 object_class_property_add_str(oc, X86_MACHINE_OEM_TABLE_ID, 1345 x86_machine_get_oem_table_id, 1346 x86_machine_set_oem_table_id); 1347 object_class_property_set_description(oc, X86_MACHINE_OEM_TABLE_ID, 1348 "Override the default value of field OEM Table ID " 1349 "in ACPI table header." 1350 "The string may be up to 8 bytes in size"); 1351 1352 object_class_property_add(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, "uint64_t", 1353 x86_machine_get_bus_lock_ratelimit, 1354 x86_machine_set_bus_lock_ratelimit, NULL, NULL); 1355 object_class_property_set_description(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, 1356 "Set the ratelimit for the bus locks acquired in VMs"); 1357 1358 object_class_property_add(oc, "sgx-epc", "SgxEPC", 1359 machine_get_sgx_epc, machine_set_sgx_epc, 1360 NULL, NULL); 1361 object_class_property_set_description(oc, "sgx-epc", 1362 "SGX EPC device"); 1363 } 1364 1365 static const TypeInfo x86_machine_info = { 1366 .name = TYPE_X86_MACHINE, 1367 .parent = TYPE_MACHINE, 1368 .abstract = true, 1369 .instance_size = sizeof(X86MachineState), 1370 .instance_init = x86_machine_initfn, 1371 .class_size = sizeof(X86MachineClass), 1372 .class_init = x86_machine_class_init, 1373 .interfaces = (InterfaceInfo[]) { 1374 { TYPE_NMI }, 1375 { } 1376 }, 1377 }; 1378 1379 static void x86_machine_register_types(void) 1380 { 1381 type_register_static(&x86_machine_info); 1382 } 1383 1384 type_init(x86_machine_register_types) 1385