1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu/datadir.h" 29 #include "qemu/guest-random.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-visit-common.h" 32 #include "qapi/clone-visitor.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/qtest.h" 36 #include "sysemu/whpx.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/replay.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/sysemu.h" 41 #include "sysemu/cpu-timers.h" 42 #include "sysemu/xen.h" 43 #include "trace.h" 44 45 #include "hw/i386/x86.h" 46 #include "target/i386/cpu.h" 47 #include "hw/i386/topology.h" 48 #include "hw/i386/fw_cfg.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/rtc/mc146818rtc.h" 51 #include "target/i386/sev.h" 52 #include "hw/i386/microvm.h" 53 54 #include "hw/acpi/cpu_hotplug.h" 55 #include "hw/irq.h" 56 #include "hw/nmi.h" 57 #include "hw/loader.h" 58 #include "multiboot.h" 59 #include "elf.h" 60 #include "standard-headers/asm-x86/bootparam.h" 61 #include CONFIG_DEVICES 62 #include "kvm/kvm_i386.h" 63 64 #ifdef CONFIG_XEN_EMU 65 #include "hw/xen/xen.h" 66 #include "hw/i386/kvm/xen_evtchn.h" 67 #endif 68 69 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 70 static size_t pvh_start_addr; 71 72 static void init_topo_info(X86CPUTopoInfo *topo_info, 73 const X86MachineState *x86ms) 74 { 75 MachineState *ms = MACHINE(x86ms); 76 77 topo_info->dies_per_pkg = ms->smp.dies; 78 topo_info->cores_per_die = ms->smp.cores; 79 topo_info->threads_per_core = ms->smp.threads; 80 } 81 82 /* 83 * Calculates initial APIC ID for a specific CPU index 84 * 85 * Currently we need to be able to calculate the APIC ID from the CPU index 86 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 87 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 88 * all CPUs up to max_cpus. 89 */ 90 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 91 unsigned int cpu_index) 92 { 93 X86CPUTopoInfo topo_info; 94 95 init_topo_info(&topo_info, x86ms); 96 97 return x86_apicid_from_cpu_idx(&topo_info, cpu_index); 98 } 99 100 101 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 102 { 103 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 104 105 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 106 goto out; 107 } 108 qdev_realize(DEVICE(cpu), NULL, errp); 109 110 out: 111 object_unref(cpu); 112 } 113 114 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 115 { 116 int i; 117 const CPUArchIdList *possible_cpus; 118 MachineState *ms = MACHINE(x86ms); 119 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 120 121 x86_cpu_set_default_version(default_cpu_version); 122 123 /* 124 * Calculates the limit to CPU APIC ID values 125 * 126 * Limit for the APIC ID value, so that all 127 * CPU APIC IDs are < x86ms->apic_id_limit. 128 * 129 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 130 */ 131 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 132 ms->smp.max_cpus - 1) + 1; 133 134 /* 135 * Can we support APIC ID 255 or higher? 136 * 137 * Under Xen: yes. 138 * With userspace emulated lapic: no 139 * With KVM's in-kernel lapic: only if X2APIC API is enabled. 140 */ 141 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 142 (!kvm_irqchip_in_kernel() || !kvm_enable_x2apic())) { 143 error_report("current -smp configuration requires kernel " 144 "irqchip and X2APIC API support."); 145 exit(EXIT_FAILURE); 146 } 147 148 if (kvm_enabled()) { 149 kvm_set_max_apic_id(x86ms->apic_id_limit); 150 } 151 152 possible_cpus = mc->possible_cpu_arch_ids(ms); 153 for (i = 0; i < ms->smp.cpus; i++) { 154 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 155 } 156 } 157 158 void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) 159 { 160 MC146818RtcState *rtc = MC146818_RTC(s); 161 162 if (cpus_count > 0xff) { 163 /* 164 * If the number of CPUs can't be represented in 8 bits, the 165 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 166 * to make old BIOSes fail more predictably. 167 */ 168 mc146818rtc_set_cmos_data(rtc, 0x5f, 0); 169 } else { 170 mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); 171 } 172 } 173 174 static int x86_apic_cmp(const void *a, const void *b) 175 { 176 CPUArchId *apic_a = (CPUArchId *)a; 177 CPUArchId *apic_b = (CPUArchId *)b; 178 179 return apic_a->arch_id - apic_b->arch_id; 180 } 181 182 /* 183 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 184 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 185 * entry corresponding to CPU's apic_id returns NULL. 186 */ 187 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 188 { 189 CPUArchId apic_id, *found_cpu; 190 191 apic_id.arch_id = id; 192 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 193 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 194 x86_apic_cmp); 195 if (found_cpu && idx) { 196 *idx = found_cpu - ms->possible_cpus->cpus; 197 } 198 return found_cpu; 199 } 200 201 void x86_cpu_plug(HotplugHandler *hotplug_dev, 202 DeviceState *dev, Error **errp) 203 { 204 CPUArchId *found_cpu; 205 Error *local_err = NULL; 206 X86CPU *cpu = X86_CPU(dev); 207 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 208 209 if (x86ms->acpi_dev) { 210 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 211 if (local_err) { 212 goto out; 213 } 214 } 215 216 /* increment the number of CPUs */ 217 x86ms->boot_cpus++; 218 if (x86ms->rtc) { 219 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 220 } 221 if (x86ms->fw_cfg) { 222 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 223 } 224 225 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 226 found_cpu->cpu = OBJECT(dev); 227 out: 228 error_propagate(errp, local_err); 229 } 230 231 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 232 DeviceState *dev, Error **errp) 233 { 234 int idx = -1; 235 X86CPU *cpu = X86_CPU(dev); 236 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 237 238 if (!x86ms->acpi_dev) { 239 error_setg(errp, "CPU hot unplug not supported without ACPI"); 240 return; 241 } 242 243 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 244 assert(idx != -1); 245 if (idx == 0) { 246 error_setg(errp, "Boot CPU is unpluggable"); 247 return; 248 } 249 250 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 251 errp); 252 } 253 254 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 255 DeviceState *dev, Error **errp) 256 { 257 CPUArchId *found_cpu; 258 Error *local_err = NULL; 259 X86CPU *cpu = X86_CPU(dev); 260 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 261 262 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 263 if (local_err) { 264 goto out; 265 } 266 267 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 268 found_cpu->cpu = NULL; 269 qdev_unrealize(dev); 270 271 /* decrement the number of CPUs */ 272 x86ms->boot_cpus--; 273 /* Update the number of CPUs in CMOS */ 274 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 275 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 276 out: 277 error_propagate(errp, local_err); 278 } 279 280 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 281 DeviceState *dev, Error **errp) 282 { 283 int idx; 284 CPUState *cs; 285 CPUArchId *cpu_slot; 286 X86CPUTopoIDs topo_ids; 287 X86CPU *cpu = X86_CPU(dev); 288 CPUX86State *env = &cpu->env; 289 MachineState *ms = MACHINE(hotplug_dev); 290 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 291 unsigned int smp_cores = ms->smp.cores; 292 unsigned int smp_threads = ms->smp.threads; 293 X86CPUTopoInfo topo_info; 294 295 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 296 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 297 ms->cpu_type); 298 return; 299 } 300 301 if (x86ms->acpi_dev) { 302 Error *local_err = NULL; 303 304 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 305 &local_err); 306 if (local_err) { 307 error_propagate(errp, local_err); 308 return; 309 } 310 } 311 312 init_topo_info(&topo_info, x86ms); 313 314 env->nr_dies = ms->smp.dies; 315 316 /* 317 * If APIC ID is not set, 318 * set it based on socket/die/core/thread properties. 319 */ 320 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 321 int max_socket = (ms->smp.max_cpus - 1) / 322 smp_threads / smp_cores / ms->smp.dies; 323 324 /* 325 * die-id was optional in QEMU 4.0 and older, so keep it optional 326 * if there's only one die per socket. 327 */ 328 if (cpu->die_id < 0 && ms->smp.dies == 1) { 329 cpu->die_id = 0; 330 } 331 332 if (cpu->socket_id < 0) { 333 error_setg(errp, "CPU socket-id is not set"); 334 return; 335 } else if (cpu->socket_id > max_socket) { 336 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 337 cpu->socket_id, max_socket); 338 return; 339 } 340 if (cpu->die_id < 0) { 341 error_setg(errp, "CPU die-id is not set"); 342 return; 343 } else if (cpu->die_id > ms->smp.dies - 1) { 344 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 345 cpu->die_id, ms->smp.dies - 1); 346 return; 347 } 348 if (cpu->core_id < 0) { 349 error_setg(errp, "CPU core-id is not set"); 350 return; 351 } else if (cpu->core_id > (smp_cores - 1)) { 352 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 353 cpu->core_id, smp_cores - 1); 354 return; 355 } 356 if (cpu->thread_id < 0) { 357 error_setg(errp, "CPU thread-id is not set"); 358 return; 359 } else if (cpu->thread_id > (smp_threads - 1)) { 360 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 361 cpu->thread_id, smp_threads - 1); 362 return; 363 } 364 365 topo_ids.pkg_id = cpu->socket_id; 366 topo_ids.die_id = cpu->die_id; 367 topo_ids.core_id = cpu->core_id; 368 topo_ids.smt_id = cpu->thread_id; 369 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 370 } 371 372 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 373 if (!cpu_slot) { 374 MachineState *ms = MACHINE(x86ms); 375 376 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 377 error_setg(errp, 378 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 379 " APIC ID %" PRIu32 ", valid index range 0:%d", 380 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 381 cpu->apic_id, ms->possible_cpus->len - 1); 382 return; 383 } 384 385 if (cpu_slot->cpu) { 386 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 387 idx, cpu->apic_id); 388 return; 389 } 390 391 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 392 * so that machine_query_hotpluggable_cpus would show correct values 393 */ 394 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 395 * once -smp refactoring is complete and there will be CPU private 396 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 397 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 398 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 399 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 400 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 401 topo_ids.pkg_id); 402 return; 403 } 404 cpu->socket_id = topo_ids.pkg_id; 405 406 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 407 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 408 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 409 return; 410 } 411 cpu->die_id = topo_ids.die_id; 412 413 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 414 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 415 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 416 topo_ids.core_id); 417 return; 418 } 419 cpu->core_id = topo_ids.core_id; 420 421 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 422 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 423 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 424 topo_ids.smt_id); 425 return; 426 } 427 cpu->thread_id = topo_ids.smt_id; 428 429 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 430 !kvm_hv_vpindex_settable()) { 431 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 432 return; 433 } 434 435 cs = CPU(cpu); 436 cs->cpu_index = idx; 437 438 numa_cpu_pre_plug(cpu_slot, dev, errp); 439 } 440 441 CpuInstanceProperties 442 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 443 { 444 MachineClass *mc = MACHINE_GET_CLASS(ms); 445 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 446 447 assert(cpu_index < possible_cpus->len); 448 return possible_cpus->cpus[cpu_index].props; 449 } 450 451 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 452 { 453 X86CPUTopoIDs topo_ids; 454 X86MachineState *x86ms = X86_MACHINE(ms); 455 X86CPUTopoInfo topo_info; 456 457 init_topo_info(&topo_info, x86ms); 458 459 assert(idx < ms->possible_cpus->len); 460 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 461 &topo_info, &topo_ids); 462 return topo_ids.pkg_id % ms->numa_state->num_nodes; 463 } 464 465 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 466 { 467 X86MachineState *x86ms = X86_MACHINE(ms); 468 unsigned int max_cpus = ms->smp.max_cpus; 469 X86CPUTopoInfo topo_info; 470 int i; 471 472 if (ms->possible_cpus) { 473 /* 474 * make sure that max_cpus hasn't changed since the first use, i.e. 475 * -smp hasn't been parsed after it 476 */ 477 assert(ms->possible_cpus->len == max_cpus); 478 return ms->possible_cpus; 479 } 480 481 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 482 sizeof(CPUArchId) * max_cpus); 483 ms->possible_cpus->len = max_cpus; 484 485 init_topo_info(&topo_info, x86ms); 486 487 for (i = 0; i < ms->possible_cpus->len; i++) { 488 X86CPUTopoIDs topo_ids; 489 490 ms->possible_cpus->cpus[i].type = ms->cpu_type; 491 ms->possible_cpus->cpus[i].vcpus_count = 1; 492 ms->possible_cpus->cpus[i].arch_id = 493 x86_cpu_apic_id_from_index(x86ms, i); 494 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 495 &topo_info, &topo_ids); 496 ms->possible_cpus->cpus[i].props.has_socket_id = true; 497 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 498 if (ms->smp.dies > 1) { 499 ms->possible_cpus->cpus[i].props.has_die_id = true; 500 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 501 } 502 ms->possible_cpus->cpus[i].props.has_core_id = true; 503 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 504 ms->possible_cpus->cpus[i].props.has_thread_id = true; 505 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 506 } 507 return ms->possible_cpus; 508 } 509 510 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 511 { 512 /* cpu index isn't used */ 513 CPUState *cs; 514 515 CPU_FOREACH(cs) { 516 X86CPU *cpu = X86_CPU(cs); 517 518 if (!cpu->apic_state) { 519 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 520 } else { 521 apic_deliver_nmi(cpu->apic_state); 522 } 523 } 524 } 525 526 static long get_file_size(FILE *f) 527 { 528 long where, size; 529 530 /* XXX: on Unix systems, using fstat() probably makes more sense */ 531 532 where = ftell(f); 533 fseek(f, 0, SEEK_END); 534 size = ftell(f); 535 fseek(f, where, SEEK_SET); 536 537 return size; 538 } 539 540 /* TSC handling */ 541 uint64_t cpu_get_tsc(CPUX86State *env) 542 { 543 return cpus_get_elapsed_ticks(); 544 } 545 546 /* IRQ handling */ 547 static void pic_irq_request(void *opaque, int irq, int level) 548 { 549 CPUState *cs = first_cpu; 550 X86CPU *cpu = X86_CPU(cs); 551 552 trace_x86_pic_interrupt(irq, level); 553 if (cpu->apic_state && !kvm_irqchip_in_kernel() && 554 !whpx_apic_in_platform()) { 555 CPU_FOREACH(cs) { 556 cpu = X86_CPU(cs); 557 if (apic_accept_pic_intr(cpu->apic_state)) { 558 apic_deliver_pic_intr(cpu->apic_state, level); 559 } 560 } 561 } else { 562 if (level) { 563 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 564 } else { 565 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 566 } 567 } 568 } 569 570 qemu_irq x86_allocate_cpu_irq(void) 571 { 572 return qemu_allocate_irq(pic_irq_request, NULL, 0); 573 } 574 575 int cpu_get_pic_interrupt(CPUX86State *env) 576 { 577 X86CPU *cpu = env_archcpu(env); 578 int intno; 579 580 if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { 581 intno = apic_get_interrupt(cpu->apic_state); 582 if (intno >= 0) { 583 return intno; 584 } 585 /* read the irq from the PIC */ 586 if (!apic_accept_pic_intr(cpu->apic_state)) { 587 return -1; 588 } 589 } 590 591 intno = pic_read_irq(isa_pic); 592 return intno; 593 } 594 595 DeviceState *cpu_get_current_apic(void) 596 { 597 if (current_cpu) { 598 X86CPU *cpu = X86_CPU(current_cpu); 599 return cpu->apic_state; 600 } else { 601 return NULL; 602 } 603 } 604 605 void gsi_handler(void *opaque, int n, int level) 606 { 607 GSIState *s = opaque; 608 609 trace_x86_gsi_interrupt(n, level); 610 switch (n) { 611 case 0 ... ISA_NUM_IRQS - 1: 612 if (s->i8259_irq[n]) { 613 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 614 qemu_set_irq(s->i8259_irq[n], level); 615 } 616 /* fall through */ 617 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 618 #ifdef CONFIG_XEN_EMU 619 /* 620 * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC 621 * routing actually works properly under Xen). And then to 622 * *either* the PIRQ handling or the I/OAPIC depending on 623 * whether the former wants it. 624 */ 625 if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { 626 break; 627 } 628 #endif 629 qemu_set_irq(s->ioapic_irq[n], level); 630 break; 631 case IO_APIC_SECONDARY_IRQBASE 632 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 633 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 634 break; 635 } 636 } 637 638 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 639 { 640 DeviceState *dev; 641 SysBusDevice *d; 642 unsigned int i; 643 644 assert(parent_name); 645 if (kvm_ioapic_in_kernel()) { 646 dev = qdev_new(TYPE_KVM_IOAPIC); 647 } else { 648 dev = qdev_new(TYPE_IOAPIC); 649 } 650 object_property_add_child(object_resolve_path(parent_name, NULL), 651 "ioapic", OBJECT(dev)); 652 d = SYS_BUS_DEVICE(dev); 653 sysbus_realize_and_unref(d, &error_fatal); 654 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 655 656 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 657 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 658 } 659 } 660 661 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 662 { 663 DeviceState *dev; 664 SysBusDevice *d; 665 unsigned int i; 666 667 dev = qdev_new(TYPE_IOAPIC); 668 d = SYS_BUS_DEVICE(dev); 669 sysbus_realize_and_unref(d, &error_fatal); 670 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 671 672 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 673 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 674 } 675 return dev; 676 } 677 678 typedef struct SetupData { 679 uint64_t next; 680 uint32_t type; 681 uint32_t len; 682 uint8_t data[]; 683 } __attribute__((packed)) SetupData; 684 685 686 /* 687 * The entry point into the kernel for PVH boot is different from 688 * the native entry point. The PVH entry is defined by the x86/HVM 689 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 690 * 691 * This function is passed to load_elf() when it is called from 692 * load_elfboot() which then additionally checks for an ELF Note of 693 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 694 * parse the PVH entry address from the ELF Note. 695 * 696 * Due to trickery in elf_opts.h, load_elf() is actually available as 697 * load_elf32() or load_elf64() and this routine needs to be able 698 * to deal with being called as 32 or 64 bit. 699 * 700 * The address of the PVH entry point is saved to the 'pvh_start_addr' 701 * global variable. (although the entry point is 32-bit, the kernel 702 * binary can be either 32-bit or 64-bit). 703 */ 704 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 705 { 706 size_t *elf_note_data_addr; 707 708 /* Check if ELF Note header passed in is valid */ 709 if (arg1 == NULL) { 710 return 0; 711 } 712 713 if (is64) { 714 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 715 uint64_t nhdr_size64 = sizeof(struct elf64_note); 716 uint64_t phdr_align = *(uint64_t *)arg2; 717 uint64_t nhdr_namesz = nhdr64->n_namesz; 718 719 elf_note_data_addr = 720 ((void *)nhdr64) + nhdr_size64 + 721 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 722 723 pvh_start_addr = *elf_note_data_addr; 724 } else { 725 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 726 uint32_t nhdr_size32 = sizeof(struct elf32_note); 727 uint32_t phdr_align = *(uint32_t *)arg2; 728 uint32_t nhdr_namesz = nhdr32->n_namesz; 729 730 elf_note_data_addr = 731 ((void *)nhdr32) + nhdr_size32 + 732 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 733 734 pvh_start_addr = *(uint32_t *)elf_note_data_addr; 735 } 736 737 return pvh_start_addr; 738 } 739 740 static bool load_elfboot(const char *kernel_filename, 741 int kernel_file_size, 742 uint8_t *header, 743 size_t pvh_xen_start_addr, 744 FWCfgState *fw_cfg) 745 { 746 uint32_t flags = 0; 747 uint32_t mh_load_addr = 0; 748 uint32_t elf_kernel_size = 0; 749 uint64_t elf_entry; 750 uint64_t elf_low, elf_high; 751 int kernel_size; 752 753 if (ldl_p(header) != 0x464c457f) { 754 return false; /* no elfboot */ 755 } 756 757 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 758 flags = elf_is64 ? 759 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 760 761 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 762 error_report("elfboot unsupported flags = %x", flags); 763 exit(1); 764 } 765 766 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 767 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 768 NULL, &elf_note_type, &elf_entry, 769 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 770 0, 0); 771 772 if (kernel_size < 0) { 773 error_report("Error while loading elf kernel"); 774 exit(1); 775 } 776 mh_load_addr = elf_low; 777 elf_kernel_size = elf_high - elf_low; 778 779 if (pvh_start_addr == 0) { 780 error_report("Error loading uncompressed kernel without PVH ELF Note"); 781 exit(1); 782 } 783 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 784 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 785 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 786 787 return true; 788 } 789 790 typedef struct SetupDataFixup { 791 void *pos; 792 hwaddr orig_val, new_val; 793 uint32_t addr; 794 } SetupDataFixup; 795 796 static void fixup_setup_data(void *opaque) 797 { 798 SetupDataFixup *fixup = opaque; 799 stq_p(fixup->pos, fixup->new_val); 800 } 801 802 static void reset_setup_data(void *opaque) 803 { 804 SetupDataFixup *fixup = opaque; 805 stq_p(fixup->pos, fixup->orig_val); 806 } 807 808 static void reset_rng_seed(void *opaque) 809 { 810 SetupData *setup_data = opaque; 811 qemu_guest_getrandom_nofail(setup_data->data, le32_to_cpu(setup_data->len)); 812 } 813 814 void x86_load_linux(X86MachineState *x86ms, 815 FWCfgState *fw_cfg, 816 int acpi_data_size, 817 bool pvh_enabled, 818 bool legacy_no_rng_seed) 819 { 820 bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; 821 uint16_t protocol; 822 int setup_size, kernel_size, cmdline_size; 823 int dtb_size, setup_data_offset; 824 uint32_t initrd_max; 825 uint8_t header[8192], *setup, *kernel; 826 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0, first_setup_data = 0; 827 FILE *f; 828 char *vmode; 829 MachineState *machine = MACHINE(x86ms); 830 SetupData *setup_data; 831 const char *kernel_filename = machine->kernel_filename; 832 const char *initrd_filename = machine->initrd_filename; 833 const char *dtb_filename = machine->dtb; 834 char *kernel_cmdline; 835 SevKernelLoaderContext sev_load_ctx = {}; 836 enum { RNG_SEED_LENGTH = 32 }; 837 838 /* 839 * Add the NUL terminator, some padding for the microvm cmdline fiddling 840 * hack, and then align to 16 bytes as a paranoia measure 841 */ 842 cmdline_size = (strlen(machine->kernel_cmdline) + 1 + 843 VIRTIO_CMDLINE_TOTAL_MAX_LEN + 16) & ~15; 844 /* Make a copy, since we might append arbitrary bytes to it later. */ 845 kernel_cmdline = g_strndup(machine->kernel_cmdline, cmdline_size); 846 847 /* load the kernel header */ 848 f = fopen(kernel_filename, "rb"); 849 if (!f) { 850 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 851 kernel_filename, strerror(errno)); 852 exit(1); 853 } 854 855 kernel_size = get_file_size(f); 856 if (!kernel_size || 857 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 858 MIN(ARRAY_SIZE(header), kernel_size)) { 859 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 860 kernel_filename, strerror(errno)); 861 exit(1); 862 } 863 864 /* kernel protocol version */ 865 if (ldl_p(header + 0x202) == 0x53726448) { 866 protocol = lduw_p(header + 0x206); 867 } else { 868 /* 869 * This could be a multiboot kernel. If it is, let's stop treating it 870 * like a Linux kernel. 871 * Note: some multiboot images could be in the ELF format (the same of 872 * PVH), so we try multiboot first since we check the multiboot magic 873 * header before to load it. 874 */ 875 if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, 876 kernel_cmdline, kernel_size, header)) { 877 return; 878 } 879 /* 880 * Check if the file is an uncompressed kernel file (ELF) and load it, 881 * saving the PVH entry point used by the x86/HVM direct boot ABI. 882 * If load_elfboot() is successful, populate the fw_cfg info. 883 */ 884 if (pvh_enabled && 885 load_elfboot(kernel_filename, kernel_size, 886 header, pvh_start_addr, fw_cfg)) { 887 fclose(f); 888 889 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 890 strlen(kernel_cmdline) + 1); 891 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 892 893 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 894 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 895 header, sizeof(header)); 896 897 /* load initrd */ 898 if (initrd_filename) { 899 GMappedFile *mapped_file; 900 gsize initrd_size; 901 gchar *initrd_data; 902 GError *gerr = NULL; 903 904 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 905 if (!mapped_file) { 906 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 907 initrd_filename, gerr->message); 908 exit(1); 909 } 910 x86ms->initrd_mapped_file = mapped_file; 911 912 initrd_data = g_mapped_file_get_contents(mapped_file); 913 initrd_size = g_mapped_file_get_length(mapped_file); 914 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 915 if (initrd_size >= initrd_max) { 916 fprintf(stderr, "qemu: initrd is too large, cannot support." 917 "(max: %"PRIu32", need %"PRId64")\n", 918 initrd_max, (uint64_t)initrd_size); 919 exit(1); 920 } 921 922 initrd_addr = (initrd_max - initrd_size) & ~4095; 923 924 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 925 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 926 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 927 initrd_size); 928 } 929 930 option_rom[nb_option_roms].bootindex = 0; 931 option_rom[nb_option_roms].name = "pvh.bin"; 932 nb_option_roms++; 933 934 return; 935 } 936 protocol = 0; 937 } 938 939 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 940 /* Low kernel */ 941 real_addr = 0x90000; 942 cmdline_addr = 0x9a000 - cmdline_size; 943 prot_addr = 0x10000; 944 } else if (protocol < 0x202) { 945 /* High but ancient kernel */ 946 real_addr = 0x90000; 947 cmdline_addr = 0x9a000 - cmdline_size; 948 prot_addr = 0x100000; 949 } else { 950 /* High and recent kernel */ 951 real_addr = 0x10000; 952 cmdline_addr = 0x20000; 953 prot_addr = 0x100000; 954 } 955 956 /* highest address for loading the initrd */ 957 if (protocol >= 0x20c && 958 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 959 /* 960 * Linux has supported initrd up to 4 GB for a very long time (2007, 961 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 962 * though it only sets initrd_max to 2 GB to "work around bootloader 963 * bugs". Luckily, QEMU firmware(which does something like bootloader) 964 * has supported this. 965 * 966 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 967 * be loaded into any address. 968 * 969 * In addition, initrd_max is uint32_t simply because QEMU doesn't 970 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 971 * field). 972 * 973 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 974 */ 975 initrd_max = UINT32_MAX; 976 } else if (protocol >= 0x203) { 977 initrd_max = ldl_p(header + 0x22c); 978 } else { 979 initrd_max = 0x37ffffff; 980 } 981 982 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 983 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 984 } 985 986 if (protocol >= 0x202) { 987 stl_p(header + 0x228, cmdline_addr); 988 } else { 989 stw_p(header + 0x20, 0xA33F); 990 stw_p(header + 0x22, cmdline_addr - real_addr); 991 } 992 993 /* handle vga= parameter */ 994 vmode = strstr(kernel_cmdline, "vga="); 995 if (vmode) { 996 unsigned int video_mode; 997 const char *end; 998 int ret; 999 /* skip "vga=" */ 1000 vmode += 4; 1001 if (!strncmp(vmode, "normal", 6)) { 1002 video_mode = 0xffff; 1003 } else if (!strncmp(vmode, "ext", 3)) { 1004 video_mode = 0xfffe; 1005 } else if (!strncmp(vmode, "ask", 3)) { 1006 video_mode = 0xfffd; 1007 } else { 1008 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 1009 if (ret != 0 || (*end && *end != ' ')) { 1010 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 1011 exit(1); 1012 } 1013 } 1014 stw_p(header + 0x1fa, video_mode); 1015 } 1016 1017 /* loader type */ 1018 /* 1019 * High nybble = B reserved for QEMU; low nybble is revision number. 1020 * If this code is substantially changed, you may want to consider 1021 * incrementing the revision. 1022 */ 1023 if (protocol >= 0x200) { 1024 header[0x210] = 0xB0; 1025 } 1026 /* heap */ 1027 if (protocol >= 0x201) { 1028 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1029 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 1030 } 1031 1032 /* load initrd */ 1033 if (initrd_filename) { 1034 GMappedFile *mapped_file; 1035 gsize initrd_size; 1036 gchar *initrd_data; 1037 GError *gerr = NULL; 1038 1039 if (protocol < 0x200) { 1040 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1041 exit(1); 1042 } 1043 1044 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1045 if (!mapped_file) { 1046 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1047 initrd_filename, gerr->message); 1048 exit(1); 1049 } 1050 x86ms->initrd_mapped_file = mapped_file; 1051 1052 initrd_data = g_mapped_file_get_contents(mapped_file); 1053 initrd_size = g_mapped_file_get_length(mapped_file); 1054 if (initrd_size >= initrd_max) { 1055 fprintf(stderr, "qemu: initrd is too large, cannot support." 1056 "(max: %"PRIu32", need %"PRId64")\n", 1057 initrd_max, (uint64_t)initrd_size); 1058 exit(1); 1059 } 1060 1061 initrd_addr = (initrd_max - initrd_size) & ~4095; 1062 1063 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1064 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1065 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1066 sev_load_ctx.initrd_data = initrd_data; 1067 sev_load_ctx.initrd_size = initrd_size; 1068 1069 stl_p(header + 0x218, initrd_addr); 1070 stl_p(header + 0x21c, initrd_size); 1071 } 1072 1073 /* load kernel and setup */ 1074 setup_size = header[0x1f1]; 1075 if (setup_size == 0) { 1076 setup_size = 4; 1077 } 1078 setup_size = (setup_size + 1) * 512; 1079 if (setup_size > kernel_size) { 1080 fprintf(stderr, "qemu: invalid kernel header\n"); 1081 exit(1); 1082 } 1083 kernel_size -= setup_size; 1084 1085 setup = g_malloc(setup_size); 1086 kernel = g_malloc(kernel_size); 1087 fseek(f, 0, SEEK_SET); 1088 if (fread(setup, 1, setup_size, f) != setup_size) { 1089 fprintf(stderr, "fread() failed\n"); 1090 exit(1); 1091 } 1092 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1093 fprintf(stderr, "fread() failed\n"); 1094 exit(1); 1095 } 1096 fclose(f); 1097 1098 /* append dtb to kernel */ 1099 if (dtb_filename) { 1100 if (protocol < 0x209) { 1101 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1102 exit(1); 1103 } 1104 1105 dtb_size = get_image_size(dtb_filename); 1106 if (dtb_size <= 0) { 1107 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1108 dtb_filename, strerror(errno)); 1109 exit(1); 1110 } 1111 1112 setup_data_offset = cmdline_size; 1113 cmdline_size += sizeof(SetupData) + dtb_size; 1114 kernel_cmdline = g_realloc(kernel_cmdline, cmdline_size); 1115 setup_data = (void *)kernel_cmdline + setup_data_offset; 1116 setup_data->next = cpu_to_le64(first_setup_data); 1117 first_setup_data = cmdline_addr + setup_data_offset; 1118 setup_data->type = cpu_to_le32(SETUP_DTB); 1119 setup_data->len = cpu_to_le32(dtb_size); 1120 load_image_size(dtb_filename, setup_data->data, dtb_size); 1121 } 1122 1123 if (!legacy_no_rng_seed && protocol >= 0x209) { 1124 setup_data_offset = cmdline_size; 1125 cmdline_size += sizeof(SetupData) + RNG_SEED_LENGTH; 1126 kernel_cmdline = g_realloc(kernel_cmdline, cmdline_size); 1127 setup_data = (void *)kernel_cmdline + setup_data_offset; 1128 setup_data->next = cpu_to_le64(first_setup_data); 1129 first_setup_data = cmdline_addr + setup_data_offset; 1130 setup_data->type = cpu_to_le32(SETUP_RNG_SEED); 1131 setup_data->len = cpu_to_le32(RNG_SEED_LENGTH); 1132 qemu_guest_getrandom_nofail(setup_data->data, RNG_SEED_LENGTH); 1133 qemu_register_reset_nosnapshotload(reset_rng_seed, setup_data); 1134 fw_cfg_add_bytes_callback(fw_cfg, FW_CFG_KERNEL_DATA, reset_rng_seed, NULL, 1135 setup_data, kernel, kernel_size, true); 1136 } else { 1137 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1138 } 1139 1140 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1141 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, cmdline_size); 1142 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline, cmdline_size); 1143 sev_load_ctx.cmdline_data = (char *)kernel_cmdline; 1144 sev_load_ctx.cmdline_size = cmdline_size; 1145 1146 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1147 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1148 sev_load_ctx.kernel_data = (char *)kernel; 1149 sev_load_ctx.kernel_size = kernel_size; 1150 1151 /* 1152 * If we're starting an encrypted VM, it will be OVMF based, which uses the 1153 * efi stub for booting and doesn't require any values to be placed in the 1154 * kernel header. We therefore don't update the header so the hash of the 1155 * kernel on the other side of the fw_cfg interface matches the hash of the 1156 * file the user passed in. 1157 */ 1158 if (!sev_enabled() && first_setup_data) { 1159 SetupDataFixup *fixup = g_malloc(sizeof(*fixup)); 1160 1161 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1162 /* Offset 0x250 is a pointer to the first setup_data link. */ 1163 fixup->pos = setup + 0x250; 1164 fixup->orig_val = ldq_p(fixup->pos); 1165 fixup->new_val = first_setup_data; 1166 fixup->addr = cpu_to_le32(real_addr); 1167 fw_cfg_add_bytes_callback(fw_cfg, FW_CFG_SETUP_ADDR, fixup_setup_data, NULL, 1168 fixup, &fixup->addr, sizeof(fixup->addr), true); 1169 qemu_register_reset(reset_setup_data, fixup); 1170 } else { 1171 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1172 } 1173 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1174 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1175 sev_load_ctx.setup_data = (char *)setup; 1176 sev_load_ctx.setup_size = setup_size; 1177 1178 if (sev_enabled()) { 1179 sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); 1180 } 1181 1182 option_rom[nb_option_roms].bootindex = 0; 1183 option_rom[nb_option_roms].name = "linuxboot.bin"; 1184 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1185 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1186 } 1187 nb_option_roms++; 1188 } 1189 1190 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 1191 MemoryRegion *rom_memory, bool isapc_ram_fw) 1192 { 1193 const char *bios_name; 1194 char *filename; 1195 MemoryRegion *bios, *isa_bios; 1196 int bios_size, isa_bios_size; 1197 ssize_t ret; 1198 1199 /* BIOS load */ 1200 bios_name = ms->firmware ?: default_firmware; 1201 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1202 if (filename) { 1203 bios_size = get_image_size(filename); 1204 } else { 1205 bios_size = -1; 1206 } 1207 if (bios_size <= 0 || 1208 (bios_size % 65536) != 0) { 1209 goto bios_error; 1210 } 1211 bios = g_malloc(sizeof(*bios)); 1212 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1213 if (sev_enabled()) { 1214 /* 1215 * The concept of a "reset" simply doesn't exist for 1216 * confidential computing guests, we have to destroy and 1217 * re-launch them instead. So there is no need to register 1218 * the firmware as rom to properly re-initialize on reset. 1219 * Just go for a straight file load instead. 1220 */ 1221 void *ptr = memory_region_get_ram_ptr(bios); 1222 load_image_size(filename, ptr, bios_size); 1223 x86_firmware_configure(ptr, bios_size); 1224 } else { 1225 if (!isapc_ram_fw) { 1226 memory_region_set_readonly(bios, true); 1227 } 1228 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1229 if (ret != 0) { 1230 goto bios_error; 1231 } 1232 } 1233 g_free(filename); 1234 1235 /* map the last 128KB of the BIOS in ISA space */ 1236 isa_bios_size = MIN(bios_size, 128 * KiB); 1237 isa_bios = g_malloc(sizeof(*isa_bios)); 1238 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1239 bios_size - isa_bios_size, isa_bios_size); 1240 memory_region_add_subregion_overlap(rom_memory, 1241 0x100000 - isa_bios_size, 1242 isa_bios, 1243 1); 1244 if (!isapc_ram_fw) { 1245 memory_region_set_readonly(isa_bios, true); 1246 } 1247 1248 /* map all the bios at the top of memory */ 1249 memory_region_add_subregion(rom_memory, 1250 (uint32_t)(-bios_size), 1251 bios); 1252 return; 1253 1254 bios_error: 1255 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1256 exit(1); 1257 } 1258 1259 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1260 { 1261 bool smm_available = false; 1262 1263 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1264 return false; 1265 } 1266 1267 if (tcg_enabled() || qtest_enabled()) { 1268 smm_available = true; 1269 } else if (kvm_enabled()) { 1270 smm_available = kvm_has_smm(); 1271 } 1272 1273 if (smm_available) { 1274 return true; 1275 } 1276 1277 if (x86ms->smm == ON_OFF_AUTO_ON) { 1278 error_report("System Management Mode not supported by this hypervisor."); 1279 exit(1); 1280 } 1281 return false; 1282 } 1283 1284 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1285 void *opaque, Error **errp) 1286 { 1287 X86MachineState *x86ms = X86_MACHINE(obj); 1288 OnOffAuto smm = x86ms->smm; 1289 1290 visit_type_OnOffAuto(v, name, &smm, errp); 1291 } 1292 1293 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1294 void *opaque, Error **errp) 1295 { 1296 X86MachineState *x86ms = X86_MACHINE(obj); 1297 1298 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1299 } 1300 1301 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1302 { 1303 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1304 return false; 1305 } 1306 return true; 1307 } 1308 1309 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1310 void *opaque, Error **errp) 1311 { 1312 X86MachineState *x86ms = X86_MACHINE(obj); 1313 OnOffAuto acpi = x86ms->acpi; 1314 1315 visit_type_OnOffAuto(v, name, &acpi, errp); 1316 } 1317 1318 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1319 void *opaque, Error **errp) 1320 { 1321 X86MachineState *x86ms = X86_MACHINE(obj); 1322 1323 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1324 } 1325 1326 static void x86_machine_get_pit(Object *obj, Visitor *v, const char *name, 1327 void *opaque, Error **errp) 1328 { 1329 X86MachineState *x86ms = X86_MACHINE(obj); 1330 OnOffAuto pit = x86ms->pit; 1331 1332 visit_type_OnOffAuto(v, name, &pit, errp); 1333 } 1334 1335 static void x86_machine_set_pit(Object *obj, Visitor *v, const char *name, 1336 void *opaque, Error **errp) 1337 { 1338 X86MachineState *x86ms = X86_MACHINE(obj);; 1339 1340 visit_type_OnOffAuto(v, name, &x86ms->pit, errp); 1341 } 1342 1343 static void x86_machine_get_pic(Object *obj, Visitor *v, const char *name, 1344 void *opaque, Error **errp) 1345 { 1346 X86MachineState *x86ms = X86_MACHINE(obj); 1347 OnOffAuto pic = x86ms->pic; 1348 1349 visit_type_OnOffAuto(v, name, &pic, errp); 1350 } 1351 1352 static void x86_machine_set_pic(Object *obj, Visitor *v, const char *name, 1353 void *opaque, Error **errp) 1354 { 1355 X86MachineState *x86ms = X86_MACHINE(obj); 1356 1357 visit_type_OnOffAuto(v, name, &x86ms->pic, errp); 1358 } 1359 1360 static char *x86_machine_get_oem_id(Object *obj, Error **errp) 1361 { 1362 X86MachineState *x86ms = X86_MACHINE(obj); 1363 1364 return g_strdup(x86ms->oem_id); 1365 } 1366 1367 static void x86_machine_set_oem_id(Object *obj, const char *value, Error **errp) 1368 { 1369 X86MachineState *x86ms = X86_MACHINE(obj); 1370 size_t len = strlen(value); 1371 1372 if (len > 6) { 1373 error_setg(errp, 1374 "User specified "X86_MACHINE_OEM_ID" value is bigger than " 1375 "6 bytes in size"); 1376 return; 1377 } 1378 1379 strncpy(x86ms->oem_id, value, 6); 1380 } 1381 1382 static char *x86_machine_get_oem_table_id(Object *obj, Error **errp) 1383 { 1384 X86MachineState *x86ms = X86_MACHINE(obj); 1385 1386 return g_strdup(x86ms->oem_table_id); 1387 } 1388 1389 static void x86_machine_set_oem_table_id(Object *obj, const char *value, 1390 Error **errp) 1391 { 1392 X86MachineState *x86ms = X86_MACHINE(obj); 1393 size_t len = strlen(value); 1394 1395 if (len > 8) { 1396 error_setg(errp, 1397 "User specified "X86_MACHINE_OEM_TABLE_ID 1398 " value is bigger than " 1399 "8 bytes in size"); 1400 return; 1401 } 1402 strncpy(x86ms->oem_table_id, value, 8); 1403 } 1404 1405 static void x86_machine_get_bus_lock_ratelimit(Object *obj, Visitor *v, 1406 const char *name, void *opaque, Error **errp) 1407 { 1408 X86MachineState *x86ms = X86_MACHINE(obj); 1409 uint64_t bus_lock_ratelimit = x86ms->bus_lock_ratelimit; 1410 1411 visit_type_uint64(v, name, &bus_lock_ratelimit, errp); 1412 } 1413 1414 static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, 1415 const char *name, void *opaque, Error **errp) 1416 { 1417 X86MachineState *x86ms = X86_MACHINE(obj); 1418 1419 visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); 1420 } 1421 1422 static void machine_get_sgx_epc(Object *obj, Visitor *v, const char *name, 1423 void *opaque, Error **errp) 1424 { 1425 X86MachineState *x86ms = X86_MACHINE(obj); 1426 SgxEPCList *list = x86ms->sgx_epc_list; 1427 1428 visit_type_SgxEPCList(v, name, &list, errp); 1429 } 1430 1431 static void machine_set_sgx_epc(Object *obj, Visitor *v, const char *name, 1432 void *opaque, Error **errp) 1433 { 1434 X86MachineState *x86ms = X86_MACHINE(obj); 1435 SgxEPCList *list; 1436 1437 list = x86ms->sgx_epc_list; 1438 visit_type_SgxEPCList(v, name, &x86ms->sgx_epc_list, errp); 1439 1440 qapi_free_SgxEPCList(list); 1441 } 1442 1443 static void x86_machine_initfn(Object *obj) 1444 { 1445 X86MachineState *x86ms = X86_MACHINE(obj); 1446 1447 x86ms->smm = ON_OFF_AUTO_AUTO; 1448 x86ms->acpi = ON_OFF_AUTO_AUTO; 1449 x86ms->pit = ON_OFF_AUTO_AUTO; 1450 x86ms->pic = ON_OFF_AUTO_AUTO; 1451 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1452 x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1453 x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1454 x86ms->bus_lock_ratelimit = 0; 1455 x86ms->above_4g_mem_start = 4 * GiB; 1456 } 1457 1458 static void x86_machine_class_init(ObjectClass *oc, void *data) 1459 { 1460 MachineClass *mc = MACHINE_CLASS(oc); 1461 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1462 NMIClass *nc = NMI_CLASS(oc); 1463 1464 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1465 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1466 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1467 x86mc->save_tsc_khz = true; 1468 x86mc->fwcfg_dma_enabled = true; 1469 nc->nmi_monitor_handler = x86_nmi; 1470 1471 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1472 x86_machine_get_smm, x86_machine_set_smm, 1473 NULL, NULL); 1474 object_class_property_set_description(oc, X86_MACHINE_SMM, 1475 "Enable SMM"); 1476 1477 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1478 x86_machine_get_acpi, x86_machine_set_acpi, 1479 NULL, NULL); 1480 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1481 "Enable ACPI"); 1482 1483 object_class_property_add(oc, X86_MACHINE_PIT, "OnOffAuto", 1484 x86_machine_get_pit, 1485 x86_machine_set_pit, 1486 NULL, NULL); 1487 object_class_property_set_description(oc, X86_MACHINE_PIT, 1488 "Enable i8254 PIT"); 1489 1490 object_class_property_add(oc, X86_MACHINE_PIC, "OnOffAuto", 1491 x86_machine_get_pic, 1492 x86_machine_set_pic, 1493 NULL, NULL); 1494 object_class_property_set_description(oc, X86_MACHINE_PIC, 1495 "Enable i8259 PIC"); 1496 1497 object_class_property_add_str(oc, X86_MACHINE_OEM_ID, 1498 x86_machine_get_oem_id, 1499 x86_machine_set_oem_id); 1500 object_class_property_set_description(oc, X86_MACHINE_OEM_ID, 1501 "Override the default value of field OEMID " 1502 "in ACPI table header." 1503 "The string may be up to 6 bytes in size"); 1504 1505 1506 object_class_property_add_str(oc, X86_MACHINE_OEM_TABLE_ID, 1507 x86_machine_get_oem_table_id, 1508 x86_machine_set_oem_table_id); 1509 object_class_property_set_description(oc, X86_MACHINE_OEM_TABLE_ID, 1510 "Override the default value of field OEM Table ID " 1511 "in ACPI table header." 1512 "The string may be up to 8 bytes in size"); 1513 1514 object_class_property_add(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, "uint64_t", 1515 x86_machine_get_bus_lock_ratelimit, 1516 x86_machine_set_bus_lock_ratelimit, NULL, NULL); 1517 object_class_property_set_description(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, 1518 "Set the ratelimit for the bus locks acquired in VMs"); 1519 1520 object_class_property_add(oc, "sgx-epc", "SgxEPC", 1521 machine_get_sgx_epc, machine_set_sgx_epc, 1522 NULL, NULL); 1523 object_class_property_set_description(oc, "sgx-epc", 1524 "SGX EPC device"); 1525 } 1526 1527 static const TypeInfo x86_machine_info = { 1528 .name = TYPE_X86_MACHINE, 1529 .parent = TYPE_MACHINE, 1530 .abstract = true, 1531 .instance_size = sizeof(X86MachineState), 1532 .instance_init = x86_machine_initfn, 1533 .class_size = sizeof(X86MachineClass), 1534 .class_init = x86_machine_class_init, 1535 .interfaces = (InterfaceInfo[]) { 1536 { TYPE_NMI }, 1537 { } 1538 }, 1539 }; 1540 1541 static void x86_machine_register_types(void) 1542 { 1543 type_register_static(&x86_machine_info); 1544 } 1545 1546 type_init(x86_machine_register_types) 1547