1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu/datadir.h" 29 #include "qapi/error.h" 30 #include "qapi/qapi-visit-common.h" 31 #include "qapi/clone-visitor.h" 32 #include "qapi/qapi-visit-machine.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/whpx.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/replay.h" 38 #include "sysemu/sysemu.h" 39 #include "sysemu/cpu-timers.h" 40 #include "sysemu/xen.h" 41 #include "trace.h" 42 43 #include "hw/i386/x86.h" 44 #include "target/i386/cpu.h" 45 #include "hw/i386/topology.h" 46 #include "hw/i386/fw_cfg.h" 47 #include "hw/intc/i8259.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "target/i386/sev.h" 50 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "hw/irq.h" 53 #include "hw/nmi.h" 54 #include "hw/loader.h" 55 #include "multiboot.h" 56 #include "elf.h" 57 #include "standard-headers/asm-x86/bootparam.h" 58 #include CONFIG_DEVICES 59 #include "kvm/kvm_i386.h" 60 61 #ifdef CONFIG_XEN_EMU 62 #include "hw/xen/xen.h" 63 #include "hw/i386/kvm/xen_evtchn.h" 64 #endif 65 66 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 67 static size_t pvh_start_addr; 68 69 static void init_topo_info(X86CPUTopoInfo *topo_info, 70 const X86MachineState *x86ms) 71 { 72 MachineState *ms = MACHINE(x86ms); 73 74 topo_info->dies_per_pkg = ms->smp.dies; 75 topo_info->cores_per_die = ms->smp.cores; 76 topo_info->threads_per_core = ms->smp.threads; 77 } 78 79 /* 80 * Calculates initial APIC ID for a specific CPU index 81 * 82 * Currently we need to be able to calculate the APIC ID from the CPU index 83 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 84 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 85 * all CPUs up to max_cpus. 86 */ 87 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 88 unsigned int cpu_index) 89 { 90 X86CPUTopoInfo topo_info; 91 92 init_topo_info(&topo_info, x86ms); 93 94 return x86_apicid_from_cpu_idx(&topo_info, cpu_index); 95 } 96 97 98 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 99 { 100 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 101 102 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 103 goto out; 104 } 105 qdev_realize(DEVICE(cpu), NULL, errp); 106 107 out: 108 object_unref(cpu); 109 } 110 111 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 112 { 113 int i; 114 const CPUArchIdList *possible_cpus; 115 MachineState *ms = MACHINE(x86ms); 116 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 117 118 x86_cpu_set_default_version(default_cpu_version); 119 120 /* 121 * Calculates the limit to CPU APIC ID values 122 * 123 * Limit for the APIC ID value, so that all 124 * CPU APIC IDs are < x86ms->apic_id_limit. 125 * 126 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 127 */ 128 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 129 ms->smp.max_cpus - 1) + 1; 130 131 /* 132 * Can we support APIC ID 255 or higher? With KVM, that requires 133 * both in-kernel lapic and X2APIC userspace API. 134 */ 135 if (x86ms->apic_id_limit > 255 && kvm_enabled() && 136 (!kvm_irqchip_in_kernel() || !kvm_enable_x2apic())) { 137 error_report("current -smp configuration requires kernel " 138 "irqchip and X2APIC API support."); 139 exit(EXIT_FAILURE); 140 } 141 142 if (kvm_enabled()) { 143 kvm_set_max_apic_id(x86ms->apic_id_limit); 144 } 145 146 possible_cpus = mc->possible_cpu_arch_ids(ms); 147 for (i = 0; i < ms->smp.cpus; i++) { 148 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 149 } 150 } 151 152 void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) 153 { 154 MC146818RtcState *rtc = MC146818_RTC(s); 155 156 if (cpus_count > 0xff) { 157 /* 158 * If the number of CPUs can't be represented in 8 bits, the 159 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 160 * to make old BIOSes fail more predictably. 161 */ 162 mc146818rtc_set_cmos_data(rtc, 0x5f, 0); 163 } else { 164 mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); 165 } 166 } 167 168 static int x86_apic_cmp(const void *a, const void *b) 169 { 170 CPUArchId *apic_a = (CPUArchId *)a; 171 CPUArchId *apic_b = (CPUArchId *)b; 172 173 return apic_a->arch_id - apic_b->arch_id; 174 } 175 176 /* 177 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 178 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 179 * entry corresponding to CPU's apic_id returns NULL. 180 */ 181 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 182 { 183 CPUArchId apic_id, *found_cpu; 184 185 apic_id.arch_id = id; 186 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 187 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 188 x86_apic_cmp); 189 if (found_cpu && idx) { 190 *idx = found_cpu - ms->possible_cpus->cpus; 191 } 192 return found_cpu; 193 } 194 195 void x86_cpu_plug(HotplugHandler *hotplug_dev, 196 DeviceState *dev, Error **errp) 197 { 198 CPUArchId *found_cpu; 199 Error *local_err = NULL; 200 X86CPU *cpu = X86_CPU(dev); 201 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 202 203 if (x86ms->acpi_dev) { 204 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 205 if (local_err) { 206 goto out; 207 } 208 } 209 210 /* increment the number of CPUs */ 211 x86ms->boot_cpus++; 212 if (x86ms->rtc) { 213 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 214 } 215 if (x86ms->fw_cfg) { 216 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 217 } 218 219 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 220 found_cpu->cpu = OBJECT(dev); 221 out: 222 error_propagate(errp, local_err); 223 } 224 225 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 226 DeviceState *dev, Error **errp) 227 { 228 int idx = -1; 229 X86CPU *cpu = X86_CPU(dev); 230 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 231 232 if (!x86ms->acpi_dev) { 233 error_setg(errp, "CPU hot unplug not supported without ACPI"); 234 return; 235 } 236 237 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 238 assert(idx != -1); 239 if (idx == 0) { 240 error_setg(errp, "Boot CPU is unpluggable"); 241 return; 242 } 243 244 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 245 errp); 246 } 247 248 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 249 DeviceState *dev, Error **errp) 250 { 251 CPUArchId *found_cpu; 252 Error *local_err = NULL; 253 X86CPU *cpu = X86_CPU(dev); 254 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 255 256 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 257 if (local_err) { 258 goto out; 259 } 260 261 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 262 found_cpu->cpu = NULL; 263 qdev_unrealize(dev); 264 265 /* decrement the number of CPUs */ 266 x86ms->boot_cpus--; 267 /* Update the number of CPUs in CMOS */ 268 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 269 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 270 out: 271 error_propagate(errp, local_err); 272 } 273 274 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 275 DeviceState *dev, Error **errp) 276 { 277 int idx; 278 CPUState *cs; 279 CPUArchId *cpu_slot; 280 X86CPUTopoIDs topo_ids; 281 X86CPU *cpu = X86_CPU(dev); 282 CPUX86State *env = &cpu->env; 283 MachineState *ms = MACHINE(hotplug_dev); 284 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 285 unsigned int smp_cores = ms->smp.cores; 286 unsigned int smp_threads = ms->smp.threads; 287 X86CPUTopoInfo topo_info; 288 289 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 290 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 291 ms->cpu_type); 292 return; 293 } 294 295 if (x86ms->acpi_dev) { 296 Error *local_err = NULL; 297 298 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 299 &local_err); 300 if (local_err) { 301 error_propagate(errp, local_err); 302 return; 303 } 304 } 305 306 init_topo_info(&topo_info, x86ms); 307 308 env->nr_dies = ms->smp.dies; 309 310 /* 311 * If APIC ID is not set, 312 * set it based on socket/die/core/thread properties. 313 */ 314 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 315 int max_socket = (ms->smp.max_cpus - 1) / 316 smp_threads / smp_cores / ms->smp.dies; 317 318 /* 319 * die-id was optional in QEMU 4.0 and older, so keep it optional 320 * if there's only one die per socket. 321 */ 322 if (cpu->die_id < 0 && ms->smp.dies == 1) { 323 cpu->die_id = 0; 324 } 325 326 if (cpu->socket_id < 0) { 327 error_setg(errp, "CPU socket-id is not set"); 328 return; 329 } else if (cpu->socket_id > max_socket) { 330 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 331 cpu->socket_id, max_socket); 332 return; 333 } 334 if (cpu->die_id < 0) { 335 error_setg(errp, "CPU die-id is not set"); 336 return; 337 } else if (cpu->die_id > ms->smp.dies - 1) { 338 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 339 cpu->die_id, ms->smp.dies - 1); 340 return; 341 } 342 if (cpu->core_id < 0) { 343 error_setg(errp, "CPU core-id is not set"); 344 return; 345 } else if (cpu->core_id > (smp_cores - 1)) { 346 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 347 cpu->core_id, smp_cores - 1); 348 return; 349 } 350 if (cpu->thread_id < 0) { 351 error_setg(errp, "CPU thread-id is not set"); 352 return; 353 } else if (cpu->thread_id > (smp_threads - 1)) { 354 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 355 cpu->thread_id, smp_threads - 1); 356 return; 357 } 358 359 topo_ids.pkg_id = cpu->socket_id; 360 topo_ids.die_id = cpu->die_id; 361 topo_ids.core_id = cpu->core_id; 362 topo_ids.smt_id = cpu->thread_id; 363 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 364 } 365 366 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 367 if (!cpu_slot) { 368 MachineState *ms = MACHINE(x86ms); 369 370 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 371 error_setg(errp, 372 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 373 " APIC ID %" PRIu32 ", valid index range 0:%d", 374 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 375 cpu->apic_id, ms->possible_cpus->len - 1); 376 return; 377 } 378 379 if (cpu_slot->cpu) { 380 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 381 idx, cpu->apic_id); 382 return; 383 } 384 385 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 386 * so that machine_query_hotpluggable_cpus would show correct values 387 */ 388 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 389 * once -smp refactoring is complete and there will be CPU private 390 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 391 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 392 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 393 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 394 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 395 topo_ids.pkg_id); 396 return; 397 } 398 cpu->socket_id = topo_ids.pkg_id; 399 400 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 401 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 402 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 403 return; 404 } 405 cpu->die_id = topo_ids.die_id; 406 407 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 408 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 409 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 410 topo_ids.core_id); 411 return; 412 } 413 cpu->core_id = topo_ids.core_id; 414 415 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 416 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 417 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 418 topo_ids.smt_id); 419 return; 420 } 421 cpu->thread_id = topo_ids.smt_id; 422 423 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 424 kvm_enabled() && !kvm_hv_vpindex_settable()) { 425 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 426 return; 427 } 428 429 cs = CPU(cpu); 430 cs->cpu_index = idx; 431 432 numa_cpu_pre_plug(cpu_slot, dev, errp); 433 } 434 435 CpuInstanceProperties 436 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 437 { 438 MachineClass *mc = MACHINE_GET_CLASS(ms); 439 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 440 441 assert(cpu_index < possible_cpus->len); 442 return possible_cpus->cpus[cpu_index].props; 443 } 444 445 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 446 { 447 X86CPUTopoIDs topo_ids; 448 X86MachineState *x86ms = X86_MACHINE(ms); 449 X86CPUTopoInfo topo_info; 450 451 init_topo_info(&topo_info, x86ms); 452 453 assert(idx < ms->possible_cpus->len); 454 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 455 &topo_info, &topo_ids); 456 return topo_ids.pkg_id % ms->numa_state->num_nodes; 457 } 458 459 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 460 { 461 X86MachineState *x86ms = X86_MACHINE(ms); 462 unsigned int max_cpus = ms->smp.max_cpus; 463 X86CPUTopoInfo topo_info; 464 int i; 465 466 if (ms->possible_cpus) { 467 /* 468 * make sure that max_cpus hasn't changed since the first use, i.e. 469 * -smp hasn't been parsed after it 470 */ 471 assert(ms->possible_cpus->len == max_cpus); 472 return ms->possible_cpus; 473 } 474 475 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 476 sizeof(CPUArchId) * max_cpus); 477 ms->possible_cpus->len = max_cpus; 478 479 init_topo_info(&topo_info, x86ms); 480 481 for (i = 0; i < ms->possible_cpus->len; i++) { 482 X86CPUTopoIDs topo_ids; 483 484 ms->possible_cpus->cpus[i].type = ms->cpu_type; 485 ms->possible_cpus->cpus[i].vcpus_count = 1; 486 ms->possible_cpus->cpus[i].arch_id = 487 x86_cpu_apic_id_from_index(x86ms, i); 488 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 489 &topo_info, &topo_ids); 490 ms->possible_cpus->cpus[i].props.has_socket_id = true; 491 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 492 if (ms->smp.dies > 1) { 493 ms->possible_cpus->cpus[i].props.has_die_id = true; 494 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 495 } 496 ms->possible_cpus->cpus[i].props.has_core_id = true; 497 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 498 ms->possible_cpus->cpus[i].props.has_thread_id = true; 499 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 500 } 501 return ms->possible_cpus; 502 } 503 504 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 505 { 506 /* cpu index isn't used */ 507 CPUState *cs; 508 509 CPU_FOREACH(cs) { 510 X86CPU *cpu = X86_CPU(cs); 511 512 if (!cpu->apic_state) { 513 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 514 } else { 515 apic_deliver_nmi(cpu->apic_state); 516 } 517 } 518 } 519 520 static long get_file_size(FILE *f) 521 { 522 long where, size; 523 524 /* XXX: on Unix systems, using fstat() probably makes more sense */ 525 526 where = ftell(f); 527 fseek(f, 0, SEEK_END); 528 size = ftell(f); 529 fseek(f, where, SEEK_SET); 530 531 return size; 532 } 533 534 /* TSC handling */ 535 uint64_t cpu_get_tsc(CPUX86State *env) 536 { 537 return cpus_get_elapsed_ticks(); 538 } 539 540 /* IRQ handling */ 541 static void pic_irq_request(void *opaque, int irq, int level) 542 { 543 CPUState *cs = first_cpu; 544 X86CPU *cpu = X86_CPU(cs); 545 546 trace_x86_pic_interrupt(irq, level); 547 if (cpu->apic_state && !kvm_irqchip_in_kernel() && 548 !whpx_apic_in_platform()) { 549 CPU_FOREACH(cs) { 550 cpu = X86_CPU(cs); 551 if (apic_accept_pic_intr(cpu->apic_state)) { 552 apic_deliver_pic_intr(cpu->apic_state, level); 553 } 554 } 555 } else { 556 if (level) { 557 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 558 } else { 559 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 560 } 561 } 562 } 563 564 qemu_irq x86_allocate_cpu_irq(void) 565 { 566 return qemu_allocate_irq(pic_irq_request, NULL, 0); 567 } 568 569 int cpu_get_pic_interrupt(CPUX86State *env) 570 { 571 X86CPU *cpu = env_archcpu(env); 572 int intno; 573 574 if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { 575 intno = apic_get_interrupt(cpu->apic_state); 576 if (intno >= 0) { 577 return intno; 578 } 579 /* read the irq from the PIC */ 580 if (!apic_accept_pic_intr(cpu->apic_state)) { 581 return -1; 582 } 583 } 584 585 intno = pic_read_irq(isa_pic); 586 return intno; 587 } 588 589 DeviceState *cpu_get_current_apic(void) 590 { 591 if (current_cpu) { 592 X86CPU *cpu = X86_CPU(current_cpu); 593 return cpu->apic_state; 594 } else { 595 return NULL; 596 } 597 } 598 599 void gsi_handler(void *opaque, int n, int level) 600 { 601 GSIState *s = opaque; 602 603 trace_x86_gsi_interrupt(n, level); 604 switch (n) { 605 case 0 ... ISA_NUM_IRQS - 1: 606 if (s->i8259_irq[n]) { 607 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 608 qemu_set_irq(s->i8259_irq[n], level); 609 } 610 /* fall through */ 611 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 612 #ifdef CONFIG_XEN_EMU 613 /* 614 * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC 615 * routing actually works properly under Xen). And then to 616 * *either* the PIRQ handling or the I/OAPIC depending on 617 * whether the former wants it. 618 */ 619 if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { 620 break; 621 } 622 #endif 623 qemu_set_irq(s->ioapic_irq[n], level); 624 break; 625 case IO_APIC_SECONDARY_IRQBASE 626 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 627 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 628 break; 629 } 630 } 631 632 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 633 { 634 DeviceState *dev; 635 SysBusDevice *d; 636 unsigned int i; 637 638 assert(parent_name); 639 if (kvm_ioapic_in_kernel()) { 640 dev = qdev_new(TYPE_KVM_IOAPIC); 641 } else { 642 dev = qdev_new(TYPE_IOAPIC); 643 } 644 object_property_add_child(object_resolve_path(parent_name, NULL), 645 "ioapic", OBJECT(dev)); 646 d = SYS_BUS_DEVICE(dev); 647 sysbus_realize_and_unref(d, &error_fatal); 648 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 649 650 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 651 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 652 } 653 } 654 655 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 656 { 657 DeviceState *dev; 658 SysBusDevice *d; 659 unsigned int i; 660 661 dev = qdev_new(TYPE_IOAPIC); 662 d = SYS_BUS_DEVICE(dev); 663 sysbus_realize_and_unref(d, &error_fatal); 664 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 665 666 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 667 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 668 } 669 return dev; 670 } 671 672 struct setup_data { 673 uint64_t next; 674 uint32_t type; 675 uint32_t len; 676 uint8_t data[]; 677 } __attribute__((packed)); 678 679 680 /* 681 * The entry point into the kernel for PVH boot is different from 682 * the native entry point. The PVH entry is defined by the x86/HVM 683 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 684 * 685 * This function is passed to load_elf() when it is called from 686 * load_elfboot() which then additionally checks for an ELF Note of 687 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 688 * parse the PVH entry address from the ELF Note. 689 * 690 * Due to trickery in elf_opts.h, load_elf() is actually available as 691 * load_elf32() or load_elf64() and this routine needs to be able 692 * to deal with being called as 32 or 64 bit. 693 * 694 * The address of the PVH entry point is saved to the 'pvh_start_addr' 695 * global variable. (although the entry point is 32-bit, the kernel 696 * binary can be either 32-bit or 64-bit). 697 */ 698 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 699 { 700 size_t *elf_note_data_addr; 701 702 /* Check if ELF Note header passed in is valid */ 703 if (arg1 == NULL) { 704 return 0; 705 } 706 707 if (is64) { 708 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 709 uint64_t nhdr_size64 = sizeof(struct elf64_note); 710 uint64_t phdr_align = *(uint64_t *)arg2; 711 uint64_t nhdr_namesz = nhdr64->n_namesz; 712 713 elf_note_data_addr = 714 ((void *)nhdr64) + nhdr_size64 + 715 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 716 717 pvh_start_addr = *elf_note_data_addr; 718 } else { 719 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 720 uint32_t nhdr_size32 = sizeof(struct elf32_note); 721 uint32_t phdr_align = *(uint32_t *)arg2; 722 uint32_t nhdr_namesz = nhdr32->n_namesz; 723 724 elf_note_data_addr = 725 ((void *)nhdr32) + nhdr_size32 + 726 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 727 728 pvh_start_addr = *(uint32_t *)elf_note_data_addr; 729 } 730 731 return pvh_start_addr; 732 } 733 734 static bool load_elfboot(const char *kernel_filename, 735 int kernel_file_size, 736 uint8_t *header, 737 size_t pvh_xen_start_addr, 738 FWCfgState *fw_cfg) 739 { 740 uint32_t flags = 0; 741 uint32_t mh_load_addr = 0; 742 uint32_t elf_kernel_size = 0; 743 uint64_t elf_entry; 744 uint64_t elf_low, elf_high; 745 int kernel_size; 746 747 if (ldl_p(header) != 0x464c457f) { 748 return false; /* no elfboot */ 749 } 750 751 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 752 flags = elf_is64 ? 753 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 754 755 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 756 error_report("elfboot unsupported flags = %x", flags); 757 exit(1); 758 } 759 760 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 761 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 762 NULL, &elf_note_type, &elf_entry, 763 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 764 0, 0); 765 766 if (kernel_size < 0) { 767 error_report("Error while loading elf kernel"); 768 exit(1); 769 } 770 mh_load_addr = elf_low; 771 elf_kernel_size = elf_high - elf_low; 772 773 if (pvh_start_addr == 0) { 774 error_report("Error loading uncompressed kernel without PVH ELF Note"); 775 exit(1); 776 } 777 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 778 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 779 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 780 781 return true; 782 } 783 784 void x86_load_linux(X86MachineState *x86ms, 785 FWCfgState *fw_cfg, 786 int acpi_data_size, 787 bool pvh_enabled) 788 { 789 bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; 790 uint16_t protocol; 791 int setup_size, kernel_size, cmdline_size; 792 int dtb_size, setup_data_offset; 793 uint32_t initrd_max; 794 uint8_t header[8192], *setup, *kernel; 795 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 796 FILE *f; 797 char *vmode; 798 MachineState *machine = MACHINE(x86ms); 799 struct setup_data *setup_data; 800 const char *kernel_filename = machine->kernel_filename; 801 const char *initrd_filename = machine->initrd_filename; 802 const char *dtb_filename = machine->dtb; 803 const char *kernel_cmdline = machine->kernel_cmdline; 804 SevKernelLoaderContext sev_load_ctx = {}; 805 806 /* Align to 16 bytes as a paranoia measure */ 807 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; 808 809 /* load the kernel header */ 810 f = fopen(kernel_filename, "rb"); 811 if (!f) { 812 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 813 kernel_filename, strerror(errno)); 814 exit(1); 815 } 816 817 kernel_size = get_file_size(f); 818 if (!kernel_size || 819 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 820 MIN(ARRAY_SIZE(header), kernel_size)) { 821 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 822 kernel_filename, strerror(errno)); 823 exit(1); 824 } 825 826 /* kernel protocol version */ 827 if (ldl_p(header + 0x202) == 0x53726448) { 828 protocol = lduw_p(header + 0x206); 829 } else { 830 /* 831 * This could be a multiboot kernel. If it is, let's stop treating it 832 * like a Linux kernel. 833 * Note: some multiboot images could be in the ELF format (the same of 834 * PVH), so we try multiboot first since we check the multiboot magic 835 * header before to load it. 836 */ 837 if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, 838 kernel_cmdline, kernel_size, header)) { 839 return; 840 } 841 /* 842 * Check if the file is an uncompressed kernel file (ELF) and load it, 843 * saving the PVH entry point used by the x86/HVM direct boot ABI. 844 * If load_elfboot() is successful, populate the fw_cfg info. 845 */ 846 if (pvh_enabled && 847 load_elfboot(kernel_filename, kernel_size, 848 header, pvh_start_addr, fw_cfg)) { 849 fclose(f); 850 851 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 852 strlen(kernel_cmdline) + 1); 853 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 854 855 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 856 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 857 header, sizeof(header)); 858 859 /* load initrd */ 860 if (initrd_filename) { 861 GMappedFile *mapped_file; 862 gsize initrd_size; 863 gchar *initrd_data; 864 GError *gerr = NULL; 865 866 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 867 if (!mapped_file) { 868 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 869 initrd_filename, gerr->message); 870 exit(1); 871 } 872 x86ms->initrd_mapped_file = mapped_file; 873 874 initrd_data = g_mapped_file_get_contents(mapped_file); 875 initrd_size = g_mapped_file_get_length(mapped_file); 876 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 877 if (initrd_size >= initrd_max) { 878 fprintf(stderr, "qemu: initrd is too large, cannot support." 879 "(max: %"PRIu32", need %"PRId64")\n", 880 initrd_max, (uint64_t)initrd_size); 881 exit(1); 882 } 883 884 initrd_addr = (initrd_max - initrd_size) & ~4095; 885 886 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 887 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 888 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 889 initrd_size); 890 } 891 892 option_rom[nb_option_roms].bootindex = 0; 893 option_rom[nb_option_roms].name = "pvh.bin"; 894 nb_option_roms++; 895 896 return; 897 } 898 protocol = 0; 899 } 900 901 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 902 /* Low kernel */ 903 real_addr = 0x90000; 904 cmdline_addr = 0x9a000 - cmdline_size; 905 prot_addr = 0x10000; 906 } else if (protocol < 0x202) { 907 /* High but ancient kernel */ 908 real_addr = 0x90000; 909 cmdline_addr = 0x9a000 - cmdline_size; 910 prot_addr = 0x100000; 911 } else { 912 /* High and recent kernel */ 913 real_addr = 0x10000; 914 cmdline_addr = 0x20000; 915 prot_addr = 0x100000; 916 } 917 918 /* highest address for loading the initrd */ 919 if (protocol >= 0x20c && 920 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 921 /* 922 * Linux has supported initrd up to 4 GB for a very long time (2007, 923 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 924 * though it only sets initrd_max to 2 GB to "work around bootloader 925 * bugs". Luckily, QEMU firmware(which does something like bootloader) 926 * has supported this. 927 * 928 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 929 * be loaded into any address. 930 * 931 * In addition, initrd_max is uint32_t simply because QEMU doesn't 932 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 933 * field). 934 * 935 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 936 */ 937 initrd_max = UINT32_MAX; 938 } else if (protocol >= 0x203) { 939 initrd_max = ldl_p(header + 0x22c); 940 } else { 941 initrd_max = 0x37ffffff; 942 } 943 944 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 945 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 946 } 947 948 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 949 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); 950 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 951 sev_load_ctx.cmdline_data = (char *)kernel_cmdline; 952 sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; 953 954 if (protocol >= 0x202) { 955 stl_p(header + 0x228, cmdline_addr); 956 } else { 957 stw_p(header + 0x20, 0xA33F); 958 stw_p(header + 0x22, cmdline_addr - real_addr); 959 } 960 961 /* handle vga= parameter */ 962 vmode = strstr(kernel_cmdline, "vga="); 963 if (vmode) { 964 unsigned int video_mode; 965 const char *end; 966 int ret; 967 /* skip "vga=" */ 968 vmode += 4; 969 if (!strncmp(vmode, "normal", 6)) { 970 video_mode = 0xffff; 971 } else if (!strncmp(vmode, "ext", 3)) { 972 video_mode = 0xfffe; 973 } else if (!strncmp(vmode, "ask", 3)) { 974 video_mode = 0xfffd; 975 } else { 976 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 977 if (ret != 0 || (*end && *end != ' ')) { 978 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 979 exit(1); 980 } 981 } 982 stw_p(header + 0x1fa, video_mode); 983 } 984 985 /* loader type */ 986 /* 987 * High nybble = B reserved for QEMU; low nybble is revision number. 988 * If this code is substantially changed, you may want to consider 989 * incrementing the revision. 990 */ 991 if (protocol >= 0x200) { 992 header[0x210] = 0xB0; 993 } 994 /* heap */ 995 if (protocol >= 0x201) { 996 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 997 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 998 } 999 1000 /* load initrd */ 1001 if (initrd_filename) { 1002 GMappedFile *mapped_file; 1003 gsize initrd_size; 1004 gchar *initrd_data; 1005 GError *gerr = NULL; 1006 1007 if (protocol < 0x200) { 1008 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1009 exit(1); 1010 } 1011 1012 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1013 if (!mapped_file) { 1014 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1015 initrd_filename, gerr->message); 1016 exit(1); 1017 } 1018 x86ms->initrd_mapped_file = mapped_file; 1019 1020 initrd_data = g_mapped_file_get_contents(mapped_file); 1021 initrd_size = g_mapped_file_get_length(mapped_file); 1022 if (initrd_size >= initrd_max) { 1023 fprintf(stderr, "qemu: initrd is too large, cannot support." 1024 "(max: %"PRIu32", need %"PRId64")\n", 1025 initrd_max, (uint64_t)initrd_size); 1026 exit(1); 1027 } 1028 1029 initrd_addr = (initrd_max - initrd_size) & ~4095; 1030 1031 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1032 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1033 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1034 sev_load_ctx.initrd_data = initrd_data; 1035 sev_load_ctx.initrd_size = initrd_size; 1036 1037 stl_p(header + 0x218, initrd_addr); 1038 stl_p(header + 0x21c, initrd_size); 1039 } 1040 1041 /* load kernel and setup */ 1042 setup_size = header[0x1f1]; 1043 if (setup_size == 0) { 1044 setup_size = 4; 1045 } 1046 setup_size = (setup_size + 1) * 512; 1047 if (setup_size > kernel_size) { 1048 fprintf(stderr, "qemu: invalid kernel header\n"); 1049 exit(1); 1050 } 1051 kernel_size -= setup_size; 1052 1053 setup = g_malloc(setup_size); 1054 kernel = g_malloc(kernel_size); 1055 fseek(f, 0, SEEK_SET); 1056 if (fread(setup, 1, setup_size, f) != setup_size) { 1057 fprintf(stderr, "fread() failed\n"); 1058 exit(1); 1059 } 1060 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1061 fprintf(stderr, "fread() failed\n"); 1062 exit(1); 1063 } 1064 fclose(f); 1065 1066 /* append dtb to kernel */ 1067 if (dtb_filename) { 1068 if (protocol < 0x209) { 1069 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1070 exit(1); 1071 } 1072 1073 dtb_size = get_image_size(dtb_filename); 1074 if (dtb_size <= 0) { 1075 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1076 dtb_filename, strerror(errno)); 1077 exit(1); 1078 } 1079 1080 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1081 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1082 kernel = g_realloc(kernel, kernel_size); 1083 1084 stq_p(header + 0x250, prot_addr + setup_data_offset); 1085 1086 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1087 setup_data->next = 0; 1088 setup_data->type = cpu_to_le32(SETUP_DTB); 1089 setup_data->len = cpu_to_le32(dtb_size); 1090 1091 load_image_size(dtb_filename, setup_data->data, dtb_size); 1092 } 1093 1094 /* 1095 * If we're starting an encrypted VM, it will be OVMF based, which uses the 1096 * efi stub for booting and doesn't require any values to be placed in the 1097 * kernel header. We therefore don't update the header so the hash of the 1098 * kernel on the other side of the fw_cfg interface matches the hash of the 1099 * file the user passed in. 1100 */ 1101 if (!sev_enabled()) { 1102 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1103 } 1104 1105 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1106 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1107 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1108 sev_load_ctx.kernel_data = (char *)kernel; 1109 sev_load_ctx.kernel_size = kernel_size; 1110 1111 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1112 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1113 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1114 sev_load_ctx.setup_data = (char *)setup; 1115 sev_load_ctx.setup_size = setup_size; 1116 1117 if (sev_enabled()) { 1118 sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); 1119 } 1120 1121 option_rom[nb_option_roms].bootindex = 0; 1122 option_rom[nb_option_roms].name = "linuxboot.bin"; 1123 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1124 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1125 } 1126 nb_option_roms++; 1127 } 1128 1129 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 1130 MemoryRegion *rom_memory, bool isapc_ram_fw) 1131 { 1132 const char *bios_name; 1133 char *filename; 1134 MemoryRegion *bios, *isa_bios; 1135 int bios_size, isa_bios_size; 1136 ssize_t ret; 1137 1138 /* BIOS load */ 1139 bios_name = ms->firmware ?: default_firmware; 1140 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1141 if (filename) { 1142 bios_size = get_image_size(filename); 1143 } else { 1144 bios_size = -1; 1145 } 1146 if (bios_size <= 0 || 1147 (bios_size % 65536) != 0) { 1148 goto bios_error; 1149 } 1150 bios = g_malloc(sizeof(*bios)); 1151 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1152 if (sev_enabled()) { 1153 /* 1154 * The concept of a "reset" simply doesn't exist for 1155 * confidential computing guests, we have to destroy and 1156 * re-launch them instead. So there is no need to register 1157 * the firmware as rom to properly re-initialize on reset. 1158 * Just go for a straight file load instead. 1159 */ 1160 void *ptr = memory_region_get_ram_ptr(bios); 1161 load_image_size(filename, ptr, bios_size); 1162 x86_firmware_configure(ptr, bios_size); 1163 } else { 1164 if (!isapc_ram_fw) { 1165 memory_region_set_readonly(bios, true); 1166 } 1167 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1168 if (ret != 0) { 1169 goto bios_error; 1170 } 1171 } 1172 g_free(filename); 1173 1174 /* map the last 128KB of the BIOS in ISA space */ 1175 isa_bios_size = MIN(bios_size, 128 * KiB); 1176 isa_bios = g_malloc(sizeof(*isa_bios)); 1177 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1178 bios_size - isa_bios_size, isa_bios_size); 1179 memory_region_add_subregion_overlap(rom_memory, 1180 0x100000 - isa_bios_size, 1181 isa_bios, 1182 1); 1183 if (!isapc_ram_fw) { 1184 memory_region_set_readonly(isa_bios, true); 1185 } 1186 1187 /* map all the bios at the top of memory */ 1188 memory_region_add_subregion(rom_memory, 1189 (uint32_t)(-bios_size), 1190 bios); 1191 return; 1192 1193 bios_error: 1194 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1195 exit(1); 1196 } 1197 1198 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1199 { 1200 bool smm_available = false; 1201 1202 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1203 return false; 1204 } 1205 1206 if (tcg_enabled() || qtest_enabled()) { 1207 smm_available = true; 1208 } else if (kvm_enabled()) { 1209 smm_available = kvm_has_smm(); 1210 } 1211 1212 if (smm_available) { 1213 return true; 1214 } 1215 1216 if (x86ms->smm == ON_OFF_AUTO_ON) { 1217 error_report("System Management Mode not supported by this hypervisor."); 1218 exit(1); 1219 } 1220 return false; 1221 } 1222 1223 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1224 void *opaque, Error **errp) 1225 { 1226 X86MachineState *x86ms = X86_MACHINE(obj); 1227 OnOffAuto smm = x86ms->smm; 1228 1229 visit_type_OnOffAuto(v, name, &smm, errp); 1230 } 1231 1232 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1233 void *opaque, Error **errp) 1234 { 1235 X86MachineState *x86ms = X86_MACHINE(obj); 1236 1237 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1238 } 1239 1240 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1241 { 1242 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1243 return false; 1244 } 1245 return true; 1246 } 1247 1248 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1249 void *opaque, Error **errp) 1250 { 1251 X86MachineState *x86ms = X86_MACHINE(obj); 1252 OnOffAuto acpi = x86ms->acpi; 1253 1254 visit_type_OnOffAuto(v, name, &acpi, errp); 1255 } 1256 1257 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1258 void *opaque, Error **errp) 1259 { 1260 X86MachineState *x86ms = X86_MACHINE(obj); 1261 1262 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1263 } 1264 1265 static void x86_machine_get_pit(Object *obj, Visitor *v, const char *name, 1266 void *opaque, Error **errp) 1267 { 1268 X86MachineState *x86ms = X86_MACHINE(obj); 1269 OnOffAuto pit = x86ms->pit; 1270 1271 visit_type_OnOffAuto(v, name, &pit, errp); 1272 } 1273 1274 static void x86_machine_set_pit(Object *obj, Visitor *v, const char *name, 1275 void *opaque, Error **errp) 1276 { 1277 X86MachineState *x86ms = X86_MACHINE(obj);; 1278 1279 visit_type_OnOffAuto(v, name, &x86ms->pit, errp); 1280 } 1281 1282 static void x86_machine_get_pic(Object *obj, Visitor *v, const char *name, 1283 void *opaque, Error **errp) 1284 { 1285 X86MachineState *x86ms = X86_MACHINE(obj); 1286 OnOffAuto pic = x86ms->pic; 1287 1288 visit_type_OnOffAuto(v, name, &pic, errp); 1289 } 1290 1291 static void x86_machine_set_pic(Object *obj, Visitor *v, const char *name, 1292 void *opaque, Error **errp) 1293 { 1294 X86MachineState *x86ms = X86_MACHINE(obj); 1295 1296 visit_type_OnOffAuto(v, name, &x86ms->pic, errp); 1297 } 1298 1299 static char *x86_machine_get_oem_id(Object *obj, Error **errp) 1300 { 1301 X86MachineState *x86ms = X86_MACHINE(obj); 1302 1303 return g_strdup(x86ms->oem_id); 1304 } 1305 1306 static void x86_machine_set_oem_id(Object *obj, const char *value, Error **errp) 1307 { 1308 X86MachineState *x86ms = X86_MACHINE(obj); 1309 size_t len = strlen(value); 1310 1311 if (len > 6) { 1312 error_setg(errp, 1313 "User specified "X86_MACHINE_OEM_ID" value is bigger than " 1314 "6 bytes in size"); 1315 return; 1316 } 1317 1318 strncpy(x86ms->oem_id, value, 6); 1319 } 1320 1321 static char *x86_machine_get_oem_table_id(Object *obj, Error **errp) 1322 { 1323 X86MachineState *x86ms = X86_MACHINE(obj); 1324 1325 return g_strdup(x86ms->oem_table_id); 1326 } 1327 1328 static void x86_machine_set_oem_table_id(Object *obj, const char *value, 1329 Error **errp) 1330 { 1331 X86MachineState *x86ms = X86_MACHINE(obj); 1332 size_t len = strlen(value); 1333 1334 if (len > 8) { 1335 error_setg(errp, 1336 "User specified "X86_MACHINE_OEM_TABLE_ID 1337 " value is bigger than " 1338 "8 bytes in size"); 1339 return; 1340 } 1341 strncpy(x86ms->oem_table_id, value, 8); 1342 } 1343 1344 static void x86_machine_get_bus_lock_ratelimit(Object *obj, Visitor *v, 1345 const char *name, void *opaque, Error **errp) 1346 { 1347 X86MachineState *x86ms = X86_MACHINE(obj); 1348 uint64_t bus_lock_ratelimit = x86ms->bus_lock_ratelimit; 1349 1350 visit_type_uint64(v, name, &bus_lock_ratelimit, errp); 1351 } 1352 1353 static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, 1354 const char *name, void *opaque, Error **errp) 1355 { 1356 X86MachineState *x86ms = X86_MACHINE(obj); 1357 1358 visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); 1359 } 1360 1361 static void machine_get_sgx_epc(Object *obj, Visitor *v, const char *name, 1362 void *opaque, Error **errp) 1363 { 1364 X86MachineState *x86ms = X86_MACHINE(obj); 1365 SgxEPCList *list = x86ms->sgx_epc_list; 1366 1367 visit_type_SgxEPCList(v, name, &list, errp); 1368 } 1369 1370 static void machine_set_sgx_epc(Object *obj, Visitor *v, const char *name, 1371 void *opaque, Error **errp) 1372 { 1373 X86MachineState *x86ms = X86_MACHINE(obj); 1374 SgxEPCList *list; 1375 1376 list = x86ms->sgx_epc_list; 1377 visit_type_SgxEPCList(v, name, &x86ms->sgx_epc_list, errp); 1378 1379 qapi_free_SgxEPCList(list); 1380 } 1381 1382 static void x86_machine_initfn(Object *obj) 1383 { 1384 X86MachineState *x86ms = X86_MACHINE(obj); 1385 1386 x86ms->smm = ON_OFF_AUTO_AUTO; 1387 x86ms->acpi = ON_OFF_AUTO_AUTO; 1388 x86ms->pit = ON_OFF_AUTO_AUTO; 1389 x86ms->pic = ON_OFF_AUTO_AUTO; 1390 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1391 x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1392 x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1393 x86ms->bus_lock_ratelimit = 0; 1394 x86ms->above_4g_mem_start = 4 * GiB; 1395 } 1396 1397 static void x86_machine_class_init(ObjectClass *oc, void *data) 1398 { 1399 MachineClass *mc = MACHINE_CLASS(oc); 1400 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1401 NMIClass *nc = NMI_CLASS(oc); 1402 1403 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1404 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1405 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1406 x86mc->save_tsc_khz = true; 1407 x86mc->fwcfg_dma_enabled = true; 1408 nc->nmi_monitor_handler = x86_nmi; 1409 1410 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1411 x86_machine_get_smm, x86_machine_set_smm, 1412 NULL, NULL); 1413 object_class_property_set_description(oc, X86_MACHINE_SMM, 1414 "Enable SMM"); 1415 1416 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1417 x86_machine_get_acpi, x86_machine_set_acpi, 1418 NULL, NULL); 1419 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1420 "Enable ACPI"); 1421 1422 object_class_property_add(oc, X86_MACHINE_PIT, "OnOffAuto", 1423 x86_machine_get_pit, 1424 x86_machine_set_pit, 1425 NULL, NULL); 1426 object_class_property_set_description(oc, X86_MACHINE_PIT, 1427 "Enable i8254 PIT"); 1428 1429 object_class_property_add(oc, X86_MACHINE_PIC, "OnOffAuto", 1430 x86_machine_get_pic, 1431 x86_machine_set_pic, 1432 NULL, NULL); 1433 object_class_property_set_description(oc, X86_MACHINE_PIC, 1434 "Enable i8259 PIC"); 1435 1436 object_class_property_add_str(oc, X86_MACHINE_OEM_ID, 1437 x86_machine_get_oem_id, 1438 x86_machine_set_oem_id); 1439 object_class_property_set_description(oc, X86_MACHINE_OEM_ID, 1440 "Override the default value of field OEMID " 1441 "in ACPI table header." 1442 "The string may be up to 6 bytes in size"); 1443 1444 1445 object_class_property_add_str(oc, X86_MACHINE_OEM_TABLE_ID, 1446 x86_machine_get_oem_table_id, 1447 x86_machine_set_oem_table_id); 1448 object_class_property_set_description(oc, X86_MACHINE_OEM_TABLE_ID, 1449 "Override the default value of field OEM Table ID " 1450 "in ACPI table header." 1451 "The string may be up to 8 bytes in size"); 1452 1453 object_class_property_add(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, "uint64_t", 1454 x86_machine_get_bus_lock_ratelimit, 1455 x86_machine_set_bus_lock_ratelimit, NULL, NULL); 1456 object_class_property_set_description(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, 1457 "Set the ratelimit for the bus locks acquired in VMs"); 1458 1459 object_class_property_add(oc, "sgx-epc", "SgxEPC", 1460 machine_get_sgx_epc, machine_set_sgx_epc, 1461 NULL, NULL); 1462 object_class_property_set_description(oc, "sgx-epc", 1463 "SGX EPC device"); 1464 } 1465 1466 static const TypeInfo x86_machine_info = { 1467 .name = TYPE_X86_MACHINE, 1468 .parent = TYPE_MACHINE, 1469 .abstract = true, 1470 .instance_size = sizeof(X86MachineState), 1471 .instance_init = x86_machine_initfn, 1472 .class_size = sizeof(X86MachineClass), 1473 .class_init = x86_machine_class_init, 1474 .interfaces = (InterfaceInfo[]) { 1475 { TYPE_NMI }, 1476 { } 1477 }, 1478 }; 1479 1480 static void x86_machine_register_types(void) 1481 { 1482 type_register_static(&x86_machine_info); 1483 } 1484 1485 type_init(x86_machine_register_types) 1486