1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu/datadir.h" 29 #include "qapi/error.h" 30 #include "qapi/qapi-visit-common.h" 31 #include "qapi/clone-visitor.h" 32 #include "qapi/qapi-visit-machine.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/whpx.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/replay.h" 38 #include "sysemu/sysemu.h" 39 #include "sysemu/cpu-timers.h" 40 #include "sysemu/xen.h" 41 #include "trace.h" 42 43 #include "hw/i386/x86.h" 44 #include "target/i386/cpu.h" 45 #include "hw/i386/topology.h" 46 #include "hw/i386/fw_cfg.h" 47 #include "hw/intc/i8259.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "target/i386/sev.h" 50 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "hw/irq.h" 53 #include "hw/nmi.h" 54 #include "hw/loader.h" 55 #include "multiboot.h" 56 #include "elf.h" 57 #include "standard-headers/asm-x86/bootparam.h" 58 #include CONFIG_DEVICES 59 #include "kvm/kvm_i386.h" 60 61 #ifdef CONFIG_XEN_EMU 62 #include "hw/xen/xen.h" 63 #include "hw/i386/kvm/xen_evtchn.h" 64 #endif 65 66 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 67 static size_t pvh_start_addr; 68 69 static void init_topo_info(X86CPUTopoInfo *topo_info, 70 const X86MachineState *x86ms) 71 { 72 MachineState *ms = MACHINE(x86ms); 73 74 topo_info->dies_per_pkg = ms->smp.dies; 75 topo_info->cores_per_die = ms->smp.cores; 76 topo_info->threads_per_core = ms->smp.threads; 77 } 78 79 /* 80 * Calculates initial APIC ID for a specific CPU index 81 * 82 * Currently we need to be able to calculate the APIC ID from the CPU index 83 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 84 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 85 * all CPUs up to max_cpus. 86 */ 87 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 88 unsigned int cpu_index) 89 { 90 X86CPUTopoInfo topo_info; 91 92 init_topo_info(&topo_info, x86ms); 93 94 return x86_apicid_from_cpu_idx(&topo_info, cpu_index); 95 } 96 97 98 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 99 { 100 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 101 102 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 103 goto out; 104 } 105 qdev_realize(DEVICE(cpu), NULL, errp); 106 107 out: 108 object_unref(cpu); 109 } 110 111 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 112 { 113 int i; 114 const CPUArchIdList *possible_cpus; 115 MachineState *ms = MACHINE(x86ms); 116 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 117 118 x86_cpu_set_default_version(default_cpu_version); 119 120 /* 121 * Calculates the limit to CPU APIC ID values 122 * 123 * Limit for the APIC ID value, so that all 124 * CPU APIC IDs are < x86ms->apic_id_limit. 125 * 126 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 127 */ 128 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 129 ms->smp.max_cpus - 1) + 1; 130 131 /* 132 * Can we support APIC ID 255 or higher? With KVM, that requires 133 * both in-kernel lapic and X2APIC userspace API. 134 * 135 * kvm_enabled() must go first to ensure that kvm_* references are 136 * not emitted for the linker to consume (kvm_enabled() is 137 * a literal `0` in configurations where kvm_* aren't defined) 138 */ 139 if (kvm_enabled() && x86ms->apic_id_limit > 255 && 140 (!kvm_irqchip_in_kernel() || !kvm_enable_x2apic())) { 141 error_report("current -smp configuration requires kernel " 142 "irqchip and X2APIC API support."); 143 exit(EXIT_FAILURE); 144 } 145 146 if (kvm_enabled()) { 147 kvm_set_max_apic_id(x86ms->apic_id_limit); 148 } 149 150 possible_cpus = mc->possible_cpu_arch_ids(ms); 151 for (i = 0; i < ms->smp.cpus; i++) { 152 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 153 } 154 } 155 156 void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) 157 { 158 MC146818RtcState *rtc = MC146818_RTC(s); 159 160 if (cpus_count > 0xff) { 161 /* 162 * If the number of CPUs can't be represented in 8 bits, the 163 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 164 * to make old BIOSes fail more predictably. 165 */ 166 mc146818rtc_set_cmos_data(rtc, 0x5f, 0); 167 } else { 168 mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); 169 } 170 } 171 172 static int x86_apic_cmp(const void *a, const void *b) 173 { 174 CPUArchId *apic_a = (CPUArchId *)a; 175 CPUArchId *apic_b = (CPUArchId *)b; 176 177 return apic_a->arch_id - apic_b->arch_id; 178 } 179 180 /* 181 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 182 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 183 * entry corresponding to CPU's apic_id returns NULL. 184 */ 185 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 186 { 187 CPUArchId apic_id, *found_cpu; 188 189 apic_id.arch_id = id; 190 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 191 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 192 x86_apic_cmp); 193 if (found_cpu && idx) { 194 *idx = found_cpu - ms->possible_cpus->cpus; 195 } 196 return found_cpu; 197 } 198 199 void x86_cpu_plug(HotplugHandler *hotplug_dev, 200 DeviceState *dev, Error **errp) 201 { 202 CPUArchId *found_cpu; 203 Error *local_err = NULL; 204 X86CPU *cpu = X86_CPU(dev); 205 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 206 207 if (x86ms->acpi_dev) { 208 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 209 if (local_err) { 210 goto out; 211 } 212 } 213 214 /* increment the number of CPUs */ 215 x86ms->boot_cpus++; 216 if (x86ms->rtc) { 217 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 218 } 219 if (x86ms->fw_cfg) { 220 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 221 } 222 223 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 224 found_cpu->cpu = OBJECT(dev); 225 out: 226 error_propagate(errp, local_err); 227 } 228 229 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 230 DeviceState *dev, Error **errp) 231 { 232 int idx = -1; 233 X86CPU *cpu = X86_CPU(dev); 234 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 235 236 if (!x86ms->acpi_dev) { 237 error_setg(errp, "CPU hot unplug not supported without ACPI"); 238 return; 239 } 240 241 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 242 assert(idx != -1); 243 if (idx == 0) { 244 error_setg(errp, "Boot CPU is unpluggable"); 245 return; 246 } 247 248 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 249 errp); 250 } 251 252 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 253 DeviceState *dev, Error **errp) 254 { 255 CPUArchId *found_cpu; 256 Error *local_err = NULL; 257 X86CPU *cpu = X86_CPU(dev); 258 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 259 260 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 261 if (local_err) { 262 goto out; 263 } 264 265 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 266 found_cpu->cpu = NULL; 267 qdev_unrealize(dev); 268 269 /* decrement the number of CPUs */ 270 x86ms->boot_cpus--; 271 /* Update the number of CPUs in CMOS */ 272 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 273 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 274 out: 275 error_propagate(errp, local_err); 276 } 277 278 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 279 DeviceState *dev, Error **errp) 280 { 281 int idx; 282 CPUState *cs; 283 CPUArchId *cpu_slot; 284 X86CPUTopoIDs topo_ids; 285 X86CPU *cpu = X86_CPU(dev); 286 CPUX86State *env = &cpu->env; 287 MachineState *ms = MACHINE(hotplug_dev); 288 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 289 unsigned int smp_cores = ms->smp.cores; 290 unsigned int smp_threads = ms->smp.threads; 291 X86CPUTopoInfo topo_info; 292 293 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 294 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 295 ms->cpu_type); 296 return; 297 } 298 299 if (x86ms->acpi_dev) { 300 Error *local_err = NULL; 301 302 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 303 &local_err); 304 if (local_err) { 305 error_propagate(errp, local_err); 306 return; 307 } 308 } 309 310 init_topo_info(&topo_info, x86ms); 311 312 env->nr_dies = ms->smp.dies; 313 314 /* 315 * If APIC ID is not set, 316 * set it based on socket/die/core/thread properties. 317 */ 318 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 319 int max_socket = (ms->smp.max_cpus - 1) / 320 smp_threads / smp_cores / ms->smp.dies; 321 322 /* 323 * die-id was optional in QEMU 4.0 and older, so keep it optional 324 * if there's only one die per socket. 325 */ 326 if (cpu->die_id < 0 && ms->smp.dies == 1) { 327 cpu->die_id = 0; 328 } 329 330 if (cpu->socket_id < 0) { 331 error_setg(errp, "CPU socket-id is not set"); 332 return; 333 } else if (cpu->socket_id > max_socket) { 334 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 335 cpu->socket_id, max_socket); 336 return; 337 } 338 if (cpu->die_id < 0) { 339 error_setg(errp, "CPU die-id is not set"); 340 return; 341 } else if (cpu->die_id > ms->smp.dies - 1) { 342 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 343 cpu->die_id, ms->smp.dies - 1); 344 return; 345 } 346 if (cpu->core_id < 0) { 347 error_setg(errp, "CPU core-id is not set"); 348 return; 349 } else if (cpu->core_id > (smp_cores - 1)) { 350 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 351 cpu->core_id, smp_cores - 1); 352 return; 353 } 354 if (cpu->thread_id < 0) { 355 error_setg(errp, "CPU thread-id is not set"); 356 return; 357 } else if (cpu->thread_id > (smp_threads - 1)) { 358 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 359 cpu->thread_id, smp_threads - 1); 360 return; 361 } 362 363 topo_ids.pkg_id = cpu->socket_id; 364 topo_ids.die_id = cpu->die_id; 365 topo_ids.core_id = cpu->core_id; 366 topo_ids.smt_id = cpu->thread_id; 367 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 368 } 369 370 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 371 if (!cpu_slot) { 372 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 373 error_setg(errp, 374 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 375 " APIC ID %" PRIu32 ", valid index range 0:%d", 376 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 377 cpu->apic_id, ms->possible_cpus->len - 1); 378 return; 379 } 380 381 if (cpu_slot->cpu) { 382 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 383 idx, cpu->apic_id); 384 return; 385 } 386 387 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 388 * so that machine_query_hotpluggable_cpus would show correct values 389 */ 390 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 391 * once -smp refactoring is complete and there will be CPU private 392 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 393 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 394 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 395 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 396 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 397 topo_ids.pkg_id); 398 return; 399 } 400 cpu->socket_id = topo_ids.pkg_id; 401 402 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 403 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 404 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 405 return; 406 } 407 cpu->die_id = topo_ids.die_id; 408 409 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 410 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 411 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 412 topo_ids.core_id); 413 return; 414 } 415 cpu->core_id = topo_ids.core_id; 416 417 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 418 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 419 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 420 topo_ids.smt_id); 421 return; 422 } 423 cpu->thread_id = topo_ids.smt_id; 424 425 /* 426 * kvm_enabled() must go first to ensure that kvm_* references are 427 * not emitted for the linker to consume (kvm_enabled() is 428 * a literal `0` in configurations where kvm_* aren't defined) 429 */ 430 if (kvm_enabled() && hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 431 !kvm_hv_vpindex_settable()) { 432 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 433 return; 434 } 435 436 cs = CPU(cpu); 437 cs->cpu_index = idx; 438 439 numa_cpu_pre_plug(cpu_slot, dev, errp); 440 } 441 442 CpuInstanceProperties 443 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 444 { 445 MachineClass *mc = MACHINE_GET_CLASS(ms); 446 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 447 448 assert(cpu_index < possible_cpus->len); 449 return possible_cpus->cpus[cpu_index].props; 450 } 451 452 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 453 { 454 X86CPUTopoIDs topo_ids; 455 X86MachineState *x86ms = X86_MACHINE(ms); 456 X86CPUTopoInfo topo_info; 457 458 init_topo_info(&topo_info, x86ms); 459 460 assert(idx < ms->possible_cpus->len); 461 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 462 &topo_info, &topo_ids); 463 return topo_ids.pkg_id % ms->numa_state->num_nodes; 464 } 465 466 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 467 { 468 X86MachineState *x86ms = X86_MACHINE(ms); 469 unsigned int max_cpus = ms->smp.max_cpus; 470 X86CPUTopoInfo topo_info; 471 int i; 472 473 if (ms->possible_cpus) { 474 /* 475 * make sure that max_cpus hasn't changed since the first use, i.e. 476 * -smp hasn't been parsed after it 477 */ 478 assert(ms->possible_cpus->len == max_cpus); 479 return ms->possible_cpus; 480 } 481 482 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 483 sizeof(CPUArchId) * max_cpus); 484 ms->possible_cpus->len = max_cpus; 485 486 init_topo_info(&topo_info, x86ms); 487 488 for (i = 0; i < ms->possible_cpus->len; i++) { 489 X86CPUTopoIDs topo_ids; 490 491 ms->possible_cpus->cpus[i].type = ms->cpu_type; 492 ms->possible_cpus->cpus[i].vcpus_count = 1; 493 ms->possible_cpus->cpus[i].arch_id = 494 x86_cpu_apic_id_from_index(x86ms, i); 495 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 496 &topo_info, &topo_ids); 497 ms->possible_cpus->cpus[i].props.has_socket_id = true; 498 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 499 if (ms->smp.dies > 1) { 500 ms->possible_cpus->cpus[i].props.has_die_id = true; 501 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 502 } 503 ms->possible_cpus->cpus[i].props.has_core_id = true; 504 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 505 ms->possible_cpus->cpus[i].props.has_thread_id = true; 506 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 507 } 508 return ms->possible_cpus; 509 } 510 511 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 512 { 513 /* cpu index isn't used */ 514 CPUState *cs; 515 516 CPU_FOREACH(cs) { 517 X86CPU *cpu = X86_CPU(cs); 518 519 if (!cpu->apic_state) { 520 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 521 } else { 522 apic_deliver_nmi(cpu->apic_state); 523 } 524 } 525 } 526 527 static long get_file_size(FILE *f) 528 { 529 long where, size; 530 531 /* XXX: on Unix systems, using fstat() probably makes more sense */ 532 533 where = ftell(f); 534 fseek(f, 0, SEEK_END); 535 size = ftell(f); 536 fseek(f, where, SEEK_SET); 537 538 return size; 539 } 540 541 /* TSC handling */ 542 uint64_t cpu_get_tsc(CPUX86State *env) 543 { 544 return cpus_get_elapsed_ticks(); 545 } 546 547 /* IRQ handling */ 548 static void pic_irq_request(void *opaque, int irq, int level) 549 { 550 CPUState *cs = first_cpu; 551 X86CPU *cpu = X86_CPU(cs); 552 553 trace_x86_pic_interrupt(irq, level); 554 if (cpu->apic_state && !kvm_irqchip_in_kernel() && 555 !whpx_apic_in_platform()) { 556 CPU_FOREACH(cs) { 557 cpu = X86_CPU(cs); 558 if (apic_accept_pic_intr(cpu->apic_state)) { 559 apic_deliver_pic_intr(cpu->apic_state, level); 560 } 561 } 562 } else { 563 if (level) { 564 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 565 } else { 566 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 567 } 568 } 569 } 570 571 qemu_irq x86_allocate_cpu_irq(void) 572 { 573 return qemu_allocate_irq(pic_irq_request, NULL, 0); 574 } 575 576 int cpu_get_pic_interrupt(CPUX86State *env) 577 { 578 X86CPU *cpu = env_archcpu(env); 579 int intno; 580 581 if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { 582 intno = apic_get_interrupt(cpu->apic_state); 583 if (intno >= 0) { 584 return intno; 585 } 586 /* read the irq from the PIC */ 587 if (!apic_accept_pic_intr(cpu->apic_state)) { 588 return -1; 589 } 590 } 591 592 intno = pic_read_irq(isa_pic); 593 return intno; 594 } 595 596 DeviceState *cpu_get_current_apic(void) 597 { 598 if (current_cpu) { 599 X86CPU *cpu = X86_CPU(current_cpu); 600 return cpu->apic_state; 601 } else { 602 return NULL; 603 } 604 } 605 606 void gsi_handler(void *opaque, int n, int level) 607 { 608 GSIState *s = opaque; 609 610 trace_x86_gsi_interrupt(n, level); 611 switch (n) { 612 case 0 ... ISA_NUM_IRQS - 1: 613 if (s->i8259_irq[n]) { 614 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 615 qemu_set_irq(s->i8259_irq[n], level); 616 } 617 /* fall through */ 618 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 619 #ifdef CONFIG_XEN_EMU 620 /* 621 * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC 622 * routing actually works properly under Xen). And then to 623 * *either* the PIRQ handling or the I/OAPIC depending on 624 * whether the former wants it. 625 */ 626 if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { 627 break; 628 } 629 #endif 630 qemu_set_irq(s->ioapic_irq[n], level); 631 break; 632 case IO_APIC_SECONDARY_IRQBASE 633 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 634 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 635 break; 636 } 637 } 638 639 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 640 { 641 DeviceState *dev; 642 SysBusDevice *d; 643 unsigned int i; 644 645 assert(parent_name); 646 if (kvm_ioapic_in_kernel()) { 647 dev = qdev_new(TYPE_KVM_IOAPIC); 648 } else { 649 dev = qdev_new(TYPE_IOAPIC); 650 } 651 object_property_add_child(object_resolve_path(parent_name, NULL), 652 "ioapic", OBJECT(dev)); 653 d = SYS_BUS_DEVICE(dev); 654 sysbus_realize_and_unref(d, &error_fatal); 655 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 656 657 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 658 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 659 } 660 } 661 662 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 663 { 664 DeviceState *dev; 665 SysBusDevice *d; 666 unsigned int i; 667 668 dev = qdev_new(TYPE_IOAPIC); 669 d = SYS_BUS_DEVICE(dev); 670 sysbus_realize_and_unref(d, &error_fatal); 671 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 672 673 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 674 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 675 } 676 return dev; 677 } 678 679 struct setup_data { 680 uint64_t next; 681 uint32_t type; 682 uint32_t len; 683 uint8_t data[]; 684 } __attribute__((packed)); 685 686 687 /* 688 * The entry point into the kernel for PVH boot is different from 689 * the native entry point. The PVH entry is defined by the x86/HVM 690 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 691 * 692 * This function is passed to load_elf() when it is called from 693 * load_elfboot() which then additionally checks for an ELF Note of 694 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 695 * parse the PVH entry address from the ELF Note. 696 * 697 * Due to trickery in elf_opts.h, load_elf() is actually available as 698 * load_elf32() or load_elf64() and this routine needs to be able 699 * to deal with being called as 32 or 64 bit. 700 * 701 * The address of the PVH entry point is saved to the 'pvh_start_addr' 702 * global variable. (although the entry point is 32-bit, the kernel 703 * binary can be either 32-bit or 64-bit). 704 */ 705 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 706 { 707 size_t *elf_note_data_addr; 708 709 /* Check if ELF Note header passed in is valid */ 710 if (arg1 == NULL) { 711 return 0; 712 } 713 714 if (is64) { 715 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 716 uint64_t nhdr_size64 = sizeof(struct elf64_note); 717 uint64_t phdr_align = *(uint64_t *)arg2; 718 uint64_t nhdr_namesz = nhdr64->n_namesz; 719 720 elf_note_data_addr = 721 ((void *)nhdr64) + nhdr_size64 + 722 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 723 724 pvh_start_addr = *elf_note_data_addr; 725 } else { 726 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 727 uint32_t nhdr_size32 = sizeof(struct elf32_note); 728 uint32_t phdr_align = *(uint32_t *)arg2; 729 uint32_t nhdr_namesz = nhdr32->n_namesz; 730 731 elf_note_data_addr = 732 ((void *)nhdr32) + nhdr_size32 + 733 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 734 735 pvh_start_addr = *(uint32_t *)elf_note_data_addr; 736 } 737 738 return pvh_start_addr; 739 } 740 741 static bool load_elfboot(const char *kernel_filename, 742 int kernel_file_size, 743 uint8_t *header, 744 size_t pvh_xen_start_addr, 745 FWCfgState *fw_cfg) 746 { 747 uint32_t flags = 0; 748 uint32_t mh_load_addr = 0; 749 uint32_t elf_kernel_size = 0; 750 uint64_t elf_entry; 751 uint64_t elf_low, elf_high; 752 int kernel_size; 753 754 if (ldl_p(header) != 0x464c457f) { 755 return false; /* no elfboot */ 756 } 757 758 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 759 flags = elf_is64 ? 760 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 761 762 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 763 error_report("elfboot unsupported flags = %x", flags); 764 exit(1); 765 } 766 767 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 768 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 769 NULL, &elf_note_type, &elf_entry, 770 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 771 0, 0); 772 773 if (kernel_size < 0) { 774 error_report("Error while loading elf kernel"); 775 exit(1); 776 } 777 mh_load_addr = elf_low; 778 elf_kernel_size = elf_high - elf_low; 779 780 if (pvh_start_addr == 0) { 781 error_report("Error loading uncompressed kernel without PVH ELF Note"); 782 exit(1); 783 } 784 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 785 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 786 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 787 788 return true; 789 } 790 791 void x86_load_linux(X86MachineState *x86ms, 792 FWCfgState *fw_cfg, 793 int acpi_data_size, 794 bool pvh_enabled) 795 { 796 bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; 797 uint16_t protocol; 798 int setup_size, kernel_size, cmdline_size; 799 int dtb_size, setup_data_offset; 800 uint32_t initrd_max; 801 uint8_t header[8192], *setup, *kernel; 802 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 803 FILE *f; 804 char *vmode; 805 MachineState *machine = MACHINE(x86ms); 806 struct setup_data *setup_data; 807 const char *kernel_filename = machine->kernel_filename; 808 const char *initrd_filename = machine->initrd_filename; 809 const char *dtb_filename = machine->dtb; 810 const char *kernel_cmdline = machine->kernel_cmdline; 811 SevKernelLoaderContext sev_load_ctx = {}; 812 813 /* Align to 16 bytes as a paranoia measure */ 814 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; 815 816 /* load the kernel header */ 817 f = fopen(kernel_filename, "rb"); 818 if (!f) { 819 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 820 kernel_filename, strerror(errno)); 821 exit(1); 822 } 823 824 kernel_size = get_file_size(f); 825 if (!kernel_size || 826 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 827 MIN(ARRAY_SIZE(header), kernel_size)) { 828 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 829 kernel_filename, strerror(errno)); 830 exit(1); 831 } 832 833 /* kernel protocol version */ 834 if (ldl_p(header + 0x202) == 0x53726448) { 835 protocol = lduw_p(header + 0x206); 836 } else { 837 /* 838 * This could be a multiboot kernel. If it is, let's stop treating it 839 * like a Linux kernel. 840 * Note: some multiboot images could be in the ELF format (the same of 841 * PVH), so we try multiboot first since we check the multiboot magic 842 * header before to load it. 843 */ 844 if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, 845 kernel_cmdline, kernel_size, header)) { 846 return; 847 } 848 /* 849 * Check if the file is an uncompressed kernel file (ELF) and load it, 850 * saving the PVH entry point used by the x86/HVM direct boot ABI. 851 * If load_elfboot() is successful, populate the fw_cfg info. 852 */ 853 if (pvh_enabled && 854 load_elfboot(kernel_filename, kernel_size, 855 header, pvh_start_addr, fw_cfg)) { 856 fclose(f); 857 858 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 859 strlen(kernel_cmdline) + 1); 860 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 861 862 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 863 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 864 header, sizeof(header)); 865 866 /* load initrd */ 867 if (initrd_filename) { 868 GMappedFile *mapped_file; 869 gsize initrd_size; 870 gchar *initrd_data; 871 GError *gerr = NULL; 872 873 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 874 if (!mapped_file) { 875 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 876 initrd_filename, gerr->message); 877 exit(1); 878 } 879 x86ms->initrd_mapped_file = mapped_file; 880 881 initrd_data = g_mapped_file_get_contents(mapped_file); 882 initrd_size = g_mapped_file_get_length(mapped_file); 883 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 884 if (initrd_size >= initrd_max) { 885 fprintf(stderr, "qemu: initrd is too large, cannot support." 886 "(max: %"PRIu32", need %"PRId64")\n", 887 initrd_max, (uint64_t)initrd_size); 888 exit(1); 889 } 890 891 initrd_addr = (initrd_max - initrd_size) & ~4095; 892 893 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 894 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 895 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 896 initrd_size); 897 } 898 899 option_rom[nb_option_roms].bootindex = 0; 900 option_rom[nb_option_roms].name = "pvh.bin"; 901 nb_option_roms++; 902 903 return; 904 } 905 protocol = 0; 906 } 907 908 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 909 /* Low kernel */ 910 real_addr = 0x90000; 911 cmdline_addr = 0x9a000 - cmdline_size; 912 prot_addr = 0x10000; 913 } else if (protocol < 0x202) { 914 /* High but ancient kernel */ 915 real_addr = 0x90000; 916 cmdline_addr = 0x9a000 - cmdline_size; 917 prot_addr = 0x100000; 918 } else { 919 /* High and recent kernel */ 920 real_addr = 0x10000; 921 cmdline_addr = 0x20000; 922 prot_addr = 0x100000; 923 } 924 925 /* highest address for loading the initrd */ 926 if (protocol >= 0x20c && 927 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 928 /* 929 * Linux has supported initrd up to 4 GB for a very long time (2007, 930 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 931 * though it only sets initrd_max to 2 GB to "work around bootloader 932 * bugs". Luckily, QEMU firmware(which does something like bootloader) 933 * has supported this. 934 * 935 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 936 * be loaded into any address. 937 * 938 * In addition, initrd_max is uint32_t simply because QEMU doesn't 939 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 940 * field). 941 * 942 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 943 */ 944 initrd_max = UINT32_MAX; 945 } else if (protocol >= 0x203) { 946 initrd_max = ldl_p(header + 0x22c); 947 } else { 948 initrd_max = 0x37ffffff; 949 } 950 951 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 952 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 953 } 954 955 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 956 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); 957 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 958 sev_load_ctx.cmdline_data = (char *)kernel_cmdline; 959 sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; 960 961 if (protocol >= 0x202) { 962 stl_p(header + 0x228, cmdline_addr); 963 } else { 964 stw_p(header + 0x20, 0xA33F); 965 stw_p(header + 0x22, cmdline_addr - real_addr); 966 } 967 968 /* handle vga= parameter */ 969 vmode = strstr(kernel_cmdline, "vga="); 970 if (vmode) { 971 unsigned int video_mode; 972 const char *end; 973 int ret; 974 /* skip "vga=" */ 975 vmode += 4; 976 if (!strncmp(vmode, "normal", 6)) { 977 video_mode = 0xffff; 978 } else if (!strncmp(vmode, "ext", 3)) { 979 video_mode = 0xfffe; 980 } else if (!strncmp(vmode, "ask", 3)) { 981 video_mode = 0xfffd; 982 } else { 983 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 984 if (ret != 0 || (*end && *end != ' ')) { 985 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 986 exit(1); 987 } 988 } 989 stw_p(header + 0x1fa, video_mode); 990 } 991 992 /* loader type */ 993 /* 994 * High nybble = B reserved for QEMU; low nybble is revision number. 995 * If this code is substantially changed, you may want to consider 996 * incrementing the revision. 997 */ 998 if (protocol >= 0x200) { 999 header[0x210] = 0xB0; 1000 } 1001 /* heap */ 1002 if (protocol >= 0x201) { 1003 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1004 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 1005 } 1006 1007 /* load initrd */ 1008 if (initrd_filename) { 1009 GMappedFile *mapped_file; 1010 gsize initrd_size; 1011 gchar *initrd_data; 1012 GError *gerr = NULL; 1013 1014 if (protocol < 0x200) { 1015 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1016 exit(1); 1017 } 1018 1019 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1020 if (!mapped_file) { 1021 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1022 initrd_filename, gerr->message); 1023 exit(1); 1024 } 1025 x86ms->initrd_mapped_file = mapped_file; 1026 1027 initrd_data = g_mapped_file_get_contents(mapped_file); 1028 initrd_size = g_mapped_file_get_length(mapped_file); 1029 if (initrd_size >= initrd_max) { 1030 fprintf(stderr, "qemu: initrd is too large, cannot support." 1031 "(max: %"PRIu32", need %"PRId64")\n", 1032 initrd_max, (uint64_t)initrd_size); 1033 exit(1); 1034 } 1035 1036 initrd_addr = (initrd_max - initrd_size) & ~4095; 1037 1038 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1039 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1040 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1041 sev_load_ctx.initrd_data = initrd_data; 1042 sev_load_ctx.initrd_size = initrd_size; 1043 1044 stl_p(header + 0x218, initrd_addr); 1045 stl_p(header + 0x21c, initrd_size); 1046 } 1047 1048 /* load kernel and setup */ 1049 setup_size = header[0x1f1]; 1050 if (setup_size == 0) { 1051 setup_size = 4; 1052 } 1053 setup_size = (setup_size + 1) * 512; 1054 if (setup_size > kernel_size) { 1055 fprintf(stderr, "qemu: invalid kernel header\n"); 1056 exit(1); 1057 } 1058 kernel_size -= setup_size; 1059 1060 setup = g_malloc(setup_size); 1061 kernel = g_malloc(kernel_size); 1062 fseek(f, 0, SEEK_SET); 1063 if (fread(setup, 1, setup_size, f) != setup_size) { 1064 fprintf(stderr, "fread() failed\n"); 1065 exit(1); 1066 } 1067 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1068 fprintf(stderr, "fread() failed\n"); 1069 exit(1); 1070 } 1071 fclose(f); 1072 1073 /* append dtb to kernel */ 1074 if (dtb_filename) { 1075 if (protocol < 0x209) { 1076 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1077 exit(1); 1078 } 1079 1080 dtb_size = get_image_size(dtb_filename); 1081 if (dtb_size <= 0) { 1082 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1083 dtb_filename, strerror(errno)); 1084 exit(1); 1085 } 1086 1087 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1088 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1089 kernel = g_realloc(kernel, kernel_size); 1090 1091 stq_p(header + 0x250, prot_addr + setup_data_offset); 1092 1093 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1094 setup_data->next = 0; 1095 setup_data->type = cpu_to_le32(SETUP_DTB); 1096 setup_data->len = cpu_to_le32(dtb_size); 1097 1098 load_image_size(dtb_filename, setup_data->data, dtb_size); 1099 } 1100 1101 /* 1102 * If we're starting an encrypted VM, it will be OVMF based, which uses the 1103 * efi stub for booting and doesn't require any values to be placed in the 1104 * kernel header. We therefore don't update the header so the hash of the 1105 * kernel on the other side of the fw_cfg interface matches the hash of the 1106 * file the user passed in. 1107 */ 1108 if (!sev_enabled()) { 1109 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1110 } 1111 1112 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1113 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1114 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1115 sev_load_ctx.kernel_data = (char *)kernel; 1116 sev_load_ctx.kernel_size = kernel_size; 1117 1118 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1119 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1120 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1121 sev_load_ctx.setup_data = (char *)setup; 1122 sev_load_ctx.setup_size = setup_size; 1123 1124 if (sev_enabled()) { 1125 sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); 1126 } 1127 1128 option_rom[nb_option_roms].bootindex = 0; 1129 option_rom[nb_option_roms].name = "linuxboot.bin"; 1130 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1131 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1132 } 1133 nb_option_roms++; 1134 } 1135 1136 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 1137 MemoryRegion *rom_memory, bool isapc_ram_fw) 1138 { 1139 const char *bios_name; 1140 char *filename; 1141 MemoryRegion *bios, *isa_bios; 1142 int bios_size, isa_bios_size; 1143 ssize_t ret; 1144 1145 /* BIOS load */ 1146 bios_name = ms->firmware ?: default_firmware; 1147 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1148 if (filename) { 1149 bios_size = get_image_size(filename); 1150 } else { 1151 bios_size = -1; 1152 } 1153 if (bios_size <= 0 || 1154 (bios_size % 65536) != 0) { 1155 goto bios_error; 1156 } 1157 bios = g_malloc(sizeof(*bios)); 1158 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1159 if (sev_enabled()) { 1160 /* 1161 * The concept of a "reset" simply doesn't exist for 1162 * confidential computing guests, we have to destroy and 1163 * re-launch them instead. So there is no need to register 1164 * the firmware as rom to properly re-initialize on reset. 1165 * Just go for a straight file load instead. 1166 */ 1167 void *ptr = memory_region_get_ram_ptr(bios); 1168 load_image_size(filename, ptr, bios_size); 1169 x86_firmware_configure(ptr, bios_size); 1170 } else { 1171 if (!isapc_ram_fw) { 1172 memory_region_set_readonly(bios, true); 1173 } 1174 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1175 if (ret != 0) { 1176 goto bios_error; 1177 } 1178 } 1179 g_free(filename); 1180 1181 /* map the last 128KB of the BIOS in ISA space */ 1182 isa_bios_size = MIN(bios_size, 128 * KiB); 1183 isa_bios = g_malloc(sizeof(*isa_bios)); 1184 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1185 bios_size - isa_bios_size, isa_bios_size); 1186 memory_region_add_subregion_overlap(rom_memory, 1187 0x100000 - isa_bios_size, 1188 isa_bios, 1189 1); 1190 if (!isapc_ram_fw) { 1191 memory_region_set_readonly(isa_bios, true); 1192 } 1193 1194 /* map all the bios at the top of memory */ 1195 memory_region_add_subregion(rom_memory, 1196 (uint32_t)(-bios_size), 1197 bios); 1198 return; 1199 1200 bios_error: 1201 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1202 exit(1); 1203 } 1204 1205 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1206 { 1207 bool smm_available = false; 1208 1209 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1210 return false; 1211 } 1212 1213 if (tcg_enabled() || qtest_enabled()) { 1214 smm_available = true; 1215 } else if (kvm_enabled()) { 1216 smm_available = kvm_has_smm(); 1217 } 1218 1219 if (smm_available) { 1220 return true; 1221 } 1222 1223 if (x86ms->smm == ON_OFF_AUTO_ON) { 1224 error_report("System Management Mode not supported by this hypervisor."); 1225 exit(1); 1226 } 1227 return false; 1228 } 1229 1230 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1231 void *opaque, Error **errp) 1232 { 1233 X86MachineState *x86ms = X86_MACHINE(obj); 1234 OnOffAuto smm = x86ms->smm; 1235 1236 visit_type_OnOffAuto(v, name, &smm, errp); 1237 } 1238 1239 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1240 void *opaque, Error **errp) 1241 { 1242 X86MachineState *x86ms = X86_MACHINE(obj); 1243 1244 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1245 } 1246 1247 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1248 { 1249 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1250 return false; 1251 } 1252 return true; 1253 } 1254 1255 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1256 void *opaque, Error **errp) 1257 { 1258 X86MachineState *x86ms = X86_MACHINE(obj); 1259 OnOffAuto acpi = x86ms->acpi; 1260 1261 visit_type_OnOffAuto(v, name, &acpi, errp); 1262 } 1263 1264 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1265 void *opaque, Error **errp) 1266 { 1267 X86MachineState *x86ms = X86_MACHINE(obj); 1268 1269 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1270 } 1271 1272 static void x86_machine_get_pit(Object *obj, Visitor *v, const char *name, 1273 void *opaque, Error **errp) 1274 { 1275 X86MachineState *x86ms = X86_MACHINE(obj); 1276 OnOffAuto pit = x86ms->pit; 1277 1278 visit_type_OnOffAuto(v, name, &pit, errp); 1279 } 1280 1281 static void x86_machine_set_pit(Object *obj, Visitor *v, const char *name, 1282 void *opaque, Error **errp) 1283 { 1284 X86MachineState *x86ms = X86_MACHINE(obj);; 1285 1286 visit_type_OnOffAuto(v, name, &x86ms->pit, errp); 1287 } 1288 1289 static void x86_machine_get_pic(Object *obj, Visitor *v, const char *name, 1290 void *opaque, Error **errp) 1291 { 1292 X86MachineState *x86ms = X86_MACHINE(obj); 1293 OnOffAuto pic = x86ms->pic; 1294 1295 visit_type_OnOffAuto(v, name, &pic, errp); 1296 } 1297 1298 static void x86_machine_set_pic(Object *obj, Visitor *v, const char *name, 1299 void *opaque, Error **errp) 1300 { 1301 X86MachineState *x86ms = X86_MACHINE(obj); 1302 1303 visit_type_OnOffAuto(v, name, &x86ms->pic, errp); 1304 } 1305 1306 static char *x86_machine_get_oem_id(Object *obj, Error **errp) 1307 { 1308 X86MachineState *x86ms = X86_MACHINE(obj); 1309 1310 return g_strdup(x86ms->oem_id); 1311 } 1312 1313 static void x86_machine_set_oem_id(Object *obj, const char *value, Error **errp) 1314 { 1315 X86MachineState *x86ms = X86_MACHINE(obj); 1316 size_t len = strlen(value); 1317 1318 if (len > 6) { 1319 error_setg(errp, 1320 "User specified "X86_MACHINE_OEM_ID" value is bigger than " 1321 "6 bytes in size"); 1322 return; 1323 } 1324 1325 strncpy(x86ms->oem_id, value, 6); 1326 } 1327 1328 static char *x86_machine_get_oem_table_id(Object *obj, Error **errp) 1329 { 1330 X86MachineState *x86ms = X86_MACHINE(obj); 1331 1332 return g_strdup(x86ms->oem_table_id); 1333 } 1334 1335 static void x86_machine_set_oem_table_id(Object *obj, const char *value, 1336 Error **errp) 1337 { 1338 X86MachineState *x86ms = X86_MACHINE(obj); 1339 size_t len = strlen(value); 1340 1341 if (len > 8) { 1342 error_setg(errp, 1343 "User specified "X86_MACHINE_OEM_TABLE_ID 1344 " value is bigger than " 1345 "8 bytes in size"); 1346 return; 1347 } 1348 strncpy(x86ms->oem_table_id, value, 8); 1349 } 1350 1351 static void x86_machine_get_bus_lock_ratelimit(Object *obj, Visitor *v, 1352 const char *name, void *opaque, Error **errp) 1353 { 1354 X86MachineState *x86ms = X86_MACHINE(obj); 1355 uint64_t bus_lock_ratelimit = x86ms->bus_lock_ratelimit; 1356 1357 visit_type_uint64(v, name, &bus_lock_ratelimit, errp); 1358 } 1359 1360 static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, 1361 const char *name, void *opaque, Error **errp) 1362 { 1363 X86MachineState *x86ms = X86_MACHINE(obj); 1364 1365 visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); 1366 } 1367 1368 static void machine_get_sgx_epc(Object *obj, Visitor *v, const char *name, 1369 void *opaque, Error **errp) 1370 { 1371 X86MachineState *x86ms = X86_MACHINE(obj); 1372 SgxEPCList *list = x86ms->sgx_epc_list; 1373 1374 visit_type_SgxEPCList(v, name, &list, errp); 1375 } 1376 1377 static void machine_set_sgx_epc(Object *obj, Visitor *v, const char *name, 1378 void *opaque, Error **errp) 1379 { 1380 X86MachineState *x86ms = X86_MACHINE(obj); 1381 SgxEPCList *list; 1382 1383 list = x86ms->sgx_epc_list; 1384 visit_type_SgxEPCList(v, name, &x86ms->sgx_epc_list, errp); 1385 1386 qapi_free_SgxEPCList(list); 1387 } 1388 1389 static void x86_machine_initfn(Object *obj) 1390 { 1391 X86MachineState *x86ms = X86_MACHINE(obj); 1392 1393 x86ms->smm = ON_OFF_AUTO_AUTO; 1394 x86ms->acpi = ON_OFF_AUTO_AUTO; 1395 x86ms->pit = ON_OFF_AUTO_AUTO; 1396 x86ms->pic = ON_OFF_AUTO_AUTO; 1397 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1398 x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1399 x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1400 x86ms->bus_lock_ratelimit = 0; 1401 x86ms->above_4g_mem_start = 4 * GiB; 1402 } 1403 1404 static void x86_machine_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1408 NMIClass *nc = NMI_CLASS(oc); 1409 1410 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1411 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1412 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1413 x86mc->save_tsc_khz = true; 1414 x86mc->fwcfg_dma_enabled = true; 1415 nc->nmi_monitor_handler = x86_nmi; 1416 1417 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1418 x86_machine_get_smm, x86_machine_set_smm, 1419 NULL, NULL); 1420 object_class_property_set_description(oc, X86_MACHINE_SMM, 1421 "Enable SMM"); 1422 1423 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1424 x86_machine_get_acpi, x86_machine_set_acpi, 1425 NULL, NULL); 1426 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1427 "Enable ACPI"); 1428 1429 object_class_property_add(oc, X86_MACHINE_PIT, "OnOffAuto", 1430 x86_machine_get_pit, 1431 x86_machine_set_pit, 1432 NULL, NULL); 1433 object_class_property_set_description(oc, X86_MACHINE_PIT, 1434 "Enable i8254 PIT"); 1435 1436 object_class_property_add(oc, X86_MACHINE_PIC, "OnOffAuto", 1437 x86_machine_get_pic, 1438 x86_machine_set_pic, 1439 NULL, NULL); 1440 object_class_property_set_description(oc, X86_MACHINE_PIC, 1441 "Enable i8259 PIC"); 1442 1443 object_class_property_add_str(oc, X86_MACHINE_OEM_ID, 1444 x86_machine_get_oem_id, 1445 x86_machine_set_oem_id); 1446 object_class_property_set_description(oc, X86_MACHINE_OEM_ID, 1447 "Override the default value of field OEMID " 1448 "in ACPI table header." 1449 "The string may be up to 6 bytes in size"); 1450 1451 1452 object_class_property_add_str(oc, X86_MACHINE_OEM_TABLE_ID, 1453 x86_machine_get_oem_table_id, 1454 x86_machine_set_oem_table_id); 1455 object_class_property_set_description(oc, X86_MACHINE_OEM_TABLE_ID, 1456 "Override the default value of field OEM Table ID " 1457 "in ACPI table header." 1458 "The string may be up to 8 bytes in size"); 1459 1460 object_class_property_add(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, "uint64_t", 1461 x86_machine_get_bus_lock_ratelimit, 1462 x86_machine_set_bus_lock_ratelimit, NULL, NULL); 1463 object_class_property_set_description(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, 1464 "Set the ratelimit for the bus locks acquired in VMs"); 1465 1466 object_class_property_add(oc, "sgx-epc", "SgxEPC", 1467 machine_get_sgx_epc, machine_set_sgx_epc, 1468 NULL, NULL); 1469 object_class_property_set_description(oc, "sgx-epc", 1470 "SGX EPC device"); 1471 } 1472 1473 static const TypeInfo x86_machine_info = { 1474 .name = TYPE_X86_MACHINE, 1475 .parent = TYPE_MACHINE, 1476 .abstract = true, 1477 .instance_size = sizeof(X86MachineState), 1478 .instance_init = x86_machine_initfn, 1479 .class_size = sizeof(X86MachineClass), 1480 .class_init = x86_machine_class_init, 1481 .interfaces = (InterfaceInfo[]) { 1482 { TYPE_NMI }, 1483 { } 1484 }, 1485 }; 1486 1487 static void x86_machine_register_types(void) 1488 { 1489 type_register_static(&x86_machine_info); 1490 } 1491 1492 type_init(x86_machine_register_types) 1493