1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu/datadir.h" 29 #include "qapi/error.h" 30 #include "qapi/qapi-visit-common.h" 31 #include "qapi/clone-visitor.h" 32 #include "qapi/qapi-visit-machine.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/whpx.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/replay.h" 38 #include "sysemu/sysemu.h" 39 #include "sysemu/cpu-timers.h" 40 #include "sysemu/xen.h" 41 #include "trace.h" 42 43 #include "hw/i386/x86.h" 44 #include "target/i386/cpu.h" 45 #include "hw/i386/topology.h" 46 #include "hw/i386/fw_cfg.h" 47 #include "hw/intc/i8259.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "target/i386/sev.h" 50 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "hw/irq.h" 53 #include "hw/nmi.h" 54 #include "hw/loader.h" 55 #include "multiboot.h" 56 #include "elf.h" 57 #include "standard-headers/asm-x86/bootparam.h" 58 #include CONFIG_DEVICES 59 #include "kvm/kvm_i386.h" 60 61 #ifdef CONFIG_XEN_EMU 62 #include "hw/xen/xen.h" 63 #include "hw/i386/kvm/xen_evtchn.h" 64 #endif 65 66 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 67 static size_t pvh_start_addr; 68 69 static void init_topo_info(X86CPUTopoInfo *topo_info, 70 const X86MachineState *x86ms) 71 { 72 MachineState *ms = MACHINE(x86ms); 73 74 topo_info->dies_per_pkg = ms->smp.dies; 75 topo_info->cores_per_die = ms->smp.cores; 76 topo_info->threads_per_core = ms->smp.threads; 77 } 78 79 /* 80 * Calculates initial APIC ID for a specific CPU index 81 * 82 * Currently we need to be able to calculate the APIC ID from the CPU index 83 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 84 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 85 * all CPUs up to max_cpus. 86 */ 87 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 88 unsigned int cpu_index) 89 { 90 X86CPUTopoInfo topo_info; 91 92 init_topo_info(&topo_info, x86ms); 93 94 return x86_apicid_from_cpu_idx(&topo_info, cpu_index); 95 } 96 97 98 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 99 { 100 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 101 102 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 103 goto out; 104 } 105 qdev_realize(DEVICE(cpu), NULL, errp); 106 107 out: 108 object_unref(cpu); 109 } 110 111 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 112 { 113 int i; 114 const CPUArchIdList *possible_cpus; 115 MachineState *ms = MACHINE(x86ms); 116 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 117 118 x86_cpu_set_default_version(default_cpu_version); 119 120 /* 121 * Calculates the limit to CPU APIC ID values 122 * 123 * Limit for the APIC ID value, so that all 124 * CPU APIC IDs are < x86ms->apic_id_limit. 125 * 126 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 127 */ 128 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 129 ms->smp.max_cpus - 1) + 1; 130 131 /* 132 * Can we support APIC ID 255 or higher? 133 * 134 * Under Xen: yes. 135 * With userspace emulated lapic: no 136 * With KVM's in-kernel lapic: only if X2APIC API is enabled. 137 */ 138 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 139 (!kvm_irqchip_in_kernel() || !kvm_enable_x2apic())) { 140 error_report("current -smp configuration requires kernel " 141 "irqchip and X2APIC API support."); 142 exit(EXIT_FAILURE); 143 } 144 145 if (kvm_enabled()) { 146 kvm_set_max_apic_id(x86ms->apic_id_limit); 147 } 148 149 possible_cpus = mc->possible_cpu_arch_ids(ms); 150 for (i = 0; i < ms->smp.cpus; i++) { 151 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 152 } 153 } 154 155 void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) 156 { 157 MC146818RtcState *rtc = MC146818_RTC(s); 158 159 if (cpus_count > 0xff) { 160 /* 161 * If the number of CPUs can't be represented in 8 bits, the 162 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 163 * to make old BIOSes fail more predictably. 164 */ 165 mc146818rtc_set_cmos_data(rtc, 0x5f, 0); 166 } else { 167 mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); 168 } 169 } 170 171 static int x86_apic_cmp(const void *a, const void *b) 172 { 173 CPUArchId *apic_a = (CPUArchId *)a; 174 CPUArchId *apic_b = (CPUArchId *)b; 175 176 return apic_a->arch_id - apic_b->arch_id; 177 } 178 179 /* 180 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 181 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 182 * entry corresponding to CPU's apic_id returns NULL. 183 */ 184 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 185 { 186 CPUArchId apic_id, *found_cpu; 187 188 apic_id.arch_id = id; 189 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 190 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 191 x86_apic_cmp); 192 if (found_cpu && idx) { 193 *idx = found_cpu - ms->possible_cpus->cpus; 194 } 195 return found_cpu; 196 } 197 198 void x86_cpu_plug(HotplugHandler *hotplug_dev, 199 DeviceState *dev, Error **errp) 200 { 201 CPUArchId *found_cpu; 202 Error *local_err = NULL; 203 X86CPU *cpu = X86_CPU(dev); 204 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 205 206 if (x86ms->acpi_dev) { 207 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 208 if (local_err) { 209 goto out; 210 } 211 } 212 213 /* increment the number of CPUs */ 214 x86ms->boot_cpus++; 215 if (x86ms->rtc) { 216 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 217 } 218 if (x86ms->fw_cfg) { 219 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 220 } 221 222 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 223 found_cpu->cpu = OBJECT(dev); 224 out: 225 error_propagate(errp, local_err); 226 } 227 228 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 229 DeviceState *dev, Error **errp) 230 { 231 int idx = -1; 232 X86CPU *cpu = X86_CPU(dev); 233 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 234 235 if (!x86ms->acpi_dev) { 236 error_setg(errp, "CPU hot unplug not supported without ACPI"); 237 return; 238 } 239 240 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 241 assert(idx != -1); 242 if (idx == 0) { 243 error_setg(errp, "Boot CPU is unpluggable"); 244 return; 245 } 246 247 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 248 errp); 249 } 250 251 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 252 DeviceState *dev, Error **errp) 253 { 254 CPUArchId *found_cpu; 255 Error *local_err = NULL; 256 X86CPU *cpu = X86_CPU(dev); 257 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 258 259 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 260 if (local_err) { 261 goto out; 262 } 263 264 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 265 found_cpu->cpu = NULL; 266 qdev_unrealize(dev); 267 268 /* decrement the number of CPUs */ 269 x86ms->boot_cpus--; 270 /* Update the number of CPUs in CMOS */ 271 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 272 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 273 out: 274 error_propagate(errp, local_err); 275 } 276 277 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 278 DeviceState *dev, Error **errp) 279 { 280 int idx; 281 CPUState *cs; 282 CPUArchId *cpu_slot; 283 X86CPUTopoIDs topo_ids; 284 X86CPU *cpu = X86_CPU(dev); 285 CPUX86State *env = &cpu->env; 286 MachineState *ms = MACHINE(hotplug_dev); 287 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 288 unsigned int smp_cores = ms->smp.cores; 289 unsigned int smp_threads = ms->smp.threads; 290 X86CPUTopoInfo topo_info; 291 292 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 293 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 294 ms->cpu_type); 295 return; 296 } 297 298 if (x86ms->acpi_dev) { 299 Error *local_err = NULL; 300 301 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 302 &local_err); 303 if (local_err) { 304 error_propagate(errp, local_err); 305 return; 306 } 307 } 308 309 init_topo_info(&topo_info, x86ms); 310 311 env->nr_dies = ms->smp.dies; 312 313 /* 314 * If APIC ID is not set, 315 * set it based on socket/die/core/thread properties. 316 */ 317 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 318 int max_socket = (ms->smp.max_cpus - 1) / 319 smp_threads / smp_cores / ms->smp.dies; 320 321 /* 322 * die-id was optional in QEMU 4.0 and older, so keep it optional 323 * if there's only one die per socket. 324 */ 325 if (cpu->die_id < 0 && ms->smp.dies == 1) { 326 cpu->die_id = 0; 327 } 328 329 if (cpu->socket_id < 0) { 330 error_setg(errp, "CPU socket-id is not set"); 331 return; 332 } else if (cpu->socket_id > max_socket) { 333 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 334 cpu->socket_id, max_socket); 335 return; 336 } 337 if (cpu->die_id < 0) { 338 error_setg(errp, "CPU die-id is not set"); 339 return; 340 } else if (cpu->die_id > ms->smp.dies - 1) { 341 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 342 cpu->die_id, ms->smp.dies - 1); 343 return; 344 } 345 if (cpu->core_id < 0) { 346 error_setg(errp, "CPU core-id is not set"); 347 return; 348 } else if (cpu->core_id > (smp_cores - 1)) { 349 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 350 cpu->core_id, smp_cores - 1); 351 return; 352 } 353 if (cpu->thread_id < 0) { 354 error_setg(errp, "CPU thread-id is not set"); 355 return; 356 } else if (cpu->thread_id > (smp_threads - 1)) { 357 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 358 cpu->thread_id, smp_threads - 1); 359 return; 360 } 361 362 topo_ids.pkg_id = cpu->socket_id; 363 topo_ids.die_id = cpu->die_id; 364 topo_ids.core_id = cpu->core_id; 365 topo_ids.smt_id = cpu->thread_id; 366 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 367 } 368 369 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 370 if (!cpu_slot) { 371 MachineState *ms = MACHINE(x86ms); 372 373 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 374 error_setg(errp, 375 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 376 " APIC ID %" PRIu32 ", valid index range 0:%d", 377 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 378 cpu->apic_id, ms->possible_cpus->len - 1); 379 return; 380 } 381 382 if (cpu_slot->cpu) { 383 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 384 idx, cpu->apic_id); 385 return; 386 } 387 388 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 389 * so that machine_query_hotpluggable_cpus would show correct values 390 */ 391 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 392 * once -smp refactoring is complete and there will be CPU private 393 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 394 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 395 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 396 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 397 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 398 topo_ids.pkg_id); 399 return; 400 } 401 cpu->socket_id = topo_ids.pkg_id; 402 403 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 404 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 405 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 406 return; 407 } 408 cpu->die_id = topo_ids.die_id; 409 410 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 411 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 412 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 413 topo_ids.core_id); 414 return; 415 } 416 cpu->core_id = topo_ids.core_id; 417 418 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 419 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 420 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 421 topo_ids.smt_id); 422 return; 423 } 424 cpu->thread_id = topo_ids.smt_id; 425 426 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 427 !kvm_hv_vpindex_settable()) { 428 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 429 return; 430 } 431 432 cs = CPU(cpu); 433 cs->cpu_index = idx; 434 435 numa_cpu_pre_plug(cpu_slot, dev, errp); 436 } 437 438 CpuInstanceProperties 439 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 440 { 441 MachineClass *mc = MACHINE_GET_CLASS(ms); 442 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 443 444 assert(cpu_index < possible_cpus->len); 445 return possible_cpus->cpus[cpu_index].props; 446 } 447 448 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 449 { 450 X86CPUTopoIDs topo_ids; 451 X86MachineState *x86ms = X86_MACHINE(ms); 452 X86CPUTopoInfo topo_info; 453 454 init_topo_info(&topo_info, x86ms); 455 456 assert(idx < ms->possible_cpus->len); 457 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 458 &topo_info, &topo_ids); 459 return topo_ids.pkg_id % ms->numa_state->num_nodes; 460 } 461 462 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 463 { 464 X86MachineState *x86ms = X86_MACHINE(ms); 465 unsigned int max_cpus = ms->smp.max_cpus; 466 X86CPUTopoInfo topo_info; 467 int i; 468 469 if (ms->possible_cpus) { 470 /* 471 * make sure that max_cpus hasn't changed since the first use, i.e. 472 * -smp hasn't been parsed after it 473 */ 474 assert(ms->possible_cpus->len == max_cpus); 475 return ms->possible_cpus; 476 } 477 478 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 479 sizeof(CPUArchId) * max_cpus); 480 ms->possible_cpus->len = max_cpus; 481 482 init_topo_info(&topo_info, x86ms); 483 484 for (i = 0; i < ms->possible_cpus->len; i++) { 485 X86CPUTopoIDs topo_ids; 486 487 ms->possible_cpus->cpus[i].type = ms->cpu_type; 488 ms->possible_cpus->cpus[i].vcpus_count = 1; 489 ms->possible_cpus->cpus[i].arch_id = 490 x86_cpu_apic_id_from_index(x86ms, i); 491 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 492 &topo_info, &topo_ids); 493 ms->possible_cpus->cpus[i].props.has_socket_id = true; 494 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 495 if (ms->smp.dies > 1) { 496 ms->possible_cpus->cpus[i].props.has_die_id = true; 497 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 498 } 499 ms->possible_cpus->cpus[i].props.has_core_id = true; 500 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 501 ms->possible_cpus->cpus[i].props.has_thread_id = true; 502 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 503 } 504 return ms->possible_cpus; 505 } 506 507 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 508 { 509 /* cpu index isn't used */ 510 CPUState *cs; 511 512 CPU_FOREACH(cs) { 513 X86CPU *cpu = X86_CPU(cs); 514 515 if (!cpu->apic_state) { 516 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 517 } else { 518 apic_deliver_nmi(cpu->apic_state); 519 } 520 } 521 } 522 523 static long get_file_size(FILE *f) 524 { 525 long where, size; 526 527 /* XXX: on Unix systems, using fstat() probably makes more sense */ 528 529 where = ftell(f); 530 fseek(f, 0, SEEK_END); 531 size = ftell(f); 532 fseek(f, where, SEEK_SET); 533 534 return size; 535 } 536 537 /* TSC handling */ 538 uint64_t cpu_get_tsc(CPUX86State *env) 539 { 540 return cpus_get_elapsed_ticks(); 541 } 542 543 /* IRQ handling */ 544 static void pic_irq_request(void *opaque, int irq, int level) 545 { 546 CPUState *cs = first_cpu; 547 X86CPU *cpu = X86_CPU(cs); 548 549 trace_x86_pic_interrupt(irq, level); 550 if (cpu->apic_state && !kvm_irqchip_in_kernel() && 551 !whpx_apic_in_platform()) { 552 CPU_FOREACH(cs) { 553 cpu = X86_CPU(cs); 554 if (apic_accept_pic_intr(cpu->apic_state)) { 555 apic_deliver_pic_intr(cpu->apic_state, level); 556 } 557 } 558 } else { 559 if (level) { 560 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 561 } else { 562 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 563 } 564 } 565 } 566 567 qemu_irq x86_allocate_cpu_irq(void) 568 { 569 return qemu_allocate_irq(pic_irq_request, NULL, 0); 570 } 571 572 int cpu_get_pic_interrupt(CPUX86State *env) 573 { 574 X86CPU *cpu = env_archcpu(env); 575 int intno; 576 577 if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { 578 intno = apic_get_interrupt(cpu->apic_state); 579 if (intno >= 0) { 580 return intno; 581 } 582 /* read the irq from the PIC */ 583 if (!apic_accept_pic_intr(cpu->apic_state)) { 584 return -1; 585 } 586 } 587 588 intno = pic_read_irq(isa_pic); 589 return intno; 590 } 591 592 DeviceState *cpu_get_current_apic(void) 593 { 594 if (current_cpu) { 595 X86CPU *cpu = X86_CPU(current_cpu); 596 return cpu->apic_state; 597 } else { 598 return NULL; 599 } 600 } 601 602 void gsi_handler(void *opaque, int n, int level) 603 { 604 GSIState *s = opaque; 605 606 trace_x86_gsi_interrupt(n, level); 607 switch (n) { 608 case 0 ... ISA_NUM_IRQS - 1: 609 if (s->i8259_irq[n]) { 610 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 611 qemu_set_irq(s->i8259_irq[n], level); 612 } 613 /* fall through */ 614 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 615 #ifdef CONFIG_XEN_EMU 616 /* 617 * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC 618 * routing actually works properly under Xen). And then to 619 * *either* the PIRQ handling or the I/OAPIC depending on 620 * whether the former wants it. 621 */ 622 if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { 623 break; 624 } 625 #endif 626 qemu_set_irq(s->ioapic_irq[n], level); 627 break; 628 case IO_APIC_SECONDARY_IRQBASE 629 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 630 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 631 break; 632 } 633 } 634 635 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 636 { 637 DeviceState *dev; 638 SysBusDevice *d; 639 unsigned int i; 640 641 assert(parent_name); 642 if (kvm_ioapic_in_kernel()) { 643 dev = qdev_new(TYPE_KVM_IOAPIC); 644 } else { 645 dev = qdev_new(TYPE_IOAPIC); 646 } 647 object_property_add_child(object_resolve_path(parent_name, NULL), 648 "ioapic", OBJECT(dev)); 649 d = SYS_BUS_DEVICE(dev); 650 sysbus_realize_and_unref(d, &error_fatal); 651 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 652 653 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 654 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 655 } 656 } 657 658 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 659 { 660 DeviceState *dev; 661 SysBusDevice *d; 662 unsigned int i; 663 664 dev = qdev_new(TYPE_IOAPIC); 665 d = SYS_BUS_DEVICE(dev); 666 sysbus_realize_and_unref(d, &error_fatal); 667 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 668 669 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 670 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 671 } 672 return dev; 673 } 674 675 struct setup_data { 676 uint64_t next; 677 uint32_t type; 678 uint32_t len; 679 uint8_t data[]; 680 } __attribute__((packed)); 681 682 683 /* 684 * The entry point into the kernel for PVH boot is different from 685 * the native entry point. The PVH entry is defined by the x86/HVM 686 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 687 * 688 * This function is passed to load_elf() when it is called from 689 * load_elfboot() which then additionally checks for an ELF Note of 690 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 691 * parse the PVH entry address from the ELF Note. 692 * 693 * Due to trickery in elf_opts.h, load_elf() is actually available as 694 * load_elf32() or load_elf64() and this routine needs to be able 695 * to deal with being called as 32 or 64 bit. 696 * 697 * The address of the PVH entry point is saved to the 'pvh_start_addr' 698 * global variable. (although the entry point is 32-bit, the kernel 699 * binary can be either 32-bit or 64-bit). 700 */ 701 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 702 { 703 size_t *elf_note_data_addr; 704 705 /* Check if ELF Note header passed in is valid */ 706 if (arg1 == NULL) { 707 return 0; 708 } 709 710 if (is64) { 711 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 712 uint64_t nhdr_size64 = sizeof(struct elf64_note); 713 uint64_t phdr_align = *(uint64_t *)arg2; 714 uint64_t nhdr_namesz = nhdr64->n_namesz; 715 716 elf_note_data_addr = 717 ((void *)nhdr64) + nhdr_size64 + 718 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 719 720 pvh_start_addr = *elf_note_data_addr; 721 } else { 722 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 723 uint32_t nhdr_size32 = sizeof(struct elf32_note); 724 uint32_t phdr_align = *(uint32_t *)arg2; 725 uint32_t nhdr_namesz = nhdr32->n_namesz; 726 727 elf_note_data_addr = 728 ((void *)nhdr32) + nhdr_size32 + 729 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 730 731 pvh_start_addr = *(uint32_t *)elf_note_data_addr; 732 } 733 734 return pvh_start_addr; 735 } 736 737 static bool load_elfboot(const char *kernel_filename, 738 int kernel_file_size, 739 uint8_t *header, 740 size_t pvh_xen_start_addr, 741 FWCfgState *fw_cfg) 742 { 743 uint32_t flags = 0; 744 uint32_t mh_load_addr = 0; 745 uint32_t elf_kernel_size = 0; 746 uint64_t elf_entry; 747 uint64_t elf_low, elf_high; 748 int kernel_size; 749 750 if (ldl_p(header) != 0x464c457f) { 751 return false; /* no elfboot */ 752 } 753 754 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 755 flags = elf_is64 ? 756 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 757 758 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 759 error_report("elfboot unsupported flags = %x", flags); 760 exit(1); 761 } 762 763 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 764 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 765 NULL, &elf_note_type, &elf_entry, 766 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 767 0, 0); 768 769 if (kernel_size < 0) { 770 error_report("Error while loading elf kernel"); 771 exit(1); 772 } 773 mh_load_addr = elf_low; 774 elf_kernel_size = elf_high - elf_low; 775 776 if (pvh_start_addr == 0) { 777 error_report("Error loading uncompressed kernel without PVH ELF Note"); 778 exit(1); 779 } 780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 781 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 782 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 783 784 return true; 785 } 786 787 void x86_load_linux(X86MachineState *x86ms, 788 FWCfgState *fw_cfg, 789 int acpi_data_size, 790 bool pvh_enabled) 791 { 792 bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; 793 uint16_t protocol; 794 int setup_size, kernel_size, cmdline_size; 795 int dtb_size, setup_data_offset; 796 uint32_t initrd_max; 797 uint8_t header[8192], *setup, *kernel; 798 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 799 FILE *f; 800 char *vmode; 801 MachineState *machine = MACHINE(x86ms); 802 struct setup_data *setup_data; 803 const char *kernel_filename = machine->kernel_filename; 804 const char *initrd_filename = machine->initrd_filename; 805 const char *dtb_filename = machine->dtb; 806 const char *kernel_cmdline = machine->kernel_cmdline; 807 SevKernelLoaderContext sev_load_ctx = {}; 808 809 /* Align to 16 bytes as a paranoia measure */ 810 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; 811 812 /* load the kernel header */ 813 f = fopen(kernel_filename, "rb"); 814 if (!f) { 815 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 816 kernel_filename, strerror(errno)); 817 exit(1); 818 } 819 820 kernel_size = get_file_size(f); 821 if (!kernel_size || 822 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 823 MIN(ARRAY_SIZE(header), kernel_size)) { 824 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 825 kernel_filename, strerror(errno)); 826 exit(1); 827 } 828 829 /* kernel protocol version */ 830 if (ldl_p(header + 0x202) == 0x53726448) { 831 protocol = lduw_p(header + 0x206); 832 } else { 833 /* 834 * This could be a multiboot kernel. If it is, let's stop treating it 835 * like a Linux kernel. 836 * Note: some multiboot images could be in the ELF format (the same of 837 * PVH), so we try multiboot first since we check the multiboot magic 838 * header before to load it. 839 */ 840 if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, 841 kernel_cmdline, kernel_size, header)) { 842 return; 843 } 844 /* 845 * Check if the file is an uncompressed kernel file (ELF) and load it, 846 * saving the PVH entry point used by the x86/HVM direct boot ABI. 847 * If load_elfboot() is successful, populate the fw_cfg info. 848 */ 849 if (pvh_enabled && 850 load_elfboot(kernel_filename, kernel_size, 851 header, pvh_start_addr, fw_cfg)) { 852 fclose(f); 853 854 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 855 strlen(kernel_cmdline) + 1); 856 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 857 858 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 859 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 860 header, sizeof(header)); 861 862 /* load initrd */ 863 if (initrd_filename) { 864 GMappedFile *mapped_file; 865 gsize initrd_size; 866 gchar *initrd_data; 867 GError *gerr = NULL; 868 869 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 870 if (!mapped_file) { 871 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 872 initrd_filename, gerr->message); 873 exit(1); 874 } 875 x86ms->initrd_mapped_file = mapped_file; 876 877 initrd_data = g_mapped_file_get_contents(mapped_file); 878 initrd_size = g_mapped_file_get_length(mapped_file); 879 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 880 if (initrd_size >= initrd_max) { 881 fprintf(stderr, "qemu: initrd is too large, cannot support." 882 "(max: %"PRIu32", need %"PRId64")\n", 883 initrd_max, (uint64_t)initrd_size); 884 exit(1); 885 } 886 887 initrd_addr = (initrd_max - initrd_size) & ~4095; 888 889 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 890 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 891 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 892 initrd_size); 893 } 894 895 option_rom[nb_option_roms].bootindex = 0; 896 option_rom[nb_option_roms].name = "pvh.bin"; 897 nb_option_roms++; 898 899 return; 900 } 901 protocol = 0; 902 } 903 904 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 905 /* Low kernel */ 906 real_addr = 0x90000; 907 cmdline_addr = 0x9a000 - cmdline_size; 908 prot_addr = 0x10000; 909 } else if (protocol < 0x202) { 910 /* High but ancient kernel */ 911 real_addr = 0x90000; 912 cmdline_addr = 0x9a000 - cmdline_size; 913 prot_addr = 0x100000; 914 } else { 915 /* High and recent kernel */ 916 real_addr = 0x10000; 917 cmdline_addr = 0x20000; 918 prot_addr = 0x100000; 919 } 920 921 /* highest address for loading the initrd */ 922 if (protocol >= 0x20c && 923 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 924 /* 925 * Linux has supported initrd up to 4 GB for a very long time (2007, 926 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 927 * though it only sets initrd_max to 2 GB to "work around bootloader 928 * bugs". Luckily, QEMU firmware(which does something like bootloader) 929 * has supported this. 930 * 931 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 932 * be loaded into any address. 933 * 934 * In addition, initrd_max is uint32_t simply because QEMU doesn't 935 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 936 * field). 937 * 938 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 939 */ 940 initrd_max = UINT32_MAX; 941 } else if (protocol >= 0x203) { 942 initrd_max = ldl_p(header + 0x22c); 943 } else { 944 initrd_max = 0x37ffffff; 945 } 946 947 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 948 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 949 } 950 951 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 952 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); 953 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 954 sev_load_ctx.cmdline_data = (char *)kernel_cmdline; 955 sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; 956 957 if (protocol >= 0x202) { 958 stl_p(header + 0x228, cmdline_addr); 959 } else { 960 stw_p(header + 0x20, 0xA33F); 961 stw_p(header + 0x22, cmdline_addr - real_addr); 962 } 963 964 /* handle vga= parameter */ 965 vmode = strstr(kernel_cmdline, "vga="); 966 if (vmode) { 967 unsigned int video_mode; 968 const char *end; 969 int ret; 970 /* skip "vga=" */ 971 vmode += 4; 972 if (!strncmp(vmode, "normal", 6)) { 973 video_mode = 0xffff; 974 } else if (!strncmp(vmode, "ext", 3)) { 975 video_mode = 0xfffe; 976 } else if (!strncmp(vmode, "ask", 3)) { 977 video_mode = 0xfffd; 978 } else { 979 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 980 if (ret != 0 || (*end && *end != ' ')) { 981 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 982 exit(1); 983 } 984 } 985 stw_p(header + 0x1fa, video_mode); 986 } 987 988 /* loader type */ 989 /* 990 * High nybble = B reserved for QEMU; low nybble is revision number. 991 * If this code is substantially changed, you may want to consider 992 * incrementing the revision. 993 */ 994 if (protocol >= 0x200) { 995 header[0x210] = 0xB0; 996 } 997 /* heap */ 998 if (protocol >= 0x201) { 999 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1000 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 1001 } 1002 1003 /* load initrd */ 1004 if (initrd_filename) { 1005 GMappedFile *mapped_file; 1006 gsize initrd_size; 1007 gchar *initrd_data; 1008 GError *gerr = NULL; 1009 1010 if (protocol < 0x200) { 1011 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1012 exit(1); 1013 } 1014 1015 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1016 if (!mapped_file) { 1017 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1018 initrd_filename, gerr->message); 1019 exit(1); 1020 } 1021 x86ms->initrd_mapped_file = mapped_file; 1022 1023 initrd_data = g_mapped_file_get_contents(mapped_file); 1024 initrd_size = g_mapped_file_get_length(mapped_file); 1025 if (initrd_size >= initrd_max) { 1026 fprintf(stderr, "qemu: initrd is too large, cannot support." 1027 "(max: %"PRIu32", need %"PRId64")\n", 1028 initrd_max, (uint64_t)initrd_size); 1029 exit(1); 1030 } 1031 1032 initrd_addr = (initrd_max - initrd_size) & ~4095; 1033 1034 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1035 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1036 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1037 sev_load_ctx.initrd_data = initrd_data; 1038 sev_load_ctx.initrd_size = initrd_size; 1039 1040 stl_p(header + 0x218, initrd_addr); 1041 stl_p(header + 0x21c, initrd_size); 1042 } 1043 1044 /* load kernel and setup */ 1045 setup_size = header[0x1f1]; 1046 if (setup_size == 0) { 1047 setup_size = 4; 1048 } 1049 setup_size = (setup_size + 1) * 512; 1050 if (setup_size > kernel_size) { 1051 fprintf(stderr, "qemu: invalid kernel header\n"); 1052 exit(1); 1053 } 1054 kernel_size -= setup_size; 1055 1056 setup = g_malloc(setup_size); 1057 kernel = g_malloc(kernel_size); 1058 fseek(f, 0, SEEK_SET); 1059 if (fread(setup, 1, setup_size, f) != setup_size) { 1060 fprintf(stderr, "fread() failed\n"); 1061 exit(1); 1062 } 1063 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1064 fprintf(stderr, "fread() failed\n"); 1065 exit(1); 1066 } 1067 fclose(f); 1068 1069 /* append dtb to kernel */ 1070 if (dtb_filename) { 1071 if (protocol < 0x209) { 1072 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1073 exit(1); 1074 } 1075 1076 dtb_size = get_image_size(dtb_filename); 1077 if (dtb_size <= 0) { 1078 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1079 dtb_filename, strerror(errno)); 1080 exit(1); 1081 } 1082 1083 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1084 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1085 kernel = g_realloc(kernel, kernel_size); 1086 1087 stq_p(header + 0x250, prot_addr + setup_data_offset); 1088 1089 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1090 setup_data->next = 0; 1091 setup_data->type = cpu_to_le32(SETUP_DTB); 1092 setup_data->len = cpu_to_le32(dtb_size); 1093 1094 load_image_size(dtb_filename, setup_data->data, dtb_size); 1095 } 1096 1097 /* 1098 * If we're starting an encrypted VM, it will be OVMF based, which uses the 1099 * efi stub for booting and doesn't require any values to be placed in the 1100 * kernel header. We therefore don't update the header so the hash of the 1101 * kernel on the other side of the fw_cfg interface matches the hash of the 1102 * file the user passed in. 1103 */ 1104 if (!sev_enabled()) { 1105 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1106 } 1107 1108 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1109 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1110 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1111 sev_load_ctx.kernel_data = (char *)kernel; 1112 sev_load_ctx.kernel_size = kernel_size; 1113 1114 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1115 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1116 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1117 sev_load_ctx.setup_data = (char *)setup; 1118 sev_load_ctx.setup_size = setup_size; 1119 1120 if (sev_enabled()) { 1121 sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); 1122 } 1123 1124 option_rom[nb_option_roms].bootindex = 0; 1125 option_rom[nb_option_roms].name = "linuxboot.bin"; 1126 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1127 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1128 } 1129 nb_option_roms++; 1130 } 1131 1132 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 1133 MemoryRegion *rom_memory, bool isapc_ram_fw) 1134 { 1135 const char *bios_name; 1136 char *filename; 1137 MemoryRegion *bios, *isa_bios; 1138 int bios_size, isa_bios_size; 1139 ssize_t ret; 1140 1141 /* BIOS load */ 1142 bios_name = ms->firmware ?: default_firmware; 1143 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1144 if (filename) { 1145 bios_size = get_image_size(filename); 1146 } else { 1147 bios_size = -1; 1148 } 1149 if (bios_size <= 0 || 1150 (bios_size % 65536) != 0) { 1151 goto bios_error; 1152 } 1153 bios = g_malloc(sizeof(*bios)); 1154 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1155 if (sev_enabled()) { 1156 /* 1157 * The concept of a "reset" simply doesn't exist for 1158 * confidential computing guests, we have to destroy and 1159 * re-launch them instead. So there is no need to register 1160 * the firmware as rom to properly re-initialize on reset. 1161 * Just go for a straight file load instead. 1162 */ 1163 void *ptr = memory_region_get_ram_ptr(bios); 1164 load_image_size(filename, ptr, bios_size); 1165 x86_firmware_configure(ptr, bios_size); 1166 } else { 1167 if (!isapc_ram_fw) { 1168 memory_region_set_readonly(bios, true); 1169 } 1170 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1171 if (ret != 0) { 1172 goto bios_error; 1173 } 1174 } 1175 g_free(filename); 1176 1177 /* map the last 128KB of the BIOS in ISA space */ 1178 isa_bios_size = MIN(bios_size, 128 * KiB); 1179 isa_bios = g_malloc(sizeof(*isa_bios)); 1180 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1181 bios_size - isa_bios_size, isa_bios_size); 1182 memory_region_add_subregion_overlap(rom_memory, 1183 0x100000 - isa_bios_size, 1184 isa_bios, 1185 1); 1186 if (!isapc_ram_fw) { 1187 memory_region_set_readonly(isa_bios, true); 1188 } 1189 1190 /* map all the bios at the top of memory */ 1191 memory_region_add_subregion(rom_memory, 1192 (uint32_t)(-bios_size), 1193 bios); 1194 return; 1195 1196 bios_error: 1197 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1198 exit(1); 1199 } 1200 1201 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1202 { 1203 bool smm_available = false; 1204 1205 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1206 return false; 1207 } 1208 1209 if (tcg_enabled() || qtest_enabled()) { 1210 smm_available = true; 1211 } else if (kvm_enabled()) { 1212 smm_available = kvm_has_smm(); 1213 } 1214 1215 if (smm_available) { 1216 return true; 1217 } 1218 1219 if (x86ms->smm == ON_OFF_AUTO_ON) { 1220 error_report("System Management Mode not supported by this hypervisor."); 1221 exit(1); 1222 } 1223 return false; 1224 } 1225 1226 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1227 void *opaque, Error **errp) 1228 { 1229 X86MachineState *x86ms = X86_MACHINE(obj); 1230 OnOffAuto smm = x86ms->smm; 1231 1232 visit_type_OnOffAuto(v, name, &smm, errp); 1233 } 1234 1235 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1236 void *opaque, Error **errp) 1237 { 1238 X86MachineState *x86ms = X86_MACHINE(obj); 1239 1240 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1241 } 1242 1243 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1244 { 1245 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1246 return false; 1247 } 1248 return true; 1249 } 1250 1251 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1252 void *opaque, Error **errp) 1253 { 1254 X86MachineState *x86ms = X86_MACHINE(obj); 1255 OnOffAuto acpi = x86ms->acpi; 1256 1257 visit_type_OnOffAuto(v, name, &acpi, errp); 1258 } 1259 1260 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1261 void *opaque, Error **errp) 1262 { 1263 X86MachineState *x86ms = X86_MACHINE(obj); 1264 1265 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1266 } 1267 1268 static void x86_machine_get_pit(Object *obj, Visitor *v, const char *name, 1269 void *opaque, Error **errp) 1270 { 1271 X86MachineState *x86ms = X86_MACHINE(obj); 1272 OnOffAuto pit = x86ms->pit; 1273 1274 visit_type_OnOffAuto(v, name, &pit, errp); 1275 } 1276 1277 static void x86_machine_set_pit(Object *obj, Visitor *v, const char *name, 1278 void *opaque, Error **errp) 1279 { 1280 X86MachineState *x86ms = X86_MACHINE(obj);; 1281 1282 visit_type_OnOffAuto(v, name, &x86ms->pit, errp); 1283 } 1284 1285 static void x86_machine_get_pic(Object *obj, Visitor *v, const char *name, 1286 void *opaque, Error **errp) 1287 { 1288 X86MachineState *x86ms = X86_MACHINE(obj); 1289 OnOffAuto pic = x86ms->pic; 1290 1291 visit_type_OnOffAuto(v, name, &pic, errp); 1292 } 1293 1294 static void x86_machine_set_pic(Object *obj, Visitor *v, const char *name, 1295 void *opaque, Error **errp) 1296 { 1297 X86MachineState *x86ms = X86_MACHINE(obj); 1298 1299 visit_type_OnOffAuto(v, name, &x86ms->pic, errp); 1300 } 1301 1302 static char *x86_machine_get_oem_id(Object *obj, Error **errp) 1303 { 1304 X86MachineState *x86ms = X86_MACHINE(obj); 1305 1306 return g_strdup(x86ms->oem_id); 1307 } 1308 1309 static void x86_machine_set_oem_id(Object *obj, const char *value, Error **errp) 1310 { 1311 X86MachineState *x86ms = X86_MACHINE(obj); 1312 size_t len = strlen(value); 1313 1314 if (len > 6) { 1315 error_setg(errp, 1316 "User specified "X86_MACHINE_OEM_ID" value is bigger than " 1317 "6 bytes in size"); 1318 return; 1319 } 1320 1321 strncpy(x86ms->oem_id, value, 6); 1322 } 1323 1324 static char *x86_machine_get_oem_table_id(Object *obj, Error **errp) 1325 { 1326 X86MachineState *x86ms = X86_MACHINE(obj); 1327 1328 return g_strdup(x86ms->oem_table_id); 1329 } 1330 1331 static void x86_machine_set_oem_table_id(Object *obj, const char *value, 1332 Error **errp) 1333 { 1334 X86MachineState *x86ms = X86_MACHINE(obj); 1335 size_t len = strlen(value); 1336 1337 if (len > 8) { 1338 error_setg(errp, 1339 "User specified "X86_MACHINE_OEM_TABLE_ID 1340 " value is bigger than " 1341 "8 bytes in size"); 1342 return; 1343 } 1344 strncpy(x86ms->oem_table_id, value, 8); 1345 } 1346 1347 static void x86_machine_get_bus_lock_ratelimit(Object *obj, Visitor *v, 1348 const char *name, void *opaque, Error **errp) 1349 { 1350 X86MachineState *x86ms = X86_MACHINE(obj); 1351 uint64_t bus_lock_ratelimit = x86ms->bus_lock_ratelimit; 1352 1353 visit_type_uint64(v, name, &bus_lock_ratelimit, errp); 1354 } 1355 1356 static void x86_machine_set_bus_lock_ratelimit(Object *obj, Visitor *v, 1357 const char *name, void *opaque, Error **errp) 1358 { 1359 X86MachineState *x86ms = X86_MACHINE(obj); 1360 1361 visit_type_uint64(v, name, &x86ms->bus_lock_ratelimit, errp); 1362 } 1363 1364 static void machine_get_sgx_epc(Object *obj, Visitor *v, const char *name, 1365 void *opaque, Error **errp) 1366 { 1367 X86MachineState *x86ms = X86_MACHINE(obj); 1368 SgxEPCList *list = x86ms->sgx_epc_list; 1369 1370 visit_type_SgxEPCList(v, name, &list, errp); 1371 } 1372 1373 static void machine_set_sgx_epc(Object *obj, Visitor *v, const char *name, 1374 void *opaque, Error **errp) 1375 { 1376 X86MachineState *x86ms = X86_MACHINE(obj); 1377 SgxEPCList *list; 1378 1379 list = x86ms->sgx_epc_list; 1380 visit_type_SgxEPCList(v, name, &x86ms->sgx_epc_list, errp); 1381 1382 qapi_free_SgxEPCList(list); 1383 } 1384 1385 static void x86_machine_initfn(Object *obj) 1386 { 1387 X86MachineState *x86ms = X86_MACHINE(obj); 1388 1389 x86ms->smm = ON_OFF_AUTO_AUTO; 1390 x86ms->acpi = ON_OFF_AUTO_AUTO; 1391 x86ms->pit = ON_OFF_AUTO_AUTO; 1392 x86ms->pic = ON_OFF_AUTO_AUTO; 1393 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1394 x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1395 x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1396 x86ms->bus_lock_ratelimit = 0; 1397 x86ms->above_4g_mem_start = 4 * GiB; 1398 } 1399 1400 static void x86_machine_class_init(ObjectClass *oc, void *data) 1401 { 1402 MachineClass *mc = MACHINE_CLASS(oc); 1403 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1404 NMIClass *nc = NMI_CLASS(oc); 1405 1406 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1407 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1408 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1409 x86mc->save_tsc_khz = true; 1410 x86mc->fwcfg_dma_enabled = true; 1411 nc->nmi_monitor_handler = x86_nmi; 1412 1413 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1414 x86_machine_get_smm, x86_machine_set_smm, 1415 NULL, NULL); 1416 object_class_property_set_description(oc, X86_MACHINE_SMM, 1417 "Enable SMM"); 1418 1419 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1420 x86_machine_get_acpi, x86_machine_set_acpi, 1421 NULL, NULL); 1422 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1423 "Enable ACPI"); 1424 1425 object_class_property_add(oc, X86_MACHINE_PIT, "OnOffAuto", 1426 x86_machine_get_pit, 1427 x86_machine_set_pit, 1428 NULL, NULL); 1429 object_class_property_set_description(oc, X86_MACHINE_PIT, 1430 "Enable i8254 PIT"); 1431 1432 object_class_property_add(oc, X86_MACHINE_PIC, "OnOffAuto", 1433 x86_machine_get_pic, 1434 x86_machine_set_pic, 1435 NULL, NULL); 1436 object_class_property_set_description(oc, X86_MACHINE_PIC, 1437 "Enable i8259 PIC"); 1438 1439 object_class_property_add_str(oc, X86_MACHINE_OEM_ID, 1440 x86_machine_get_oem_id, 1441 x86_machine_set_oem_id); 1442 object_class_property_set_description(oc, X86_MACHINE_OEM_ID, 1443 "Override the default value of field OEMID " 1444 "in ACPI table header." 1445 "The string may be up to 6 bytes in size"); 1446 1447 1448 object_class_property_add_str(oc, X86_MACHINE_OEM_TABLE_ID, 1449 x86_machine_get_oem_table_id, 1450 x86_machine_set_oem_table_id); 1451 object_class_property_set_description(oc, X86_MACHINE_OEM_TABLE_ID, 1452 "Override the default value of field OEM Table ID " 1453 "in ACPI table header." 1454 "The string may be up to 8 bytes in size"); 1455 1456 object_class_property_add(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, "uint64_t", 1457 x86_machine_get_bus_lock_ratelimit, 1458 x86_machine_set_bus_lock_ratelimit, NULL, NULL); 1459 object_class_property_set_description(oc, X86_MACHINE_BUS_LOCK_RATELIMIT, 1460 "Set the ratelimit for the bus locks acquired in VMs"); 1461 1462 object_class_property_add(oc, "sgx-epc", "SgxEPC", 1463 machine_get_sgx_epc, machine_set_sgx_epc, 1464 NULL, NULL); 1465 object_class_property_set_description(oc, "sgx-epc", 1466 "SGX EPC device"); 1467 } 1468 1469 static const TypeInfo x86_machine_info = { 1470 .name = TYPE_X86_MACHINE, 1471 .parent = TYPE_MACHINE, 1472 .abstract = true, 1473 .instance_size = sizeof(X86MachineState), 1474 .instance_init = x86_machine_initfn, 1475 .class_size = sizeof(X86MachineClass), 1476 .class_init = x86_machine_class_init, 1477 .interfaces = (InterfaceInfo[]) { 1478 { TYPE_NMI }, 1479 { } 1480 }, 1481 }; 1482 1483 static void x86_machine_register_types(void) 1484 { 1485 type_register_static(&x86_machine_info); 1486 } 1487 1488 type_init(x86_machine_register_types) 1489