1 /* 2 * Copyright (c) 2003-2004 Fabrice Bellard 3 * Copyright (c) 2019 Red Hat, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy 6 * of this software and associated documentation files (the "Software"), to deal 7 * in the Software without restriction, including without limitation the rights 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 * copies of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 * THE SOFTWARE. 22 */ 23 #include "qemu/osdep.h" 24 #include "qemu/error-report.h" 25 #include "qemu/option.h" 26 #include "qemu/cutils.h" 27 #include "qemu/units.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/qmp/qerror.h" 31 #include "qapi/qapi-visit-common.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/qtest.h" 34 #include "sysemu/numa.h" 35 #include "sysemu/replay.h" 36 #include "sysemu/sysemu.h" 37 #include "sysemu/cpu-timers.h" 38 #include "trace.h" 39 40 #include "hw/i386/x86.h" 41 #include "target/i386/cpu.h" 42 #include "hw/i386/topology.h" 43 #include "hw/i386/fw_cfg.h" 44 #include "hw/intc/i8259.h" 45 #include "hw/rtc/mc146818rtc.h" 46 47 #include "hw/acpi/cpu_hotplug.h" 48 #include "hw/irq.h" 49 #include "hw/nmi.h" 50 #include "hw/loader.h" 51 #include "multiboot.h" 52 #include "elf.h" 53 #include "standard-headers/asm-x86/bootparam.h" 54 #include CONFIG_DEVICES 55 #include "kvm_i386.h" 56 57 #define BIOS_FILENAME "bios.bin" 58 59 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 60 static size_t pvh_start_addr; 61 62 inline void init_topo_info(X86CPUTopoInfo *topo_info, 63 const X86MachineState *x86ms) 64 { 65 MachineState *ms = MACHINE(x86ms); 66 67 topo_info->dies_per_pkg = x86ms->smp_dies; 68 topo_info->cores_per_die = ms->smp.cores; 69 topo_info->threads_per_core = ms->smp.threads; 70 } 71 72 /* 73 * Calculates initial APIC ID for a specific CPU index 74 * 75 * Currently we need to be able to calculate the APIC ID from the CPU index 76 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 77 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 78 * all CPUs up to max_cpus. 79 */ 80 uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, 81 unsigned int cpu_index) 82 { 83 X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms); 84 X86CPUTopoInfo topo_info; 85 uint32_t correct_id; 86 static bool warned; 87 88 init_topo_info(&topo_info, x86ms); 89 90 correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); 91 if (x86mc->compat_apic_id_mode) { 92 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 93 error_report("APIC IDs set in compatibility mode, " 94 "CPU topology won't match the configuration"); 95 warned = true; 96 } 97 return cpu_index; 98 } else { 99 return correct_id; 100 } 101 } 102 103 104 void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) 105 { 106 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 107 108 if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { 109 goto out; 110 } 111 qdev_realize(DEVICE(cpu), NULL, errp); 112 113 out: 114 object_unref(cpu); 115 } 116 117 void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) 118 { 119 int i; 120 const CPUArchIdList *possible_cpus; 121 MachineState *ms = MACHINE(x86ms); 122 MachineClass *mc = MACHINE_GET_CLASS(x86ms); 123 124 x86_cpu_set_default_version(default_cpu_version); 125 126 /* 127 * Calculates the limit to CPU APIC ID values 128 * 129 * Limit for the APIC ID value, so that all 130 * CPU APIC IDs are < x86ms->apic_id_limit. 131 * 132 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 133 */ 134 x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, 135 ms->smp.max_cpus - 1) + 1; 136 possible_cpus = mc->possible_cpu_arch_ids(ms); 137 for (i = 0; i < ms->smp.cpus; i++) { 138 x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); 139 } 140 } 141 142 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 143 { 144 if (cpus_count > 0xff) { 145 /* 146 * If the number of CPUs can't be represented in 8 bits, the 147 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 148 * to make old BIOSes fail more predictably. 149 */ 150 rtc_set_memory(rtc, 0x5f, 0); 151 } else { 152 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 153 } 154 } 155 156 static int x86_apic_cmp(const void *a, const void *b) 157 { 158 CPUArchId *apic_a = (CPUArchId *)a; 159 CPUArchId *apic_b = (CPUArchId *)b; 160 161 return apic_a->arch_id - apic_b->arch_id; 162 } 163 164 /* 165 * returns pointer to CPUArchId descriptor that matches CPU's apic_id 166 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 167 * entry corresponding to CPU's apic_id returns NULL. 168 */ 169 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 170 { 171 CPUArchId apic_id, *found_cpu; 172 173 apic_id.arch_id = id; 174 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 175 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 176 x86_apic_cmp); 177 if (found_cpu && idx) { 178 *idx = found_cpu - ms->possible_cpus->cpus; 179 } 180 return found_cpu; 181 } 182 183 void x86_cpu_plug(HotplugHandler *hotplug_dev, 184 DeviceState *dev, Error **errp) 185 { 186 CPUArchId *found_cpu; 187 Error *local_err = NULL; 188 X86CPU *cpu = X86_CPU(dev); 189 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 190 191 if (x86ms->acpi_dev) { 192 hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); 193 if (local_err) { 194 goto out; 195 } 196 } 197 198 /* increment the number of CPUs */ 199 x86ms->boot_cpus++; 200 if (x86ms->rtc) { 201 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 202 } 203 if (x86ms->fw_cfg) { 204 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 205 } 206 207 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 208 found_cpu->cpu = OBJECT(dev); 209 out: 210 error_propagate(errp, local_err); 211 } 212 213 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 214 DeviceState *dev, Error **errp) 215 { 216 int idx = -1; 217 X86CPU *cpu = X86_CPU(dev); 218 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 219 220 if (!x86ms->acpi_dev) { 221 error_setg(errp, "CPU hot unplug not supported without ACPI"); 222 return; 223 } 224 225 x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 226 assert(idx != -1); 227 if (idx == 0) { 228 error_setg(errp, "Boot CPU is unpluggable"); 229 return; 230 } 231 232 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 233 errp); 234 } 235 236 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 237 DeviceState *dev, Error **errp) 238 { 239 CPUArchId *found_cpu; 240 Error *local_err = NULL; 241 X86CPU *cpu = X86_CPU(dev); 242 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 243 244 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 245 if (local_err) { 246 goto out; 247 } 248 249 found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); 250 found_cpu->cpu = NULL; 251 qdev_unrealize(dev); 252 253 /* decrement the number of CPUs */ 254 x86ms->boot_cpus--; 255 /* Update the number of CPUs in CMOS */ 256 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 257 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 258 out: 259 error_propagate(errp, local_err); 260 } 261 262 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 263 DeviceState *dev, Error **errp) 264 { 265 int idx; 266 CPUState *cs; 267 CPUArchId *cpu_slot; 268 X86CPUTopoIDs topo_ids; 269 X86CPU *cpu = X86_CPU(dev); 270 CPUX86State *env = &cpu->env; 271 MachineState *ms = MACHINE(hotplug_dev); 272 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 273 unsigned int smp_cores = ms->smp.cores; 274 unsigned int smp_threads = ms->smp.threads; 275 X86CPUTopoInfo topo_info; 276 277 if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 278 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 279 ms->cpu_type); 280 return; 281 } 282 283 if (x86ms->acpi_dev) { 284 Error *local_err = NULL; 285 286 hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, 287 &local_err); 288 if (local_err) { 289 error_propagate(errp, local_err); 290 return; 291 } 292 } 293 294 init_topo_info(&topo_info, x86ms); 295 296 env->nr_dies = x86ms->smp_dies; 297 298 /* 299 * If APIC ID is not set, 300 * set it based on socket/die/core/thread properties. 301 */ 302 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 303 int max_socket = (ms->smp.max_cpus - 1) / 304 smp_threads / smp_cores / x86ms->smp_dies; 305 306 /* 307 * die-id was optional in QEMU 4.0 and older, so keep it optional 308 * if there's only one die per socket. 309 */ 310 if (cpu->die_id < 0 && x86ms->smp_dies == 1) { 311 cpu->die_id = 0; 312 } 313 314 if (cpu->socket_id < 0) { 315 error_setg(errp, "CPU socket-id is not set"); 316 return; 317 } else if (cpu->socket_id > max_socket) { 318 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 319 cpu->socket_id, max_socket); 320 return; 321 } 322 if (cpu->die_id < 0) { 323 error_setg(errp, "CPU die-id is not set"); 324 return; 325 } else if (cpu->die_id > x86ms->smp_dies - 1) { 326 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 327 cpu->die_id, x86ms->smp_dies - 1); 328 return; 329 } 330 if (cpu->core_id < 0) { 331 error_setg(errp, "CPU core-id is not set"); 332 return; 333 } else if (cpu->core_id > (smp_cores - 1)) { 334 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 335 cpu->core_id, smp_cores - 1); 336 return; 337 } 338 if (cpu->thread_id < 0) { 339 error_setg(errp, "CPU thread-id is not set"); 340 return; 341 } else if (cpu->thread_id > (smp_threads - 1)) { 342 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 343 cpu->thread_id, smp_threads - 1); 344 return; 345 } 346 347 topo_ids.pkg_id = cpu->socket_id; 348 topo_ids.die_id = cpu->die_id; 349 topo_ids.core_id = cpu->core_id; 350 topo_ids.smt_id = cpu->thread_id; 351 cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); 352 } 353 354 cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); 355 if (!cpu_slot) { 356 MachineState *ms = MACHINE(x86ms); 357 358 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 359 error_setg(errp, 360 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 361 " APIC ID %" PRIu32 ", valid index range 0:%d", 362 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, 363 cpu->apic_id, ms->possible_cpus->len - 1); 364 return; 365 } 366 367 if (cpu_slot->cpu) { 368 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 369 idx, cpu->apic_id); 370 return; 371 } 372 373 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 374 * so that machine_query_hotpluggable_cpus would show correct values 375 */ 376 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 377 * once -smp refactoring is complete and there will be CPU private 378 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 379 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); 380 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { 381 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 382 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, 383 topo_ids.pkg_id); 384 return; 385 } 386 cpu->socket_id = topo_ids.pkg_id; 387 388 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { 389 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 390 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); 391 return; 392 } 393 cpu->die_id = topo_ids.die_id; 394 395 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { 396 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 397 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, 398 topo_ids.core_id); 399 return; 400 } 401 cpu->core_id = topo_ids.core_id; 402 403 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { 404 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 405 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, 406 topo_ids.smt_id); 407 return; 408 } 409 cpu->thread_id = topo_ids.smt_id; 410 411 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 412 !kvm_hv_vpindex_settable()) { 413 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 414 return; 415 } 416 417 cs = CPU(cpu); 418 cs->cpu_index = idx; 419 420 numa_cpu_pre_plug(cpu_slot, dev, errp); 421 } 422 423 CpuInstanceProperties 424 x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 425 { 426 MachineClass *mc = MACHINE_GET_CLASS(ms); 427 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 428 429 assert(cpu_index < possible_cpus->len); 430 return possible_cpus->cpus[cpu_index].props; 431 } 432 433 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) 434 { 435 X86CPUTopoIDs topo_ids; 436 X86MachineState *x86ms = X86_MACHINE(ms); 437 X86CPUTopoInfo topo_info; 438 439 init_topo_info(&topo_info, x86ms); 440 441 assert(idx < ms->possible_cpus->len); 442 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 443 &topo_info, &topo_ids); 444 return topo_ids.pkg_id % ms->numa_state->num_nodes; 445 } 446 447 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) 448 { 449 X86MachineState *x86ms = X86_MACHINE(ms); 450 unsigned int max_cpus = ms->smp.max_cpus; 451 X86CPUTopoInfo topo_info; 452 int i; 453 454 if (ms->possible_cpus) { 455 /* 456 * make sure that max_cpus hasn't changed since the first use, i.e. 457 * -smp hasn't been parsed after it 458 */ 459 assert(ms->possible_cpus->len == max_cpus); 460 return ms->possible_cpus; 461 } 462 463 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 464 sizeof(CPUArchId) * max_cpus); 465 ms->possible_cpus->len = max_cpus; 466 467 init_topo_info(&topo_info, x86ms); 468 469 for (i = 0; i < ms->possible_cpus->len; i++) { 470 X86CPUTopoIDs topo_ids; 471 472 ms->possible_cpus->cpus[i].type = ms->cpu_type; 473 ms->possible_cpus->cpus[i].vcpus_count = 1; 474 ms->possible_cpus->cpus[i].arch_id = 475 x86_cpu_apic_id_from_index(x86ms, i); 476 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 477 &topo_info, &topo_ids); 478 ms->possible_cpus->cpus[i].props.has_socket_id = true; 479 ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; 480 if (x86ms->smp_dies > 1) { 481 ms->possible_cpus->cpus[i].props.has_die_id = true; 482 ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; 483 } 484 ms->possible_cpus->cpus[i].props.has_core_id = true; 485 ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; 486 ms->possible_cpus->cpus[i].props.has_thread_id = true; 487 ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; 488 } 489 return ms->possible_cpus; 490 } 491 492 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 493 { 494 /* cpu index isn't used */ 495 CPUState *cs; 496 497 CPU_FOREACH(cs) { 498 X86CPU *cpu = X86_CPU(cs); 499 500 if (!cpu->apic_state) { 501 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 502 } else { 503 apic_deliver_nmi(cpu->apic_state); 504 } 505 } 506 } 507 508 static long get_file_size(FILE *f) 509 { 510 long where, size; 511 512 /* XXX: on Unix systems, using fstat() probably makes more sense */ 513 514 where = ftell(f); 515 fseek(f, 0, SEEK_END); 516 size = ftell(f); 517 fseek(f, where, SEEK_SET); 518 519 return size; 520 } 521 522 /* TSC handling */ 523 uint64_t cpu_get_tsc(CPUX86State *env) 524 { 525 return cpus_get_elapsed_ticks(); 526 } 527 528 /* IRQ handling */ 529 static void pic_irq_request(void *opaque, int irq, int level) 530 { 531 CPUState *cs = first_cpu; 532 X86CPU *cpu = X86_CPU(cs); 533 534 trace_x86_pic_interrupt(irq, level); 535 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 536 CPU_FOREACH(cs) { 537 cpu = X86_CPU(cs); 538 if (apic_accept_pic_intr(cpu->apic_state)) { 539 apic_deliver_pic_intr(cpu->apic_state, level); 540 } 541 } 542 } else { 543 if (level) { 544 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 545 } else { 546 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 547 } 548 } 549 } 550 551 qemu_irq x86_allocate_cpu_irq(void) 552 { 553 return qemu_allocate_irq(pic_irq_request, NULL, 0); 554 } 555 556 int cpu_get_pic_interrupt(CPUX86State *env) 557 { 558 X86CPU *cpu = env_archcpu(env); 559 int intno; 560 561 if (!kvm_irqchip_in_kernel()) { 562 intno = apic_get_interrupt(cpu->apic_state); 563 if (intno >= 0) { 564 return intno; 565 } 566 /* read the irq from the PIC */ 567 if (!apic_accept_pic_intr(cpu->apic_state)) { 568 return -1; 569 } 570 } 571 572 intno = pic_read_irq(isa_pic); 573 return intno; 574 } 575 576 DeviceState *cpu_get_current_apic(void) 577 { 578 if (current_cpu) { 579 X86CPU *cpu = X86_CPU(current_cpu); 580 return cpu->apic_state; 581 } else { 582 return NULL; 583 } 584 } 585 586 void gsi_handler(void *opaque, int n, int level) 587 { 588 GSIState *s = opaque; 589 590 trace_x86_gsi_interrupt(n, level); 591 switch (n) { 592 case 0 ... ISA_NUM_IRQS - 1: 593 if (s->i8259_irq[n]) { 594 /* Under KVM, Kernel will forward to both PIC and IOAPIC */ 595 qemu_set_irq(s->i8259_irq[n], level); 596 } 597 /* fall through */ 598 case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: 599 qemu_set_irq(s->ioapic_irq[n], level); 600 break; 601 case IO_APIC_SECONDARY_IRQBASE 602 ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: 603 qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); 604 break; 605 } 606 } 607 608 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 609 { 610 DeviceState *dev; 611 SysBusDevice *d; 612 unsigned int i; 613 614 assert(parent_name); 615 if (kvm_ioapic_in_kernel()) { 616 dev = qdev_new(TYPE_KVM_IOAPIC); 617 } else { 618 dev = qdev_new(TYPE_IOAPIC); 619 } 620 object_property_add_child(object_resolve_path(parent_name, NULL), 621 "ioapic", OBJECT(dev)); 622 d = SYS_BUS_DEVICE(dev); 623 sysbus_realize_and_unref(d, &error_fatal); 624 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 625 626 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 627 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 628 } 629 } 630 631 DeviceState *ioapic_init_secondary(GSIState *gsi_state) 632 { 633 DeviceState *dev; 634 SysBusDevice *d; 635 unsigned int i; 636 637 dev = qdev_new(TYPE_IOAPIC); 638 d = SYS_BUS_DEVICE(dev); 639 sysbus_realize_and_unref(d, &error_fatal); 640 sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); 641 642 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 643 gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); 644 } 645 return dev; 646 } 647 648 struct setup_data { 649 uint64_t next; 650 uint32_t type; 651 uint32_t len; 652 uint8_t data[]; 653 } __attribute__((packed)); 654 655 656 /* 657 * The entry point into the kernel for PVH boot is different from 658 * the native entry point. The PVH entry is defined by the x86/HVM 659 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 660 * 661 * This function is passed to load_elf() when it is called from 662 * load_elfboot() which then additionally checks for an ELF Note of 663 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 664 * parse the PVH entry address from the ELF Note. 665 * 666 * Due to trickery in elf_opts.h, load_elf() is actually available as 667 * load_elf32() or load_elf64() and this routine needs to be able 668 * to deal with being called as 32 or 64 bit. 669 * 670 * The address of the PVH entry point is saved to the 'pvh_start_addr' 671 * global variable. (although the entry point is 32-bit, the kernel 672 * binary can be either 32-bit or 64-bit). 673 */ 674 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 675 { 676 size_t *elf_note_data_addr; 677 678 /* Check if ELF Note header passed in is valid */ 679 if (arg1 == NULL) { 680 return 0; 681 } 682 683 if (is64) { 684 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 685 uint64_t nhdr_size64 = sizeof(struct elf64_note); 686 uint64_t phdr_align = *(uint64_t *)arg2; 687 uint64_t nhdr_namesz = nhdr64->n_namesz; 688 689 elf_note_data_addr = 690 ((void *)nhdr64) + nhdr_size64 + 691 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 692 } else { 693 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 694 uint32_t nhdr_size32 = sizeof(struct elf32_note); 695 uint32_t phdr_align = *(uint32_t *)arg2; 696 uint32_t nhdr_namesz = nhdr32->n_namesz; 697 698 elf_note_data_addr = 699 ((void *)nhdr32) + nhdr_size32 + 700 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 701 } 702 703 pvh_start_addr = *elf_note_data_addr; 704 705 return pvh_start_addr; 706 } 707 708 static bool load_elfboot(const char *kernel_filename, 709 int kernel_file_size, 710 uint8_t *header, 711 size_t pvh_xen_start_addr, 712 FWCfgState *fw_cfg) 713 { 714 uint32_t flags = 0; 715 uint32_t mh_load_addr = 0; 716 uint32_t elf_kernel_size = 0; 717 uint64_t elf_entry; 718 uint64_t elf_low, elf_high; 719 int kernel_size; 720 721 if (ldl_p(header) != 0x464c457f) { 722 return false; /* no elfboot */ 723 } 724 725 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 726 flags = elf_is64 ? 727 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 728 729 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 730 error_report("elfboot unsupported flags = %x", flags); 731 exit(1); 732 } 733 734 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 735 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 736 NULL, &elf_note_type, &elf_entry, 737 &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, 738 0, 0); 739 740 if (kernel_size < 0) { 741 error_report("Error while loading elf kernel"); 742 exit(1); 743 } 744 mh_load_addr = elf_low; 745 elf_kernel_size = elf_high - elf_low; 746 747 if (pvh_start_addr == 0) { 748 error_report("Error loading uncompressed kernel without PVH ELF Note"); 749 exit(1); 750 } 751 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 752 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 753 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 754 755 return true; 756 } 757 758 void x86_load_linux(X86MachineState *x86ms, 759 FWCfgState *fw_cfg, 760 int acpi_data_size, 761 bool pvh_enabled, 762 bool linuxboot_dma_enabled) 763 { 764 uint16_t protocol; 765 int setup_size, kernel_size, cmdline_size; 766 int dtb_size, setup_data_offset; 767 uint32_t initrd_max; 768 uint8_t header[8192], *setup, *kernel; 769 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 770 FILE *f; 771 char *vmode; 772 MachineState *machine = MACHINE(x86ms); 773 struct setup_data *setup_data; 774 const char *kernel_filename = machine->kernel_filename; 775 const char *initrd_filename = machine->initrd_filename; 776 const char *dtb_filename = machine->dtb; 777 const char *kernel_cmdline = machine->kernel_cmdline; 778 779 /* Align to 16 bytes as a paranoia measure */ 780 cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; 781 782 /* load the kernel header */ 783 f = fopen(kernel_filename, "rb"); 784 if (!f) { 785 fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", 786 kernel_filename, strerror(errno)); 787 exit(1); 788 } 789 790 kernel_size = get_file_size(f); 791 if (!kernel_size || 792 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 793 MIN(ARRAY_SIZE(header), kernel_size)) { 794 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 795 kernel_filename, strerror(errno)); 796 exit(1); 797 } 798 799 /* kernel protocol version */ 800 if (ldl_p(header + 0x202) == 0x53726448) { 801 protocol = lduw_p(header + 0x206); 802 } else { 803 /* 804 * This could be a multiboot kernel. If it is, let's stop treating it 805 * like a Linux kernel. 806 * Note: some multiboot images could be in the ELF format (the same of 807 * PVH), so we try multiboot first since we check the multiboot magic 808 * header before to load it. 809 */ 810 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 811 kernel_cmdline, kernel_size, header)) { 812 return; 813 } 814 /* 815 * Check if the file is an uncompressed kernel file (ELF) and load it, 816 * saving the PVH entry point used by the x86/HVM direct boot ABI. 817 * If load_elfboot() is successful, populate the fw_cfg info. 818 */ 819 if (pvh_enabled && 820 load_elfboot(kernel_filename, kernel_size, 821 header, pvh_start_addr, fw_cfg)) { 822 fclose(f); 823 824 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 825 strlen(kernel_cmdline) + 1); 826 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 827 828 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 829 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 830 header, sizeof(header)); 831 832 /* load initrd */ 833 if (initrd_filename) { 834 GMappedFile *mapped_file; 835 gsize initrd_size; 836 gchar *initrd_data; 837 GError *gerr = NULL; 838 839 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 840 if (!mapped_file) { 841 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 842 initrd_filename, gerr->message); 843 exit(1); 844 } 845 x86ms->initrd_mapped_file = mapped_file; 846 847 initrd_data = g_mapped_file_get_contents(mapped_file); 848 initrd_size = g_mapped_file_get_length(mapped_file); 849 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 850 if (initrd_size >= initrd_max) { 851 fprintf(stderr, "qemu: initrd is too large, cannot support." 852 "(max: %"PRIu32", need %"PRId64")\n", 853 initrd_max, (uint64_t)initrd_size); 854 exit(1); 855 } 856 857 initrd_addr = (initrd_max - initrd_size) & ~4095; 858 859 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 860 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 861 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 862 initrd_size); 863 } 864 865 option_rom[nb_option_roms].bootindex = 0; 866 option_rom[nb_option_roms].name = "pvh.bin"; 867 nb_option_roms++; 868 869 return; 870 } 871 protocol = 0; 872 } 873 874 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 875 /* Low kernel */ 876 real_addr = 0x90000; 877 cmdline_addr = 0x9a000 - cmdline_size; 878 prot_addr = 0x10000; 879 } else if (protocol < 0x202) { 880 /* High but ancient kernel */ 881 real_addr = 0x90000; 882 cmdline_addr = 0x9a000 - cmdline_size; 883 prot_addr = 0x100000; 884 } else { 885 /* High and recent kernel */ 886 real_addr = 0x10000; 887 cmdline_addr = 0x20000; 888 prot_addr = 0x100000; 889 } 890 891 /* highest address for loading the initrd */ 892 if (protocol >= 0x20c && 893 lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 894 /* 895 * Linux has supported initrd up to 4 GB for a very long time (2007, 896 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 897 * though it only sets initrd_max to 2 GB to "work around bootloader 898 * bugs". Luckily, QEMU firmware(which does something like bootloader) 899 * has supported this. 900 * 901 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 902 * be loaded into any address. 903 * 904 * In addition, initrd_max is uint32_t simply because QEMU doesn't 905 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 906 * field). 907 * 908 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 909 */ 910 initrd_max = UINT32_MAX; 911 } else if (protocol >= 0x203) { 912 initrd_max = ldl_p(header + 0x22c); 913 } else { 914 initrd_max = 0x37ffffff; 915 } 916 917 if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { 918 initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; 919 } 920 921 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 922 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); 923 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 924 925 if (protocol >= 0x202) { 926 stl_p(header + 0x228, cmdline_addr); 927 } else { 928 stw_p(header + 0x20, 0xA33F); 929 stw_p(header + 0x22, cmdline_addr - real_addr); 930 } 931 932 /* handle vga= parameter */ 933 vmode = strstr(kernel_cmdline, "vga="); 934 if (vmode) { 935 unsigned int video_mode; 936 const char *end; 937 int ret; 938 /* skip "vga=" */ 939 vmode += 4; 940 if (!strncmp(vmode, "normal", 6)) { 941 video_mode = 0xffff; 942 } else if (!strncmp(vmode, "ext", 3)) { 943 video_mode = 0xfffe; 944 } else if (!strncmp(vmode, "ask", 3)) { 945 video_mode = 0xfffd; 946 } else { 947 ret = qemu_strtoui(vmode, &end, 0, &video_mode); 948 if (ret != 0 || (*end && *end != ' ')) { 949 fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); 950 exit(1); 951 } 952 } 953 stw_p(header + 0x1fa, video_mode); 954 } 955 956 /* loader type */ 957 /* 958 * High nybble = B reserved for QEMU; low nybble is revision number. 959 * If this code is substantially changed, you may want to consider 960 * incrementing the revision. 961 */ 962 if (protocol >= 0x200) { 963 header[0x210] = 0xB0; 964 } 965 /* heap */ 966 if (protocol >= 0x201) { 967 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 968 stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); 969 } 970 971 /* load initrd */ 972 if (initrd_filename) { 973 GMappedFile *mapped_file; 974 gsize initrd_size; 975 gchar *initrd_data; 976 GError *gerr = NULL; 977 978 if (protocol < 0x200) { 979 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 980 exit(1); 981 } 982 983 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 984 if (!mapped_file) { 985 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 986 initrd_filename, gerr->message); 987 exit(1); 988 } 989 x86ms->initrd_mapped_file = mapped_file; 990 991 initrd_data = g_mapped_file_get_contents(mapped_file); 992 initrd_size = g_mapped_file_get_length(mapped_file); 993 if (initrd_size >= initrd_max) { 994 fprintf(stderr, "qemu: initrd is too large, cannot support." 995 "(max: %"PRIu32", need %"PRId64")\n", 996 initrd_max, (uint64_t)initrd_size); 997 exit(1); 998 } 999 1000 initrd_addr = (initrd_max - initrd_size) & ~4095; 1001 1002 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1003 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1004 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1005 1006 stl_p(header + 0x218, initrd_addr); 1007 stl_p(header + 0x21c, initrd_size); 1008 } 1009 1010 /* load kernel and setup */ 1011 setup_size = header[0x1f1]; 1012 if (setup_size == 0) { 1013 setup_size = 4; 1014 } 1015 setup_size = (setup_size + 1) * 512; 1016 if (setup_size > kernel_size) { 1017 fprintf(stderr, "qemu: invalid kernel header\n"); 1018 exit(1); 1019 } 1020 kernel_size -= setup_size; 1021 1022 setup = g_malloc(setup_size); 1023 kernel = g_malloc(kernel_size); 1024 fseek(f, 0, SEEK_SET); 1025 if (fread(setup, 1, setup_size, f) != setup_size) { 1026 fprintf(stderr, "fread() failed\n"); 1027 exit(1); 1028 } 1029 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1030 fprintf(stderr, "fread() failed\n"); 1031 exit(1); 1032 } 1033 fclose(f); 1034 1035 /* append dtb to kernel */ 1036 if (dtb_filename) { 1037 if (protocol < 0x209) { 1038 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1039 exit(1); 1040 } 1041 1042 dtb_size = get_image_size(dtb_filename); 1043 if (dtb_size <= 0) { 1044 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1045 dtb_filename, strerror(errno)); 1046 exit(1); 1047 } 1048 1049 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1050 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1051 kernel = g_realloc(kernel, kernel_size); 1052 1053 stq_p(header + 0x250, prot_addr + setup_data_offset); 1054 1055 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1056 setup_data->next = 0; 1057 setup_data->type = cpu_to_le32(SETUP_DTB); 1058 setup_data->len = cpu_to_le32(dtb_size); 1059 1060 load_image_size(dtb_filename, setup_data->data, dtb_size); 1061 } 1062 1063 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1064 1065 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1066 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1067 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1068 1069 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1070 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1071 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1072 1073 option_rom[nb_option_roms].bootindex = 0; 1074 option_rom[nb_option_roms].name = "linuxboot.bin"; 1075 if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1076 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1077 } 1078 nb_option_roms++; 1079 } 1080 1081 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw) 1082 { 1083 char *filename; 1084 MemoryRegion *bios, *isa_bios; 1085 int bios_size, isa_bios_size; 1086 int ret; 1087 1088 /* BIOS load */ 1089 if (bios_name == NULL) { 1090 bios_name = BIOS_FILENAME; 1091 } 1092 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1093 if (filename) { 1094 bios_size = get_image_size(filename); 1095 } else { 1096 bios_size = -1; 1097 } 1098 if (bios_size <= 0 || 1099 (bios_size % 65536) != 0) { 1100 goto bios_error; 1101 } 1102 bios = g_malloc(sizeof(*bios)); 1103 memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); 1104 if (!isapc_ram_fw) { 1105 memory_region_set_readonly(bios, true); 1106 } 1107 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); 1108 if (ret != 0) { 1109 bios_error: 1110 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); 1111 exit(1); 1112 } 1113 g_free(filename); 1114 1115 /* map the last 128KB of the BIOS in ISA space */ 1116 isa_bios_size = MIN(bios_size, 128 * KiB); 1117 isa_bios = g_malloc(sizeof(*isa_bios)); 1118 memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, 1119 bios_size - isa_bios_size, isa_bios_size); 1120 memory_region_add_subregion_overlap(rom_memory, 1121 0x100000 - isa_bios_size, 1122 isa_bios, 1123 1); 1124 if (!isapc_ram_fw) { 1125 memory_region_set_readonly(isa_bios, true); 1126 } 1127 1128 /* map all the bios at the top of memory */ 1129 memory_region_add_subregion(rom_memory, 1130 (uint32_t)(-bios_size), 1131 bios); 1132 } 1133 1134 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) 1135 { 1136 bool smm_available = false; 1137 1138 if (x86ms->smm == ON_OFF_AUTO_OFF) { 1139 return false; 1140 } 1141 1142 if (tcg_enabled() || qtest_enabled()) { 1143 smm_available = true; 1144 } else if (kvm_enabled()) { 1145 smm_available = kvm_has_smm(); 1146 } 1147 1148 if (smm_available) { 1149 return true; 1150 } 1151 1152 if (x86ms->smm == ON_OFF_AUTO_ON) { 1153 error_report("System Management Mode not supported by this hypervisor."); 1154 exit(1); 1155 } 1156 return false; 1157 } 1158 1159 static void x86_machine_get_smm(Object *obj, Visitor *v, const char *name, 1160 void *opaque, Error **errp) 1161 { 1162 X86MachineState *x86ms = X86_MACHINE(obj); 1163 OnOffAuto smm = x86ms->smm; 1164 1165 visit_type_OnOffAuto(v, name, &smm, errp); 1166 } 1167 1168 static void x86_machine_set_smm(Object *obj, Visitor *v, const char *name, 1169 void *opaque, Error **errp) 1170 { 1171 X86MachineState *x86ms = X86_MACHINE(obj); 1172 1173 visit_type_OnOffAuto(v, name, &x86ms->smm, errp); 1174 } 1175 1176 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms) 1177 { 1178 if (x86ms->acpi == ON_OFF_AUTO_OFF) { 1179 return false; 1180 } 1181 return true; 1182 } 1183 1184 static void x86_machine_get_acpi(Object *obj, Visitor *v, const char *name, 1185 void *opaque, Error **errp) 1186 { 1187 X86MachineState *x86ms = X86_MACHINE(obj); 1188 OnOffAuto acpi = x86ms->acpi; 1189 1190 visit_type_OnOffAuto(v, name, &acpi, errp); 1191 } 1192 1193 static void x86_machine_set_acpi(Object *obj, Visitor *v, const char *name, 1194 void *opaque, Error **errp) 1195 { 1196 X86MachineState *x86ms = X86_MACHINE(obj); 1197 1198 visit_type_OnOffAuto(v, name, &x86ms->acpi, errp); 1199 } 1200 1201 static void x86_machine_initfn(Object *obj) 1202 { 1203 X86MachineState *x86ms = X86_MACHINE(obj); 1204 1205 x86ms->smm = ON_OFF_AUTO_AUTO; 1206 x86ms->acpi = ON_OFF_AUTO_AUTO; 1207 x86ms->smp_dies = 1; 1208 x86ms->pci_irq_mask = ACPI_BUILD_PCI_IRQS; 1209 } 1210 1211 static void x86_machine_class_init(ObjectClass *oc, void *data) 1212 { 1213 MachineClass *mc = MACHINE_CLASS(oc); 1214 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1215 NMIClass *nc = NMI_CLASS(oc); 1216 1217 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1218 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1219 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1220 x86mc->compat_apic_id_mode = false; 1221 x86mc->save_tsc_khz = true; 1222 nc->nmi_monitor_handler = x86_nmi; 1223 1224 object_class_property_add(oc, X86_MACHINE_SMM, "OnOffAuto", 1225 x86_machine_get_smm, x86_machine_set_smm, 1226 NULL, NULL); 1227 object_class_property_set_description(oc, X86_MACHINE_SMM, 1228 "Enable SMM"); 1229 1230 object_class_property_add(oc, X86_MACHINE_ACPI, "OnOffAuto", 1231 x86_machine_get_acpi, x86_machine_set_acpi, 1232 NULL, NULL); 1233 object_class_property_set_description(oc, X86_MACHINE_ACPI, 1234 "Enable ACPI"); 1235 } 1236 1237 static const TypeInfo x86_machine_info = { 1238 .name = TYPE_X86_MACHINE, 1239 .parent = TYPE_MACHINE, 1240 .abstract = true, 1241 .instance_size = sizeof(X86MachineState), 1242 .instance_init = x86_machine_initfn, 1243 .class_size = sizeof(X86MachineClass), 1244 .class_init = x86_machine_class_init, 1245 .interfaces = (InterfaceInfo[]) { 1246 { TYPE_NMI }, 1247 { } 1248 }, 1249 }; 1250 1251 static void x86_machine_register_types(void) 1252 { 1253 type_register_static(&x86_machine_info); 1254 } 1255 1256 type_init(x86_machine_register_types) 1257