1 /* 2 * QEMU emulation of common X86 IOMMU 3 * 4 * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "hw/boards.h" 23 #include "hw/i386/x86-iommu.h" 24 #include "hw/i386/pc.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "trace.h" 28 #include "sysemu/kvm.h" 29 30 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu, 31 iec_notify_fn fn, void *data) 32 { 33 IEC_Notifier *notifier = g_new0(IEC_Notifier, 1); 34 35 notifier->iec_notify = fn; 36 notifier->private = data; 37 38 QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list); 39 } 40 41 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global, 42 uint32_t index, uint32_t mask) 43 { 44 IEC_Notifier *notifier; 45 46 trace_x86_iommu_iec_notify(global, index, mask); 47 48 QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) { 49 if (notifier->iec_notify) { 50 notifier->iec_notify(notifier->private, global, 51 index, mask); 52 } 53 } 54 } 55 56 /* Generate one MSI message from VTDIrq info */ 57 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *msg_out) 58 { 59 X86IOMMU_MSIMessage msg = {}; 60 61 /* Generate address bits */ 62 msg.dest_mode = irq->dest_mode; 63 msg.redir_hint = irq->redir_hint; 64 msg.dest = irq->dest; 65 msg.__addr_hi = irq->dest & 0xffffff00; 66 msg.__addr_head = cpu_to_le32(0xfee); 67 /* Keep this from original MSI address bits */ 68 msg.__not_used = irq->msi_addr_last_bits; 69 70 /* Generate data bits */ 71 msg.vector = irq->vector; 72 msg.delivery_mode = irq->delivery_mode; 73 msg.level = 1; 74 msg.trigger_mode = irq->trigger_mode; 75 76 msg_out->address = msg.msi_addr; 77 msg_out->data = msg.msi_data; 78 } 79 80 /* Default X86 IOMMU device */ 81 static X86IOMMUState *x86_iommu_default = NULL; 82 83 static void x86_iommu_set_default(X86IOMMUState *x86_iommu) 84 { 85 assert(x86_iommu); 86 87 if (x86_iommu_default) { 88 error_report("QEMU does not support multiple vIOMMUs " 89 "for x86 yet."); 90 exit(1); 91 } 92 93 x86_iommu_default = x86_iommu; 94 } 95 96 X86IOMMUState *x86_iommu_get_default(void) 97 { 98 return x86_iommu_default; 99 } 100 101 IommuType x86_iommu_get_type(void) 102 { 103 return x86_iommu_default->type; 104 } 105 106 static void x86_iommu_realize(DeviceState *dev, Error **errp) 107 { 108 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 109 X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev); 110 MachineState *ms = MACHINE(qdev_get_machine()); 111 MachineClass *mc = MACHINE_GET_CLASS(ms); 112 PCMachineState *pcms = 113 PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)); 114 QLIST_INIT(&x86_iommu->iec_notifiers); 115 bool irq_all_kernel = kvm_irqchip_in_kernel() && !kvm_irqchip_is_split(); 116 117 if (!pcms || !pcms->bus) { 118 error_setg(errp, "Machine-type '%s' not supported by IOMMU", 119 mc->name); 120 return; 121 } 122 123 /* If the user didn't specify IR, choose a default value for it */ 124 if (x86_iommu->intr_supported == ON_OFF_AUTO_AUTO) { 125 x86_iommu->intr_supported = irq_all_kernel ? 126 ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 127 } 128 129 /* Both Intel and AMD IOMMU IR only support "kernel-irqchip={off|split}" */ 130 if (x86_iommu_ir_supported(x86_iommu) && irq_all_kernel) { 131 error_setg(errp, "Interrupt Remapping cannot work with " 132 "kernel-irqchip=on, please use 'split|off'."); 133 return; 134 } 135 136 if (x86_class->realize) { 137 x86_class->realize(dev, errp); 138 } 139 140 x86_iommu_set_default(X86_IOMMU_DEVICE(dev)); 141 } 142 143 static Property x86_iommu_properties[] = { 144 DEFINE_PROP_ON_OFF_AUTO("intremap", X86IOMMUState, 145 intr_supported, ON_OFF_AUTO_AUTO), 146 DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), 147 DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), 148 DEFINE_PROP_END_OF_LIST(), 149 }; 150 151 static void x86_iommu_class_init(ObjectClass *klass, void *data) 152 { 153 DeviceClass *dc = DEVICE_CLASS(klass); 154 dc->realize = x86_iommu_realize; 155 dc->props = x86_iommu_properties; 156 } 157 158 bool x86_iommu_ir_supported(X86IOMMUState *s) 159 { 160 return s->intr_supported == ON_OFF_AUTO_ON; 161 } 162 163 static const TypeInfo x86_iommu_info = { 164 .name = TYPE_X86_IOMMU_DEVICE, 165 .parent = TYPE_SYS_BUS_DEVICE, 166 .instance_size = sizeof(X86IOMMUState), 167 .class_init = x86_iommu_class_init, 168 .class_size = sizeof(X86IOMMUClass), 169 .abstract = true, 170 }; 171 172 static void x86_iommu_register_types(void) 173 { 174 type_register_static(&x86_iommu_info); 175 } 176 177 type_init(x86_iommu_register_types) 178