1 /* 2 * QEMU emulation of common X86 IOMMU 3 * 4 * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/sysbus.h" 22 #include "hw/boards.h" 23 #include "hw/i386/x86-iommu.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/i386/pc.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "trace.h" 29 #include "sysemu/kvm.h" 30 31 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu, 32 iec_notify_fn fn, void *data) 33 { 34 IEC_Notifier *notifier = g_new0(IEC_Notifier, 1); 35 36 notifier->iec_notify = fn; 37 notifier->private = data; 38 39 QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list); 40 } 41 42 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global, 43 uint32_t index, uint32_t mask) 44 { 45 IEC_Notifier *notifier; 46 47 trace_x86_iommu_iec_notify(global, index, mask); 48 49 QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) { 50 if (notifier->iec_notify) { 51 notifier->iec_notify(notifier->private, global, 52 index, mask); 53 } 54 } 55 } 56 57 /* Generate one MSI message from VTDIrq info */ 58 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *msg_out) 59 { 60 X86IOMMU_MSIMessage msg = {}; 61 62 /* Generate address bits */ 63 msg.dest_mode = irq->dest_mode; 64 msg.redir_hint = irq->redir_hint; 65 msg.dest = irq->dest; 66 msg.__addr_hi = irq->dest & 0xffffff00; 67 msg.__addr_head = cpu_to_le32(0xfee); 68 /* Keep this from original MSI address bits */ 69 msg.__not_used = irq->msi_addr_last_bits; 70 71 /* Generate data bits */ 72 msg.vector = irq->vector; 73 msg.delivery_mode = irq->delivery_mode; 74 msg.level = 1; 75 msg.trigger_mode = irq->trigger_mode; 76 77 msg_out->address = msg.msi_addr; 78 msg_out->data = msg.msi_data; 79 } 80 81 /* Default X86 IOMMU device */ 82 static X86IOMMUState *x86_iommu_default = NULL; 83 84 static void x86_iommu_set_default(X86IOMMUState *x86_iommu) 85 { 86 assert(x86_iommu); 87 88 if (x86_iommu_default) { 89 error_report("QEMU does not support multiple vIOMMUs " 90 "for x86 yet."); 91 exit(1); 92 } 93 94 x86_iommu_default = x86_iommu; 95 } 96 97 X86IOMMUState *x86_iommu_get_default(void) 98 { 99 return x86_iommu_default; 100 } 101 102 IommuType x86_iommu_get_type(void) 103 { 104 return x86_iommu_default->type; 105 } 106 107 static void x86_iommu_realize(DeviceState *dev, Error **errp) 108 { 109 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev); 110 X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev); 111 MachineState *ms = MACHINE(qdev_get_machine()); 112 MachineClass *mc = MACHINE_GET_CLASS(ms); 113 PCMachineState *pcms = 114 PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)); 115 QLIST_INIT(&x86_iommu->iec_notifiers); 116 bool irq_all_kernel = kvm_irqchip_in_kernel() && !kvm_irqchip_is_split(); 117 118 if (!pcms || !pcms->bus) { 119 error_setg(errp, "Machine-type '%s' not supported by IOMMU", 120 mc->name); 121 return; 122 } 123 124 /* If the user didn't specify IR, choose a default value for it */ 125 if (x86_iommu->intr_supported == ON_OFF_AUTO_AUTO) { 126 x86_iommu->intr_supported = irq_all_kernel ? 127 ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 128 } 129 130 /* Both Intel and AMD IOMMU IR only support "kernel-irqchip={off|split}" */ 131 if (x86_iommu_ir_supported(x86_iommu) && irq_all_kernel) { 132 error_setg(errp, "Interrupt Remapping cannot work with " 133 "kernel-irqchip=on, please use 'split|off'."); 134 return; 135 } 136 137 if (x86_class->realize) { 138 x86_class->realize(dev, errp); 139 } 140 141 x86_iommu_set_default(X86_IOMMU_DEVICE(dev)); 142 } 143 144 static Property x86_iommu_properties[] = { 145 DEFINE_PROP_ON_OFF_AUTO("intremap", X86IOMMUState, 146 intr_supported, ON_OFF_AUTO_AUTO), 147 DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), 148 DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), 149 DEFINE_PROP_END_OF_LIST(), 150 }; 151 152 static void x86_iommu_class_init(ObjectClass *klass, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(klass); 155 dc->realize = x86_iommu_realize; 156 dc->props = x86_iommu_properties; 157 } 158 159 bool x86_iommu_ir_supported(X86IOMMUState *s) 160 { 161 return s->intr_supported == ON_OFF_AUTO_ON; 162 } 163 164 static const TypeInfo x86_iommu_info = { 165 .name = TYPE_X86_IOMMU_DEVICE, 166 .parent = TYPE_SYS_BUS_DEVICE, 167 .instance_size = sizeof(X86IOMMUState), 168 .class_init = x86_iommu_class_init, 169 .class_size = sizeof(X86IOMMUClass), 170 .abstract = true, 171 }; 172 173 static void x86_iommu_register_types(void) 174 { 175 type_register_static(&x86_iommu_info); 176 } 177 178 type_init(x86_iommu_register_types) 179