xref: /openbmc/qemu/hw/i386/trace-events (revision d61e45ec)
1e723b871SLaurent Vivier# See docs/tracing.txt for syntax documentation.
25eb76e48SDaniel P. Berrange
35eb76e48SDaniel P. Berrange# hw/i386/xen/xen_platform.c
45eb76e48SDaniel P. Berrangexen_platform_log(char *s) "xen platform: %s"
55eb76e48SDaniel P. Berrange
65eb76e48SDaniel P. Berrange# hw/i386/xen/xen_pvdevice.c
75eb76e48SDaniel P. Berrangexen_pv_mmio_read(uint64_t addr) "WARNING: read from Xen PV Device MMIO space (address %"PRIx64")"
85eb76e48SDaniel P. Berrangexen_pv_mmio_write(uint64_t addr) "WARNING: write to Xen PV Device MMIO space (address %"PRIx64")"
95eb76e48SDaniel P. Berrange
105eb76e48SDaniel P. Berrange# hw/i386/pc.c
11deff0ddbSLaurent Viviermhp_pc_dimm_assigned_slot(int slot) "%d"
125eb76e48SDaniel P. Berrangemhp_pc_dimm_assigned_address(uint64_t addr) "0x%"PRIx64
1302a2cbc8SPeter Xu
1402a2cbc8SPeter Xu# hw/i386/x86-iommu.c
1502a2cbc8SPeter Xux86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%d index=%" PRIu32 " mask=%" PRIu32
16*d61e45ecSDavid Kiarie
17*d61e45ecSDavid Kiarie# hw/i386/amd_iommu.c
18*d61e45ecSDavid Kiarieamdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" +  offset 0x%"PRIx32
19*d61e45ecSDavid Kiarieamdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t slot, uint8_t func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx16" devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
20*d61e45ecSDavid Kiarieamdvi_completion_wait_fail(uint64_t addr) "error: fail to write at address 0x%"PRIx64
21*d61e45ecSDavid Kiarieamdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, uint64_t val, uint64_t offset) "%s write addr 0x%"PRIx64", size %u, val 0x%"PRIx64", offset 0x%"PRIx64
22*d61e45ecSDavid Kiarieamdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, uint64_t offset) "%s read addr 0x%"PRIx64", size %u offset 0x%"PRIx64
23*d61e45ecSDavid Kiarieamdvi_command_error(uint64_t status) "error: Executing commands with command buffer disabled 0x%"PRIx64
24*d61e45ecSDavid Kiarieamdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fail to access memory at 0x%"PRIx64" + 0x%"PRIx32
25*d61e45ecSDavid Kiarieamdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "command buffer head at 0x%"PRIx32" command buffer tail at 0x%"PRIx32" command buffer base at 0x%"PRIx64
26*d61e45ecSDavid Kiarieamdvi_unhandled_command(uint8_t type) "unhandled command 0x%"PRIx8
27*d61e45ecSDavid Kiarieamdvi_intr_inval(void) "Interrupt table invalidated"
28*d61e45ecSDavid Kiarieamdvi_iotlb_inval(void) "IOTLB pages invalidated"
29*d61e45ecSDavid Kiarieamdvi_prefetch_pages(void) "Pre-fetch of AMD-Vi pages requested"
30*d61e45ecSDavid Kiarieamdvi_pages_inval(uint16_t domid) "AMD-Vi pages for domain 0x%"PRIx16 " invalidated"
31*d61e45ecSDavid Kiarieamdvi_all_inval(void) "Invalidation of all AMD-Vi cache requested "
32*d61e45ecSDavid Kiarieamdvi_ppr_exec(void) "Execution of PPR queue requested "
33*d61e45ecSDavid Kiarieamdvi_devtab_inval(uint8_t bus, uint8_t slot, uint8_t func) "device table entry for devid: %02x:%02x.%x invalidated"
34*d61e45ecSDavid Kiarieamdvi_completion_wait(uint64_t addr, uint64_t data) "completion wait requested with store address 0x%"PRIx64" and store data 0x%"PRIx64
35*d61e45ecSDavid Kiarieamdvi_control_status(uint64_t val) "MMIO_STATUS state 0x%"PRIx64
36*d61e45ecSDavid Kiarieamdvi_iotlb_reset(void) "IOTLB exceed size limit - reset "
37*d61e45ecSDavid Kiarieamdvi_completion_wait_exec(uint64_t addr, uint64_t data) "completion wait requested with store address 0x%"PRIx64" and store data 0x%"PRIx64
38*d61e45ecSDavid Kiarieamdvi_dte_get_fail(uint64_t addr, uint32_t offset) "error: failed to access Device Entry devtab 0x%"PRIx64" offset 0x%"PRIx32
39*d61e45ecSDavid Kiarieamdvi_invalid_dte(uint64_t addr) "PTE entry at 0x%"PRIx64" is invalid "
40*d61e45ecSDavid Kiarieamdvi_get_pte_hwerror(uint64_t addr) "hardware error eccessing PTE at addr 0x%"PRIx64
41*d61e45ecSDavid Kiarieamdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PRIx8" translating addr 0x%"PRIx64
42*d61e45ecSDavid Kiarieamdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64
43*d61e45ecSDavid Kiarieamdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
44*d61e45ecSDavid Kiarieamdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
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