1e723b871SLaurent Vivier# See docs/tracing.txt for syntax documentation. 25eb76e48SDaniel P. Berrange 302a2cbc8SPeter Xu# hw/i386/x86-iommu.c 402a2cbc8SPeter Xux86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%d index=%" PRIu32 " mask=%" PRIu32 5d61e45ecSDavid Kiarie 6*bc535e59SPeter Xu# hw/i386/intel_iommu.c 7*bc535e59SPeter Xuvtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)" 8*bc535e59SPeter Xuvtd_inv_desc(const char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" low 0x%"PRIx64 9*bc535e59SPeter Xuvtd_inv_desc_invalid(uint64_t hi, uint64_t lo) "invalid inv desc hi 0x%"PRIx64" lo 0x%"PRIx64 10*bc535e59SPeter Xuvtd_inv_desc_cc_domain(uint16_t domain) "context invalidate domain 0x%"PRIx16 11*bc535e59SPeter Xuvtd_inv_desc_cc_global(void) "context invalidate globally" 12*bc535e59SPeter Xuvtd_inv_desc_cc_device(uint8_t bus, uint8_t dev, uint8_t fn) "context invalidate device %02"PRIx8":%02"PRIx8".%02"PRIx8 13*bc535e59SPeter Xuvtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "context invalidate devices sid 0x%"PRIx16" fmask 0x%"PRIx16 14*bc535e59SPeter Xuvtd_inv_desc_cc_invalid(uint64_t hi, uint64_t lo) "invalid context-cache desc hi 0x%"PRIx64" lo 0x%"PRIx64 15*bc535e59SPeter Xuvtd_inv_desc_iotlb_global(void) "iotlb invalidate global" 16*bc535e59SPeter Xuvtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16 17*bc535e59SPeter Xuvtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8 18*bc535e59SPeter Xuvtd_inv_desc_iotlb_invalid(uint64_t hi, uint64_t lo) "invalid iotlb desc hi 0x%"PRIx64" lo 0x%"PRIx64 19*bc535e59SPeter Xuvtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32 20*bc535e59SPeter Xuvtd_inv_desc_wait_irq(const char *msg) "%s" 21*bc535e59SPeter Xuvtd_inv_desc_wait_invalid(uint64_t hi, uint64_t lo) "invalid wait desc hi 0x%"PRIx64" lo 0x%"PRIx64 22*bc535e59SPeter Xuvtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64 23*bc535e59SPeter Xu 24d61e45ecSDavid Kiarie# hw/i386/amd_iommu.c 25d61e45ecSDavid Kiarieamdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32 26d61e45ecSDavid Kiarieamdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t slot, uint8_t func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx16" devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 27d61e45ecSDavid Kiarieamdvi_completion_wait_fail(uint64_t addr) "error: fail to write at address 0x%"PRIx64 28d61e45ecSDavid Kiarieamdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, uint64_t val, uint64_t offset) "%s write addr 0x%"PRIx64", size %u, val 0x%"PRIx64", offset 0x%"PRIx64 29d61e45ecSDavid Kiarieamdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, uint64_t offset) "%s read addr 0x%"PRIx64", size %u offset 0x%"PRIx64 30d61e45ecSDavid Kiarieamdvi_command_error(uint64_t status) "error: Executing commands with command buffer disabled 0x%"PRIx64 31d61e45ecSDavid Kiarieamdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fail to access memory at 0x%"PRIx64" + 0x%"PRIx32 32d61e45ecSDavid Kiarieamdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "command buffer head at 0x%"PRIx32" command buffer tail at 0x%"PRIx32" command buffer base at 0x%"PRIx64 33d61e45ecSDavid Kiarieamdvi_unhandled_command(uint8_t type) "unhandled command 0x%"PRIx8 34d61e45ecSDavid Kiarieamdvi_intr_inval(void) "Interrupt table invalidated" 35d61e45ecSDavid Kiarieamdvi_iotlb_inval(void) "IOTLB pages invalidated" 36d61e45ecSDavid Kiarieamdvi_prefetch_pages(void) "Pre-fetch of AMD-Vi pages requested" 37d61e45ecSDavid Kiarieamdvi_pages_inval(uint16_t domid) "AMD-Vi pages for domain 0x%"PRIx16 " invalidated" 38d61e45ecSDavid Kiarieamdvi_all_inval(void) "Invalidation of all AMD-Vi cache requested " 39d61e45ecSDavid Kiarieamdvi_ppr_exec(void) "Execution of PPR queue requested " 40d61e45ecSDavid Kiarieamdvi_devtab_inval(uint8_t bus, uint8_t slot, uint8_t func) "device table entry for devid: %02x:%02x.%x invalidated" 41d61e45ecSDavid Kiarieamdvi_completion_wait(uint64_t addr, uint64_t data) "completion wait requested with store address 0x%"PRIx64" and store data 0x%"PRIx64 42d61e45ecSDavid Kiarieamdvi_control_status(uint64_t val) "MMIO_STATUS state 0x%"PRIx64 43d61e45ecSDavid Kiarieamdvi_iotlb_reset(void) "IOTLB exceed size limit - reset " 44d61e45ecSDavid Kiarieamdvi_dte_get_fail(uint64_t addr, uint32_t offset) "error: failed to access Device Entry devtab 0x%"PRIx64" offset 0x%"PRIx32 45d61e45ecSDavid Kiarieamdvi_invalid_dte(uint64_t addr) "PTE entry at 0x%"PRIx64" is invalid " 46d61e45ecSDavid Kiarieamdvi_get_pte_hwerror(uint64_t addr) "hardware error eccessing PTE at addr 0x%"PRIx64 47d61e45ecSDavid Kiarieamdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PRIx8" translating addr 0x%"PRIx64 48d61e45ecSDavid Kiarieamdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 49d61e45ecSDavid Kiarieamdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 50d61e45ecSDavid Kiarieamdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 51