1d0fb9657SStefano Garzarella# See docs/devel/tracing.rst for syntax documentation. 25eb76e48SDaniel P. Berrange 3500016e5SMarkus Armbruster# x86-iommu.c 402a2cbc8SPeter Xux86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%d index=%" PRIu32 " mask=%" PRIu32 5d61e45ecSDavid Kiarie 6500016e5SMarkus Armbruster# intel_iommu.c 7bc535e59SPeter Xuvtd_inv_desc(const char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" low 0x%"PRIx64 8bc535e59SPeter Xuvtd_inv_desc_cc_domain(uint16_t domain) "context invalidate domain 0x%"PRIx16 9bc535e59SPeter Xuvtd_inv_desc_cc_global(void) "context invalidate globally" 10bc535e59SPeter Xuvtd_inv_desc_cc_device(uint8_t bus, uint8_t dev, uint8_t fn) "context invalidate device %02"PRIx8":%02"PRIx8".%02"PRIx8 11bc535e59SPeter Xuvtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "context invalidate devices sid 0x%"PRIx16" fmask 0x%"PRIx16 12bc535e59SPeter Xuvtd_inv_desc_iotlb_global(void) "iotlb invalidate global" 13bc535e59SPeter Xuvtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16 14bc535e59SPeter Xuvtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8 15*1b2b1237SJason Wangvtd_inv_desc_iotlb_pasid_pages(uint16_t domain, uint64_t addr, uint8_t mask, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8" pasid 0x%"PRIx32 16*1b2b1237SJason Wangvtd_inv_desc_iotlb_pasid(uint16_t domain, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" pasid 0x%"PRIx32 17bc535e59SPeter Xuvtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32 18bc535e59SPeter Xuvtd_inv_desc_wait_irq(const char *msg) "%s" 19bc535e59SPeter Xuvtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64 207feb51b7SPeter Xuvtd_inv_desc_iec(uint32_t granularity, uint32_t index, uint32_t mask) "granularity 0x%"PRIx32" index 0x%"PRIx32" mask 0x%"PRIx32 217feb51b7SPeter Xuvtd_inv_qi_enable(bool enable) "enabled %d" 227feb51b7SPeter Xuvtd_inv_qi_setup(uint64_t addr, int size) "addr 0x%"PRIx64" size %d" 237feb51b7SPeter Xuvtd_inv_qi_head(uint16_t head) "read head %d" 247feb51b7SPeter Xuvtd_inv_qi_tail(uint16_t head) "write tail %d" 257feb51b7SPeter Xuvtd_inv_qi_fetch(void) "" 267feb51b7SPeter Xuvtd_context_cache_reset(void) "" 276c441e1dSPeter Xuvtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" 286c441e1dSPeter Xuvtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present" 296c441e1dSPeter Xuvtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16 306c441e1dSPeter Xuvtd_iotlb_page_update(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page update sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16 316c441e1dSPeter Xuvtd_iotlb_cc_hit(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen) "IOTLB context hit bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32 326c441e1dSPeter Xuvtd_iotlb_cc_update(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen1, uint32_t gen2) "IOTLB context update bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32" -> gen %"PRIu32 336c441e1dSPeter Xuvtd_iotlb_reset(const char *reason) "IOTLB reset (reason: %s)" 346c441e1dSPeter Xuvtd_fault_disabled(void) "Fault processing disabled for context entry" 35fb43cf73SLiu, Yi Lvtd_replay_ce_valid(const char *mode, uint8_t bus, uint8_t dev, uint8_t fn, uint16_t domain, uint64_t hi, uint64_t lo) "%s: replay valid context device %02"PRIx8":%02"PRIx8".%02"PRIx8" domain 0x%"PRIx16" hi 0x%"PRIx64" lo 0x%"PRIx64 36f06a696dSPeter Xuvtd_replay_ce_invalid(uint8_t bus, uint8_t dev, uint8_t fn) "replay invalid context device %02"PRIx8":%02"PRIx8".%02"PRIx8 37f06a696dSPeter Xuvtd_page_walk_level(uint64_t addr, uint32_t level, uint64_t start, uint64_t end) "walk (base=0x%"PRIx64", level=%"PRIu32") iova range 0x%"PRIx64" - 0x%"PRIx64 382539eadeSPhilippe Mathieu-Daudévtd_page_walk_one(uint16_t domain, uint64_t iova, uint64_t gpa, uint64_t mask, int perm) "domain 0x%"PRIx16" iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mask 0x%"PRIx64" perm %d" 3963b88968SPeter Xuvtd_page_walk_one_skip_map(uint64_t iova, uint64_t mask, uint64_t translated) "iova 0x%"PRIx64" mask 0x%"PRIx64" translated 0x%"PRIx64 4063b88968SPeter Xuvtd_page_walk_one_skip_unmap(uint64_t iova, uint64_t mask) "iova 0x%"PRIx64" mask 0x%"PRIx64 41f06a696dSPeter Xuvtd_page_walk_skip_read(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to unable to read" 42f06a696dSPeter Xuvtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64" due to rsrv set" 43558e0024SPeter Xuvtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)" 44dd4d607eSPeter Xuvtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64 452539eadeSPhilippe Mathieu-Daudévtd_translate_pt(uint16_t sid, uint64_t addr) "source id 0x%"PRIx16", iova 0x%"PRIx64 462539eadeSPhilippe Mathieu-Daudévtd_pt_enable_fast_path(uint16_t sid, bool success) "sid 0x%"PRIx16" %d" 477feb51b7SPeter Xuvtd_irq_generate(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64 487feb51b7SPeter Xuvtd_reg_read(uint64_t addr, uint64_t size) "addr 0x%"PRIx64" size 0x%"PRIx64 497feb51b7SPeter Xuvtd_reg_write(uint64_t addr, uint64_t size, uint64_t val) "addr 0x%"PRIx64" size 0x%"PRIx64" value 0x%"PRIx64 5081fb1e64SPeter Xuvtd_reg_dmar_root(uint64_t addr, bool scalable) "addr 0x%"PRIx64" scalable %d" 517feb51b7SPeter Xuvtd_reg_ir_root(uint64_t addr, uint32_t size) "addr 0x%"PRIx64" size 0x%"PRIx32 527feb51b7SPeter Xuvtd_reg_write_gcmd(uint32_t status, uint32_t val) "status 0x%"PRIx32" value 0x%"PRIx32 537feb51b7SPeter Xuvtd_reg_write_fectl(uint32_t value) "value 0x%"PRIx32 547feb51b7SPeter Xuvtd_reg_write_iectl(uint32_t value) "value 0x%"PRIx32 557feb51b7SPeter Xuvtd_reg_ics_clear_ip(void) "" 567feb51b7SPeter Xuvtd_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova, uint64_t gpa, uint64_t mask) "dev %02x:%02x.%02x iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mask 0x%"PRIx64 577feb51b7SPeter Xuvtd_dmar_enable(bool en) "enable %d" 587feb51b7SPeter Xuvtd_dmar_fault(uint16_t sid, int fault, uint64_t addr, bool is_write) "sid 0x%"PRIx16" fault %d addr 0x%"PRIx64" write %d" 597feb51b7SPeter Xuvtd_ir_enable(bool en) "enable %d" 607feb51b7SPeter Xuvtd_ir_irte_get(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64 617feb51b7SPeter Xuvtd_ir_remap(int index, int tri, int vec, int deliver, uint32_t dest, int dest_mode) "index %d trigger %d vector %d deliver %d dest 0x%"PRIx32" mode %d" 627feb51b7SPeter Xuvtd_ir_remap_type(const char *type) "%s" 637feb51b7SPeter Xuvtd_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")" 647feb51b7SPeter Xuvtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64 657feb51b7SPeter Xuvtd_fsts_ppf(bool set) "FSTS PPF bit set to %d" 667feb51b7SPeter Xuvtd_fsts_clear_ip(void) "" 677feb51b7SPeter Xuvtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64 688991c460SLadi Prosekvtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 697feb51b7SPeter Xuvtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"PRIx16" index %d vec %d (should be: %d)" 707feb51b7SPeter Xuvtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x%"PRIx16" index %d trigger %d (should be: %d)" 71bc535e59SPeter Xu 72500016e5SMarkus Armbruster# amd_iommu.c 73d61e45ecSDavid Kiarieamdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32 74d61e45ecSDavid Kiarieamdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t slot, uint8_t func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx16" devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 75d61e45ecSDavid Kiarieamdvi_completion_wait_fail(uint64_t addr) "error: fail to write at address 0x%"PRIx64 76d61e45ecSDavid Kiarieamdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, uint64_t val, uint64_t offset) "%s write addr 0x%"PRIx64", size %u, val 0x%"PRIx64", offset 0x%"PRIx64 77d61e45ecSDavid Kiarieamdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, uint64_t offset) "%s read addr 0x%"PRIx64", size %u offset 0x%"PRIx64 780d3ef788SEric Blakeamdvi_mmio_read_invalid(int max, uint64_t addr, unsigned size) "error: addr outside region (max 0x%x): read addr 0x%" PRIx64 ", size %u" 79d61e45ecSDavid Kiarieamdvi_command_error(uint64_t status) "error: Executing commands with command buffer disabled 0x%"PRIx64 80d61e45ecSDavid Kiarieamdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fail to access memory at 0x%"PRIx64" + 0x%"PRIx32 81d61e45ecSDavid Kiarieamdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "command buffer head at 0x%"PRIx32" command buffer tail at 0x%"PRIx32" command buffer base at 0x%"PRIx64 82d61e45ecSDavid Kiarieamdvi_unhandled_command(uint8_t type) "unhandled command 0x%"PRIx8 83d61e45ecSDavid Kiarieamdvi_intr_inval(void) "Interrupt table invalidated" 84d61e45ecSDavid Kiarieamdvi_iotlb_inval(void) "IOTLB pages invalidated" 85d61e45ecSDavid Kiarieamdvi_prefetch_pages(void) "Pre-fetch of AMD-Vi pages requested" 86d61e45ecSDavid Kiarieamdvi_pages_inval(uint16_t domid) "AMD-Vi pages for domain 0x%"PRIx16 " invalidated" 87d61e45ecSDavid Kiarieamdvi_all_inval(void) "Invalidation of all AMD-Vi cache requested " 88d61e45ecSDavid Kiarieamdvi_ppr_exec(void) "Execution of PPR queue requested " 89d61e45ecSDavid Kiarieamdvi_devtab_inval(uint8_t bus, uint8_t slot, uint8_t func) "device table entry for devid: %02x:%02x.%x invalidated" 90d61e45ecSDavid Kiarieamdvi_completion_wait(uint64_t addr, uint64_t data) "completion wait requested with store address 0x%"PRIx64" and store data 0x%"PRIx64 91d61e45ecSDavid Kiarieamdvi_control_status(uint64_t val) "MMIO_STATUS state 0x%"PRIx64 92d61e45ecSDavid Kiarieamdvi_iotlb_reset(void) "IOTLB exceed size limit - reset " 93d61e45ecSDavid Kiarieamdvi_dte_get_fail(uint64_t addr, uint32_t offset) "error: failed to access Device Entry devtab 0x%"PRIx64" offset 0x%"PRIx32 94d61e45ecSDavid Kiarieamdvi_invalid_dte(uint64_t addr) "PTE entry at 0x%"PRIx64" is invalid " 95d61e45ecSDavid Kiarieamdvi_get_pte_hwerror(uint64_t addr) "hardware error eccessing PTE at addr 0x%"PRIx64 96d61e45ecSDavid Kiarieamdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PRIx8" translating addr 0x%"PRIx64 97d61e45ecSDavid Kiarieamdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64 98d61e45ecSDavid Kiarieamdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 99d61e45ecSDavid Kiarieamdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64 100577c470fSSingh, Brijeshamdvi_mem_ir_write_req(uint64_t addr, uint64_t val, uint32_t size) "addr 0x%"PRIx64" data 0x%"PRIx64" size 0x%"PRIx32 101577c470fSSingh, Brijeshamdvi_mem_ir_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" data 0x%"PRIx64 102577c470fSSingh, Brijeshamdvi_ir_remap_msi_req(uint64_t addr, uint64_t data, uint8_t devid) "addr 0x%"PRIx64" data 0x%"PRIx64" devid 0x%"PRIx8 103577c470fSSingh, Brijeshamdvi_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")" 104577c470fSSingh, Brijeshamdvi_err(const char *str) "%s" 105b44159feSSingh, Brijeshamdvi_ir_irte(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" offset 0x%"PRIx64 106b44159feSSingh, Brijeshamdvi_ir_irte_val(uint32_t data) "data 0x%"PRIx32 107b44159feSSingh, Brijeshamdvi_ir_err(const char *str) "%s" 108b44159feSSingh, Brijeshamdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8 109b44159feSSingh, Brijeshamdvi_ir_target_abort(const char *str) "%s" 110b44159feSSingh, Brijeshamdvi_ir_delivery_mode(const char *str) "%s" 111135f866eSSingh, Brijeshamdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64 1127299e1a4SPhilippe Mathieu-Daudé 113500016e5SMarkus Armbruster# vmport.c 1147299e1a4SPhilippe Mathieu-Daudévmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p" 1157299e1a4SPhilippe Mathieu-Daudévmport_command(unsigned char command) "command: 0x%02x" 1164ca8dabdSPhilippe Mathieu-Daudé 11789a289c7SPaolo Bonzini# x86.c 11889a289c7SPaolo Bonzinix86_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d" 11989a289c7SPaolo Bonzinix86_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d" 12089a289c7SPaolo Bonzini 121d3e07dc8SPhilippe Mathieu-Daudé# port92.c 1224ca8dabdSPhilippe Mathieu-Daudéport92_read(uint8_t val) "port92: read 0x%02x" 1234ca8dabdSPhilippe Mathieu-Daudéport92_write(uint8_t val) "port92: write 0x%02x" 124