1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 #include "qemu/error-report.h" 48 #include "migration/migration.h" 49 50 /* ICH9 AHCI has 6 ports */ 51 #define MAX_SATA_PORTS 6 52 53 static bool has_acpi_build = true; 54 static bool rsdp_in_ram = true; 55 static bool smbios_defaults = true; 56 static bool smbios_legacy_mode; 57 static bool smbios_uuid_encoded = true; 58 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 59 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 60 * pages in the host. 61 */ 62 static bool gigabyte_align = true; 63 static bool has_reserved_memory = true; 64 65 /* PC hardware initialisation */ 66 static void pc_q35_init(MachineState *machine) 67 { 68 PCMachineState *pc_machine = PC_MACHINE(machine); 69 ram_addr_t below_4g_mem_size, above_4g_mem_size; 70 Q35PCIHost *q35_host; 71 PCIHostState *phb; 72 PCIBus *host_bus; 73 PCIDevice *lpc; 74 BusState *idebus[MAX_SATA_PORTS]; 75 ISADevice *rtc_state; 76 ISADevice *floppy; 77 MemoryRegion *pci_memory; 78 MemoryRegion *rom_memory; 79 MemoryRegion *ram_memory; 80 GSIState *gsi_state; 81 ISABus *isa_bus; 82 int pci_enabled = 1; 83 qemu_irq *gsi; 84 qemu_irq *i8259; 85 int i; 86 ICH9LPCState *ich9_lpc; 87 PCIDevice *ahci; 88 DeviceState *icc_bridge; 89 PcGuestInfo *guest_info; 90 ram_addr_t lowmem; 91 DriveInfo *hd[MAX_SATA_PORTS]; 92 MachineClass *mc = MACHINE_GET_CLASS(machine); 93 94 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 95 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 96 * also known as MMCFG). 97 * If it doesn't, we need to split it in chunks below and above 4G. 98 * In any case, try to make sure that guest addresses aligned at 99 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 100 * For old machine types, use whatever split we used historically to avoid 101 * breaking migration. 102 */ 103 if (machine->ram_size >= 0xb0000000) { 104 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 105 } else { 106 lowmem = 0xb0000000; 107 } 108 109 /* Handle the machine opt max-ram-below-4g. It is basically doing 110 * min(qemu limit, user limit). 111 */ 112 if (lowmem > pc_machine->max_ram_below_4g) { 113 lowmem = pc_machine->max_ram_below_4g; 114 if (machine->ram_size - lowmem > lowmem && 115 lowmem & ((1ULL << 30) - 1)) { 116 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 117 ") not a multiple of 1G; possible bad performance.", 118 pc_machine->max_ram_below_4g); 119 } 120 } 121 122 if (machine->ram_size >= lowmem) { 123 above_4g_mem_size = machine->ram_size - lowmem; 124 below_4g_mem_size = lowmem; 125 } else { 126 above_4g_mem_size = 0; 127 below_4g_mem_size = machine->ram_size; 128 } 129 130 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size, 131 &ram_memory) != 0) { 132 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 133 exit(1); 134 } 135 136 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 137 object_property_add_child(qdev_get_machine(), "icc-bridge", 138 OBJECT(icc_bridge), NULL); 139 140 pc_cpus_init(machine->cpu_model, icc_bridge); 141 pc_acpi_init("q35-acpi-dsdt.aml"); 142 143 kvmclock_create(); 144 145 /* pci enabled */ 146 if (pci_enabled) { 147 pci_memory = g_new(MemoryRegion, 1); 148 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 149 rom_memory = pci_memory; 150 } else { 151 pci_memory = NULL; 152 rom_memory = get_system_memory(); 153 } 154 155 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 156 guest_info->isapc_ram_fw = false; 157 guest_info->has_acpi_build = has_acpi_build; 158 guest_info->has_reserved_memory = has_reserved_memory; 159 guest_info->rsdp_in_ram = rsdp_in_ram; 160 161 /* Migration was not supported in 2.0 for Q35, so do not bother 162 * with this hack (see hw/i386/acpi-build.c). 163 */ 164 guest_info->legacy_acpi_table_size = 0; 165 166 if (smbios_defaults) { 167 /* These values are guest ABI, do not change */ 168 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 169 mc->name, smbios_legacy_mode, smbios_uuid_encoded); 170 } 171 172 /* allocate ram and load rom/bios */ 173 if (!xen_enabled()) { 174 pc_memory_init(machine, get_system_memory(), 175 below_4g_mem_size, above_4g_mem_size, 176 rom_memory, &ram_memory, guest_info); 177 } 178 179 /* irq lines */ 180 gsi_state = g_malloc0(sizeof(*gsi_state)); 181 if (kvm_irqchip_in_kernel()) { 182 kvm_pc_setup_irq_routing(pci_enabled); 183 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 184 GSI_NUM_PINS); 185 } else { 186 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 187 } 188 189 /* create pci host bus */ 190 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 191 192 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 193 q35_host->mch.ram_memory = ram_memory; 194 q35_host->mch.pci_address_space = pci_memory; 195 q35_host->mch.system_memory = get_system_memory(); 196 q35_host->mch.address_space_io = get_system_io(); 197 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 198 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 199 q35_host->mch.guest_info = guest_info; 200 /* pci */ 201 qdev_init_nofail(DEVICE(q35_host)); 202 phb = PCI_HOST_BRIDGE(q35_host); 203 host_bus = phb->bus; 204 /* create ISA bus */ 205 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 206 ICH9_LPC_FUNC), true, 207 TYPE_ICH9_LPC_DEVICE); 208 209 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 210 TYPE_HOTPLUG_HANDLER, 211 (Object **)&pc_machine->acpi_dev, 212 object_property_allow_set_link, 213 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 214 object_property_set_link(OBJECT(machine), OBJECT(lpc), 215 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 216 217 ich9_lpc = ICH9_LPC_DEVICE(lpc); 218 ich9_lpc->pic = gsi; 219 ich9_lpc->ioapic = gsi_state->ioapic_irq; 220 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 221 ICH9_LPC_NB_PIRQS); 222 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 223 isa_bus = ich9_lpc->isa_bus; 224 225 /*end early*/ 226 isa_bus_irqs(isa_bus, gsi); 227 228 if (kvm_irqchip_in_kernel()) { 229 i8259 = kvm_i8259_init(isa_bus); 230 } else if (xen_enabled()) { 231 i8259 = xen_interrupt_controller_init(); 232 } else { 233 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 234 } 235 236 for (i = 0; i < ISA_NUM_IRQS; i++) { 237 gsi_state->i8259_irq[i] = i8259[i]; 238 } 239 if (pci_enabled) { 240 ioapic_init_gsi(gsi_state, "q35"); 241 } 242 qdev_init_nofail(icc_bridge); 243 244 pc_register_ferr_irq(gsi[13]); 245 246 assert(pc_machine->vmport != ON_OFF_AUTO_MAX); 247 if (pc_machine->vmport == ON_OFF_AUTO_AUTO) { 248 pc_machine->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 249 } 250 251 /* init basic PC hardware */ 252 pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy, &floppy, 253 (pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104); 254 255 /* connect pm stuff to lpc */ 256 ich9_lpc_pm_init(lpc); 257 258 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 259 ahci = pci_create_simple_multifunction(host_bus, 260 PCI_DEVFN(ICH9_SATA1_DEV, 261 ICH9_SATA1_FUNC), 262 true, "ich9-ahci"); 263 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 264 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 265 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 266 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 267 ahci_ide_create_devs(ahci, hd); 268 269 if (usb_enabled()) { 270 /* Should we create 6 UHCI according to ich9 spec? */ 271 ehci_create_ich9_with_companions(host_bus, 0x1d); 272 } 273 274 /* TODO: Populate SPD eeprom data. */ 275 smbus_eeprom_init(ich9_smb_init(host_bus, 276 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 277 0xb100), 278 8, NULL, 0); 279 280 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 281 machine, floppy, idebus[0], idebus[1], rtc_state); 282 283 /* the rest devices to which pci devfn is automatically assigned */ 284 pc_vga_init(isa_bus, host_bus); 285 pc_nic_init(isa_bus, host_bus); 286 if (pci_enabled) { 287 pc_pci_device_init(host_bus); 288 } 289 } 290 291 static void pc_compat_2_3(MachineState *machine) 292 { 293 savevm_skip_section_footers(); 294 } 295 296 static void pc_compat_2_2(MachineState *machine) 297 { 298 pc_compat_2_3(machine); 299 rsdp_in_ram = false; 300 x86_cpu_compat_set_features("kvm64", FEAT_1_EDX, 0, CPUID_VME); 301 x86_cpu_compat_set_features("kvm32", FEAT_1_EDX, 0, CPUID_VME); 302 x86_cpu_compat_set_features("Conroe", FEAT_1_EDX, 0, CPUID_VME); 303 x86_cpu_compat_set_features("Penryn", FEAT_1_EDX, 0, CPUID_VME); 304 x86_cpu_compat_set_features("Nehalem", FEAT_1_EDX, 0, CPUID_VME); 305 x86_cpu_compat_set_features("Westmere", FEAT_1_EDX, 0, CPUID_VME); 306 x86_cpu_compat_set_features("SandyBridge", FEAT_1_EDX, 0, CPUID_VME); 307 x86_cpu_compat_set_features("Haswell", FEAT_1_EDX, 0, CPUID_VME); 308 x86_cpu_compat_set_features("Broadwell", FEAT_1_EDX, 0, CPUID_VME); 309 x86_cpu_compat_set_features("Opteron_G1", FEAT_1_EDX, 0, CPUID_VME); 310 x86_cpu_compat_set_features("Opteron_G2", FEAT_1_EDX, 0, CPUID_VME); 311 x86_cpu_compat_set_features("Opteron_G3", FEAT_1_EDX, 0, CPUID_VME); 312 x86_cpu_compat_set_features("Opteron_G4", FEAT_1_EDX, 0, CPUID_VME); 313 x86_cpu_compat_set_features("Opteron_G5", FEAT_1_EDX, 0, CPUID_VME); 314 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_F16C); 315 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); 316 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); 317 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); 318 machine->suppress_vmdesc = true; 319 } 320 321 static void pc_compat_2_1(MachineState *machine) 322 { 323 PCMachineState *pcms = PC_MACHINE(machine); 324 325 pc_compat_2_2(machine); 326 pcms->enforce_aligned_dimm = false; 327 smbios_uuid_encoded = false; 328 x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); 329 x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); 330 x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM); 331 } 332 333 static void pc_compat_2_0(MachineState *machine) 334 { 335 pc_compat_2_1(machine); 336 smbios_legacy_mode = true; 337 has_reserved_memory = false; 338 pc_set_legacy_acpi_data_size(); 339 } 340 341 static void pc_compat_1_7(MachineState *machine) 342 { 343 pc_compat_2_0(machine); 344 smbios_defaults = false; 345 gigabyte_align = false; 346 option_rom_has_mr = true; 347 x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC); 348 } 349 350 static void pc_compat_1_6(MachineState *machine) 351 { 352 pc_compat_1_7(machine); 353 rom_file_has_mr = false; 354 has_acpi_build = false; 355 } 356 357 static void pc_compat_1_5(MachineState *machine) 358 { 359 pc_compat_1_6(machine); 360 } 361 362 static void pc_compat_1_4(MachineState *machine) 363 { 364 pc_compat_1_5(machine); 365 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 366 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 367 } 368 369 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 370 static void pc_init_##suffix(MachineState *machine) \ 371 { \ 372 void (*compat)(MachineState *m) = (compatfn); \ 373 if (compat) { \ 374 compat(machine); \ 375 } \ 376 pc_q35_init(machine); \ 377 } \ 378 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 379 380 381 static void pc_q35_machine_options(MachineClass *m) 382 { 383 pc_default_machine_options(m); 384 m->family = "pc_q35"; 385 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 386 m->hot_add_cpu = pc_hot_add_cpu; 387 m->units_per_default_bus = 1; 388 } 389 390 static void pc_q35_2_4_machine_options(MachineClass *m) 391 { 392 pc_q35_machine_options(m); 393 m->default_machine_opts = "firmware=bios-256k.bin"; 394 m->default_display = "std"; 395 m->no_floppy = 1; 396 m->alias = "q35"; 397 } 398 399 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 400 pc_q35_2_4_machine_options); 401 402 403 static void pc_q35_2_3_machine_options(MachineClass *m) 404 { 405 pc_q35_2_4_machine_options(m); 406 m->no_floppy = 0; 407 m->alias = NULL; 408 SET_MACHINE_COMPAT(m, PC_COMPAT_2_3); 409 } 410 411 DEFINE_Q35_MACHINE(v2_3, "pc-q35-2.3", pc_compat_2_3, 412 pc_q35_2_3_machine_options); 413 414 415 static void pc_q35_2_2_machine_options(MachineClass *m) 416 { 417 pc_q35_2_3_machine_options(m); 418 SET_MACHINE_COMPAT(m, PC_COMPAT_2_2); 419 } 420 421 DEFINE_Q35_MACHINE(v2_2, "pc-q35-2.2", pc_compat_2_2, 422 pc_q35_2_2_machine_options); 423 424 425 static void pc_q35_2_1_machine_options(MachineClass *m) 426 { 427 pc_q35_2_2_machine_options(m); 428 m->default_display = NULL; 429 SET_MACHINE_COMPAT(m, PC_COMPAT_2_1); 430 } 431 432 DEFINE_Q35_MACHINE(v2_1, "pc-q35-2.1", pc_compat_2_1, 433 pc_q35_2_1_machine_options); 434 435 436 static void pc_q35_2_0_machine_options(MachineClass *m) 437 { 438 pc_q35_2_1_machine_options(m); 439 SET_MACHINE_COMPAT(m, PC_COMPAT_2_0); 440 } 441 442 DEFINE_Q35_MACHINE(v2_0, "pc-q35-2.0", pc_compat_2_0, 443 pc_q35_2_0_machine_options); 444 445 446 static void pc_q35_1_7_machine_options(MachineClass *m) 447 { 448 pc_q35_2_0_machine_options(m); 449 m->default_machine_opts = NULL; 450 SET_MACHINE_COMPAT(m, PC_COMPAT_1_7); 451 } 452 453 DEFINE_Q35_MACHINE(v1_7, "pc-q35-1.7", pc_compat_1_7, 454 pc_q35_1_7_machine_options); 455 456 457 static void pc_q35_1_6_machine_options(MachineClass *m) 458 { 459 pc_q35_machine_options(m); 460 SET_MACHINE_COMPAT(m, PC_COMPAT_1_6); 461 } 462 463 DEFINE_Q35_MACHINE(v1_6, "pc-q35-1.6", pc_compat_1_6, 464 pc_q35_1_6_machine_options); 465 466 467 static void pc_q35_1_5_machine_options(MachineClass *m) 468 { 469 pc_q35_1_6_machine_options(m); 470 SET_MACHINE_COMPAT(m, PC_COMPAT_1_5); 471 } 472 473 DEFINE_Q35_MACHINE(v1_5, "pc-q35-1.5", pc_compat_1_5, 474 pc_q35_1_5_machine_options); 475 476 477 static void pc_q35_1_4_machine_options(MachineClass *m) 478 { 479 pc_q35_1_5_machine_options(m); 480 m->hot_add_cpu = NULL; 481 SET_MACHINE_COMPAT(m, PC_COMPAT_1_4); 482 } 483 484 DEFINE_Q35_MACHINE(v1_4, "pc-q35-1.4", pc_compat_1_4, 485 pc_q35_1_4_machine_options); 486