1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/hw.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus.h" 36 #include "hw/boards.h" 37 #include "hw/timer/mc146818rtc.h" 38 #include "hw/xen/xen.h" 39 #include "sysemu/kvm.h" 40 #include "kvm_i386.h" 41 #include "hw/kvm/clock.h" 42 #include "hw/pci-host/q35.h" 43 #include "exec/address-spaces.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/ich9.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/display/ramfb.h" 49 #include "hw/smbios/smbios.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci.h" 52 #include "hw/usb.h" 53 #include "qapi/error.h" 54 #include "qemu/error-report.h" 55 #include "sysemu/numa.h" 56 57 /* ICH9 AHCI has 6 ports */ 58 #define MAX_SATA_PORTS 6 59 60 /* PC hardware initialisation */ 61 static void pc_q35_init(MachineState *machine) 62 { 63 PCMachineState *pcms = PC_MACHINE(machine); 64 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 65 Q35PCIHost *q35_host; 66 PCIHostState *phb; 67 PCIBus *host_bus; 68 PCIDevice *lpc; 69 DeviceState *lpc_dev; 70 BusState *idebus[MAX_SATA_PORTS]; 71 ISADevice *rtc_state; 72 MemoryRegion *system_io = get_system_io(); 73 MemoryRegion *pci_memory; 74 MemoryRegion *rom_memory; 75 MemoryRegion *ram_memory; 76 GSIState *gsi_state; 77 ISABus *isa_bus; 78 qemu_irq *i8259; 79 int i; 80 ICH9LPCState *ich9_lpc; 81 PCIDevice *ahci; 82 ram_addr_t lowmem; 83 DriveInfo *hd[MAX_SATA_PORTS]; 84 MachineClass *mc = MACHINE_GET_CLASS(machine); 85 86 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 87 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 88 * also known as MMCFG). 89 * If it doesn't, we need to split it in chunks below and above 4G. 90 * In any case, try to make sure that guest addresses aligned at 91 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 92 */ 93 if (machine->ram_size >= 0xb0000000) { 94 lowmem = 0x80000000; 95 } else { 96 lowmem = 0xb0000000; 97 } 98 99 /* Handle the machine opt max-ram-below-4g. It is basically doing 100 * min(qemu limit, user limit). 101 */ 102 if (!pcms->max_ram_below_4g) { 103 pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */; 104 } 105 if (lowmem > pcms->max_ram_below_4g) { 106 lowmem = pcms->max_ram_below_4g; 107 if (machine->ram_size - lowmem > lowmem && 108 lowmem & ((1ULL << 30) - 1)) { 109 warn_report("There is possibly poor performance as the ram size " 110 " (0x%" PRIx64 ") is more then twice the size of" 111 " max-ram-below-4g (%"PRIu64") and" 112 " max-ram-below-4g is not a multiple of 1G.", 113 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 114 } 115 } 116 117 if (machine->ram_size >= lowmem) { 118 pcms->above_4g_mem_size = machine->ram_size - lowmem; 119 pcms->below_4g_mem_size = lowmem; 120 } else { 121 pcms->above_4g_mem_size = 0; 122 pcms->below_4g_mem_size = machine->ram_size; 123 } 124 125 if (xen_enabled()) { 126 xen_hvm_init(pcms, &ram_memory); 127 } 128 129 pc_cpus_init(pcms); 130 131 kvmclock_create(); 132 133 /* pci enabled */ 134 if (pcmc->pci_enabled) { 135 pci_memory = g_new(MemoryRegion, 1); 136 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 137 rom_memory = pci_memory; 138 } else { 139 pci_memory = NULL; 140 rom_memory = get_system_memory(); 141 } 142 143 pc_guest_info_init(pcms); 144 145 if (pcmc->smbios_defaults) { 146 /* These values are guest ABI, do not change */ 147 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 148 mc->name, pcmc->smbios_legacy_mode, 149 pcmc->smbios_uuid_encoded, 150 SMBIOS_ENTRY_POINT_21); 151 } 152 153 /* allocate ram and load rom/bios */ 154 if (!xen_enabled()) { 155 pc_memory_init(pcms, get_system_memory(), 156 rom_memory, &ram_memory); 157 } 158 159 /* irq lines */ 160 gsi_state = g_malloc0(sizeof(*gsi_state)); 161 if (kvm_ioapic_in_kernel()) { 162 kvm_pc_setup_irq_routing(pcmc->pci_enabled); 163 pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 164 GSI_NUM_PINS); 165 } else { 166 pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 167 } 168 169 /* create pci host bus */ 170 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 171 172 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 173 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 174 MCH_HOST_PROP_RAM_MEM, NULL); 175 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 176 MCH_HOST_PROP_PCI_MEM, NULL); 177 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 178 MCH_HOST_PROP_SYSTEM_MEM, NULL); 179 object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 180 MCH_HOST_PROP_IO_MEM, NULL); 181 object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size, 182 PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 183 object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size, 184 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 185 /* pci */ 186 qdev_init_nofail(DEVICE(q35_host)); 187 phb = PCI_HOST_BRIDGE(q35_host); 188 host_bus = phb->bus; 189 /* create ISA bus */ 190 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 191 ICH9_LPC_FUNC), true, 192 TYPE_ICH9_LPC_DEVICE); 193 194 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 195 TYPE_HOTPLUG_HANDLER, 196 (Object **)&pcms->acpi_dev, 197 object_property_allow_set_link, 198 OBJ_PROP_LINK_STRONG, &error_abort); 199 object_property_set_link(OBJECT(machine), OBJECT(lpc), 200 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 201 202 ich9_lpc = ICH9_LPC_DEVICE(lpc); 203 lpc_dev = DEVICE(lpc); 204 for (i = 0; i < GSI_NUM_PINS; i++) { 205 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]); 206 } 207 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 208 ICH9_LPC_NB_PIRQS); 209 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 210 isa_bus = ich9_lpc->isa_bus; 211 212 if (kvm_pic_in_kernel()) { 213 i8259 = kvm_i8259_init(isa_bus); 214 } else if (xen_enabled()) { 215 i8259 = xen_interrupt_controller_init(); 216 } else { 217 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 218 } 219 220 for (i = 0; i < ISA_NUM_IRQS; i++) { 221 gsi_state->i8259_irq[i] = i8259[i]; 222 } 223 g_free(i8259); 224 225 if (pcmc->pci_enabled) { 226 ioapic_init_gsi(gsi_state, "q35"); 227 } 228 229 pc_register_ferr_irq(pcms->gsi[13]); 230 231 assert(pcms->vmport != ON_OFF_AUTO__MAX); 232 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 233 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 234 } 235 236 /* init basic PC hardware */ 237 pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy, 238 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit, 239 0xff0104); 240 241 /* connect pm stuff to lpc */ 242 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); 243 244 if (pcms->sata) { 245 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 246 ahci = pci_create_simple_multifunction(host_bus, 247 PCI_DEVFN(ICH9_SATA1_DEV, 248 ICH9_SATA1_FUNC), 249 true, "ich9-ahci"); 250 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 251 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 252 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 253 ide_drive_get(hd, ahci_get_num_ports(ahci)); 254 ahci_ide_create_devs(ahci, hd); 255 } else { 256 idebus[0] = idebus[1] = NULL; 257 } 258 259 if (machine_usb(machine)) { 260 /* Should we create 6 UHCI according to ich9 spec? */ 261 ehci_create_ich9_with_companions(host_bus, 0x1d); 262 } 263 264 if (pcms->smbus) { 265 /* TODO: Populate SPD eeprom data. */ 266 smbus_eeprom_init(ich9_smb_init(host_bus, 267 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 268 0xb100), 269 8, NULL, 0); 270 } 271 272 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 273 274 /* the rest devices to which pci devfn is automatically assigned */ 275 pc_vga_init(isa_bus, host_bus); 276 pc_nic_init(pcmc, isa_bus, host_bus); 277 278 if (pcms->acpi_nvdimm_state.is_enabled) { 279 nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, 280 pcms->fw_cfg, OBJECT(pcms)); 281 } 282 } 283 284 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 285 static void pc_init_##suffix(MachineState *machine) \ 286 { \ 287 void (*compat)(MachineState *m) = (compatfn); \ 288 if (compat) { \ 289 compat(machine); \ 290 } \ 291 pc_q35_init(machine); \ 292 } \ 293 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 294 295 296 static void pc_q35_machine_options(MachineClass *m) 297 { 298 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 299 pcmc->default_nic_model = "e1000e"; 300 301 m->family = "pc_q35"; 302 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 303 m->units_per_default_bus = 1; 304 m->default_machine_opts = "firmware=bios-256k.bin"; 305 m->default_display = "std"; 306 m->no_floppy = 1; 307 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 308 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 309 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 310 m->max_cpus = 288; 311 } 312 313 static void pc_q35_3_0_machine_options(MachineClass *m) 314 { 315 pc_q35_machine_options(m); 316 m->alias = "q35"; 317 } 318 319 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 320 pc_q35_3_0_machine_options); 321 322 static void pc_q35_2_12_machine_options(MachineClass *m) 323 { 324 pc_q35_3_0_machine_options(m); 325 m->alias = NULL; 326 SET_MACHINE_COMPAT(m, PC_COMPAT_2_12); 327 } 328 329 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 330 pc_q35_2_12_machine_options); 331 332 static void pc_q35_2_11_machine_options(MachineClass *m) 333 { 334 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 335 336 pc_q35_2_12_machine_options(m); 337 pcmc->default_nic_model = "e1000"; 338 SET_MACHINE_COMPAT(m, PC_COMPAT_2_11); 339 } 340 341 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 342 pc_q35_2_11_machine_options); 343 344 static void pc_q35_2_10_machine_options(MachineClass *m) 345 { 346 pc_q35_2_11_machine_options(m); 347 SET_MACHINE_COMPAT(m, PC_COMPAT_2_10); 348 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 349 m->auto_enable_numa_with_memhp = false; 350 } 351 352 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 353 pc_q35_2_10_machine_options); 354 355 static void pc_q35_2_9_machine_options(MachineClass *m) 356 { 357 pc_q35_2_10_machine_options(m); 358 SET_MACHINE_COMPAT(m, PC_COMPAT_2_9); 359 } 360 361 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 362 pc_q35_2_9_machine_options); 363 364 static void pc_q35_2_8_machine_options(MachineClass *m) 365 { 366 pc_q35_2_9_machine_options(m); 367 SET_MACHINE_COMPAT(m, PC_COMPAT_2_8); 368 } 369 370 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 371 pc_q35_2_8_machine_options); 372 373 static void pc_q35_2_7_machine_options(MachineClass *m) 374 { 375 pc_q35_2_8_machine_options(m); 376 m->max_cpus = 255; 377 SET_MACHINE_COMPAT(m, PC_COMPAT_2_7); 378 } 379 380 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 381 pc_q35_2_7_machine_options); 382 383 static void pc_q35_2_6_machine_options(MachineClass *m) 384 { 385 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 386 pc_q35_2_7_machine_options(m); 387 pcmc->legacy_cpu_hotplug = true; 388 pcmc->linuxboot_dma_enabled = false; 389 SET_MACHINE_COMPAT(m, PC_COMPAT_2_6); 390 } 391 392 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 393 pc_q35_2_6_machine_options); 394 395 static void pc_q35_2_5_machine_options(MachineClass *m) 396 { 397 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 398 pc_q35_2_6_machine_options(m); 399 pcmc->save_tsc_khz = false; 400 m->legacy_fw_cfg_order = 1; 401 SET_MACHINE_COMPAT(m, PC_COMPAT_2_5); 402 } 403 404 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 405 pc_q35_2_5_machine_options); 406 407 static void pc_q35_2_4_machine_options(MachineClass *m) 408 { 409 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 410 pc_q35_2_5_machine_options(m); 411 m->hw_version = "2.4.0"; 412 pcmc->broken_reserved_end = true; 413 SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); 414 } 415 416 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 417 pc_q35_2_4_machine_options); 418