1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/timer/mc146818rtc.h" 37 #include "hw/xen/xen.h" 38 #include "sysemu/kvm.h" 39 #include "kvm_i386.h" 40 #include "hw/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/qdev-properties.h" 43 #include "exec/address-spaces.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/ich9.h" 47 #include "hw/i386/amd_iommu.h" 48 #include "hw/i386/intel_iommu.h" 49 #include "hw/display/ramfb.h" 50 #include "hw/firmware/smbios.h" 51 #include "hw/ide/pci.h" 52 #include "hw/ide/ahci.h" 53 #include "hw/usb.h" 54 #include "qapi/error.h" 55 #include "qemu/error-report.h" 56 #include "sysemu/numa.h" 57 58 /* ICH9 AHCI has 6 ports */ 59 #define MAX_SATA_PORTS 6 60 61 struct ehci_companions { 62 const char *name; 63 int func; 64 int port; 65 }; 66 67 static const struct ehci_companions ich9_1d[] = { 68 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 69 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 70 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 71 }; 72 73 static const struct ehci_companions ich9_1a[] = { 74 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 75 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 76 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 77 }; 78 79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 80 { 81 const struct ehci_companions *comp; 82 PCIDevice *ehci, *uhci; 83 BusState *usbbus; 84 const char *name; 85 int i; 86 87 switch (slot) { 88 case 0x1d: 89 name = "ich9-usb-ehci1"; 90 comp = ich9_1d; 91 break; 92 case 0x1a: 93 name = "ich9-usb-ehci2"; 94 comp = ich9_1a; 95 break; 96 default: 97 return -1; 98 } 99 100 ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); 101 qdev_init_nofail(&ehci->qdev); 102 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 103 104 for (i = 0; i < 3; i++) { 105 uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), 106 true, comp[i].name); 107 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 108 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 109 qdev_init_nofail(&uhci->qdev); 110 } 111 return 0; 112 } 113 114 /* PC hardware initialisation */ 115 static void pc_q35_init(MachineState *machine) 116 { 117 PCMachineState *pcms = PC_MACHINE(machine); 118 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 119 X86MachineState *x86ms = X86_MACHINE(machine); 120 Q35PCIHost *q35_host; 121 PCIHostState *phb; 122 PCIBus *host_bus; 123 PCIDevice *lpc; 124 DeviceState *lpc_dev; 125 BusState *idebus[MAX_SATA_PORTS]; 126 ISADevice *rtc_state; 127 MemoryRegion *system_io = get_system_io(); 128 MemoryRegion *pci_memory; 129 MemoryRegion *rom_memory; 130 MemoryRegion *ram_memory; 131 GSIState *gsi_state; 132 ISABus *isa_bus; 133 qemu_irq *i8259; 134 int i; 135 ICH9LPCState *ich9_lpc; 136 PCIDevice *ahci; 137 ram_addr_t lowmem; 138 DriveInfo *hd[MAX_SATA_PORTS]; 139 MachineClass *mc = MACHINE_GET_CLASS(machine); 140 141 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 142 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 143 * also known as MMCFG). 144 * If it doesn't, we need to split it in chunks below and above 4G. 145 * In any case, try to make sure that guest addresses aligned at 146 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 147 */ 148 if (machine->ram_size >= 0xb0000000) { 149 lowmem = 0x80000000; 150 } else { 151 lowmem = 0xb0000000; 152 } 153 154 /* Handle the machine opt max-ram-below-4g. It is basically doing 155 * min(qemu limit, user limit). 156 */ 157 if (!x86ms->max_ram_below_4g) { 158 x86ms->max_ram_below_4g = 4 * GiB; 159 } 160 if (lowmem > x86ms->max_ram_below_4g) { 161 lowmem = x86ms->max_ram_below_4g; 162 if (machine->ram_size - lowmem > lowmem && 163 lowmem & (1 * GiB - 1)) { 164 warn_report("There is possibly poor performance as the ram size " 165 " (0x%" PRIx64 ") is more then twice the size of" 166 " max-ram-below-4g (%"PRIu64") and" 167 " max-ram-below-4g is not a multiple of 1G.", 168 (uint64_t)machine->ram_size, x86ms->max_ram_below_4g); 169 } 170 } 171 172 if (machine->ram_size >= lowmem) { 173 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 174 x86ms->below_4g_mem_size = lowmem; 175 } else { 176 x86ms->above_4g_mem_size = 0; 177 x86ms->below_4g_mem_size = machine->ram_size; 178 } 179 180 if (xen_enabled()) { 181 xen_hvm_init(pcms, &ram_memory); 182 } 183 184 x86_cpus_init(pcms); 185 186 kvmclock_create(); 187 188 /* pci enabled */ 189 if (pcmc->pci_enabled) { 190 pci_memory = g_new(MemoryRegion, 1); 191 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 192 rom_memory = pci_memory; 193 } else { 194 pci_memory = NULL; 195 rom_memory = get_system_memory(); 196 } 197 198 pc_guest_info_init(pcms); 199 200 if (pcmc->smbios_defaults) { 201 /* These values are guest ABI, do not change */ 202 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 203 mc->name, pcmc->smbios_legacy_mode, 204 pcmc->smbios_uuid_encoded, 205 SMBIOS_ENTRY_POINT_21); 206 } 207 208 /* allocate ram and load rom/bios */ 209 if (!xen_enabled()) { 210 pc_memory_init(pcms, get_system_memory(), 211 rom_memory, &ram_memory); 212 } 213 214 /* irq lines */ 215 gsi_state = g_malloc0(sizeof(*gsi_state)); 216 if (kvm_ioapic_in_kernel()) { 217 kvm_pc_setup_irq_routing(pcmc->pci_enabled); 218 x86ms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 219 GSI_NUM_PINS); 220 } else { 221 x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 222 } 223 224 /* create pci host bus */ 225 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 226 227 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 228 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 229 MCH_HOST_PROP_RAM_MEM, NULL); 230 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 231 MCH_HOST_PROP_PCI_MEM, NULL); 232 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 233 MCH_HOST_PROP_SYSTEM_MEM, NULL); 234 object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 235 MCH_HOST_PROP_IO_MEM, NULL); 236 object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size, 237 PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 238 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size, 239 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 240 /* pci */ 241 qdev_init_nofail(DEVICE(q35_host)); 242 phb = PCI_HOST_BRIDGE(q35_host); 243 host_bus = phb->bus; 244 /* create ISA bus */ 245 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 246 ICH9_LPC_FUNC), true, 247 TYPE_ICH9_LPC_DEVICE); 248 249 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 250 TYPE_HOTPLUG_HANDLER, 251 (Object **)&pcms->acpi_dev, 252 object_property_allow_set_link, 253 OBJ_PROP_LINK_STRONG, &error_abort); 254 object_property_set_link(OBJECT(machine), OBJECT(lpc), 255 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 256 257 ich9_lpc = ICH9_LPC_DEVICE(lpc); 258 lpc_dev = DEVICE(lpc); 259 for (i = 0; i < GSI_NUM_PINS; i++) { 260 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 261 } 262 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 263 ICH9_LPC_NB_PIRQS); 264 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 265 isa_bus = ich9_lpc->isa_bus; 266 267 if (kvm_pic_in_kernel()) { 268 i8259 = kvm_i8259_init(isa_bus); 269 } else if (xen_enabled()) { 270 i8259 = xen_interrupt_controller_init(); 271 } else { 272 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 273 } 274 275 for (i = 0; i < ISA_NUM_IRQS; i++) { 276 gsi_state->i8259_irq[i] = i8259[i]; 277 } 278 g_free(i8259); 279 280 if (pcmc->pci_enabled) { 281 ioapic_init_gsi(gsi_state, "q35"); 282 } 283 284 pc_register_ferr_irq(x86ms->gsi[13]); 285 286 assert(pcms->vmport != ON_OFF_AUTO__MAX); 287 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 288 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 289 } 290 291 /* init basic PC hardware */ 292 pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 293 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled, 294 0xff0104); 295 296 /* connect pm stuff to lpc */ 297 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); 298 299 if (pcms->sata_enabled) { 300 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 301 ahci = pci_create_simple_multifunction(host_bus, 302 PCI_DEVFN(ICH9_SATA1_DEV, 303 ICH9_SATA1_FUNC), 304 true, "ich9-ahci"); 305 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 306 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 307 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 308 ide_drive_get(hd, ahci_get_num_ports(ahci)); 309 ahci_ide_create_devs(ahci, hd); 310 } else { 311 idebus[0] = idebus[1] = NULL; 312 } 313 314 if (machine_usb(machine)) { 315 /* Should we create 6 UHCI according to ich9 spec? */ 316 ehci_create_ich9_with_companions(host_bus, 0x1d); 317 } 318 319 if (pcms->smbus_enabled) { 320 /* TODO: Populate SPD eeprom data. */ 321 pcms->smbus = ich9_smb_init(host_bus, 322 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 323 0xb100); 324 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 325 } 326 327 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 328 329 /* the rest devices to which pci devfn is automatically assigned */ 330 pc_vga_init(isa_bus, host_bus); 331 pc_nic_init(pcmc, isa_bus, host_bus); 332 333 if (machine->nvdimms_state->is_enabled) { 334 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 335 x86ms->fw_cfg, OBJECT(pcms)); 336 } 337 } 338 339 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 340 static void pc_init_##suffix(MachineState *machine) \ 341 { \ 342 void (*compat)(MachineState *m) = (compatfn); \ 343 if (compat) { \ 344 compat(machine); \ 345 } \ 346 pc_q35_init(machine); \ 347 } \ 348 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 349 350 351 static void pc_q35_machine_options(MachineClass *m) 352 { 353 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 354 pcmc->default_nic_model = "e1000e"; 355 356 m->family = "pc_q35"; 357 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 358 m->units_per_default_bus = 1; 359 m->default_machine_opts = "firmware=bios-256k.bin"; 360 m->default_display = "std"; 361 m->default_kernel_irqchip_split = false; 362 m->no_floppy = 1; 363 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 364 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 365 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 366 m->max_cpus = 288; 367 } 368 369 static void pc_q35_4_2_machine_options(MachineClass *m) 370 { 371 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 372 pc_q35_machine_options(m); 373 m->alias = "q35"; 374 pcmc->default_cpu_version = 1; 375 } 376 377 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 378 pc_q35_4_2_machine_options); 379 380 static void pc_q35_4_1_machine_options(MachineClass *m) 381 { 382 pc_q35_4_2_machine_options(m); 383 m->alias = NULL; 384 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 385 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 386 } 387 388 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 389 pc_q35_4_1_machine_options); 390 391 static void pc_q35_4_0_1_machine_options(MachineClass *m) 392 { 393 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 394 pc_q35_4_1_machine_options(m); 395 m->alias = NULL; 396 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 397 /* 398 * This is the default machine for the 4.0-stable branch. It is basically 399 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 400 * 4.0 compat props. 401 */ 402 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 403 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 404 } 405 406 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 407 pc_q35_4_0_1_machine_options); 408 409 static void pc_q35_4_0_machine_options(MachineClass *m) 410 { 411 pc_q35_4_0_1_machine_options(m); 412 m->default_kernel_irqchip_split = true; 413 m->alias = NULL; 414 /* Compat props are applied by the 4.0.1 machine */ 415 } 416 417 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 418 pc_q35_4_0_machine_options); 419 420 static void pc_q35_3_1_machine_options(MachineClass *m) 421 { 422 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 423 424 pc_q35_4_0_machine_options(m); 425 m->default_kernel_irqchip_split = false; 426 pcmc->do_not_add_smb_acpi = true; 427 m->smbus_no_migration_support = true; 428 m->alias = NULL; 429 pcmc->pvh_enabled = false; 430 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 431 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 432 } 433 434 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 435 pc_q35_3_1_machine_options); 436 437 static void pc_q35_3_0_machine_options(MachineClass *m) 438 { 439 pc_q35_3_1_machine_options(m); 440 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 441 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 442 } 443 444 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 445 pc_q35_3_0_machine_options); 446 447 static void pc_q35_2_12_machine_options(MachineClass *m) 448 { 449 pc_q35_3_0_machine_options(m); 450 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 451 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 452 } 453 454 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 455 pc_q35_2_12_machine_options); 456 457 static void pc_q35_2_11_machine_options(MachineClass *m) 458 { 459 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 460 461 pc_q35_2_12_machine_options(m); 462 pcmc->default_nic_model = "e1000"; 463 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 464 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 465 } 466 467 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 468 pc_q35_2_11_machine_options); 469 470 static void pc_q35_2_10_machine_options(MachineClass *m) 471 { 472 pc_q35_2_11_machine_options(m); 473 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 474 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 475 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 476 m->auto_enable_numa_with_memhp = false; 477 } 478 479 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 480 pc_q35_2_10_machine_options); 481 482 static void pc_q35_2_9_machine_options(MachineClass *m) 483 { 484 pc_q35_2_10_machine_options(m); 485 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 486 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 487 } 488 489 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 490 pc_q35_2_9_machine_options); 491 492 static void pc_q35_2_8_machine_options(MachineClass *m) 493 { 494 pc_q35_2_9_machine_options(m); 495 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 496 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 497 } 498 499 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 500 pc_q35_2_8_machine_options); 501 502 static void pc_q35_2_7_machine_options(MachineClass *m) 503 { 504 pc_q35_2_8_machine_options(m); 505 m->max_cpus = 255; 506 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 507 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 508 } 509 510 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 511 pc_q35_2_7_machine_options); 512 513 static void pc_q35_2_6_machine_options(MachineClass *m) 514 { 515 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 516 517 pc_q35_2_7_machine_options(m); 518 pcmc->legacy_cpu_hotplug = true; 519 pcmc->linuxboot_dma_enabled = false; 520 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 521 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 522 } 523 524 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 525 pc_q35_2_6_machine_options); 526 527 static void pc_q35_2_5_machine_options(MachineClass *m) 528 { 529 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 530 531 pc_q35_2_6_machine_options(m); 532 pcmc->save_tsc_khz = false; 533 m->legacy_fw_cfg_order = 1; 534 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 535 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 536 } 537 538 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 539 pc_q35_2_5_machine_options); 540 541 static void pc_q35_2_4_machine_options(MachineClass *m) 542 { 543 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 544 545 pc_q35_2_5_machine_options(m); 546 m->hw_version = "2.4.0"; 547 pcmc->broken_reserved_end = true; 548 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 549 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 550 } 551 552 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 553 pc_q35_2_4_machine_options); 554