1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/char/parallel-isa.h" 35 #include "hw/loader.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "sysemu/tcg.h" 39 #include "sysemu/kvm.h" 40 #include "hw/i386/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/pci/pcie_port.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/virtio/virtio-iommu.h" 49 #include "hw/display/ramfb.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci-pci.h" 52 #include "hw/intc/ioapic.h" 53 #include "hw/southbridge/ich9.h" 54 #include "hw/usb.h" 55 #include "hw/usb/hcd-uhci.h" 56 #include "qapi/error.h" 57 #include "qemu/error-report.h" 58 #include "sysemu/numa.h" 59 #include "hw/hyperv/vmbus-bridge.h" 60 #include "hw/mem/nvdimm.h" 61 #include "hw/i386/acpi-build.h" 62 #include "target/i386/cpu.h" 63 64 /* ICH9 AHCI has 6 ports */ 65 #define MAX_SATA_PORTS 6 66 67 static GlobalProperty pc_q35_compat_defaults[] = { 68 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "39" }, 69 }; 70 static const size_t pc_q35_compat_defaults_len = 71 G_N_ELEMENTS(pc_q35_compat_defaults); 72 73 struct ehci_companions { 74 const char *name; 75 int func; 76 int port; 77 }; 78 79 static const struct ehci_companions ich9_1d[] = { 80 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 81 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 82 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 83 }; 84 85 static const struct ehci_companions ich9_1a[] = { 86 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 87 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 88 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 89 }; 90 91 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 92 { 93 const struct ehci_companions *comp; 94 PCIDevice *ehci, *uhci; 95 BusState *usbbus; 96 const char *name; 97 int i; 98 99 switch (slot) { 100 case 0x1d: 101 name = "ich9-usb-ehci1"; 102 comp = ich9_1d; 103 break; 104 case 0x1a: 105 name = "ich9-usb-ehci2"; 106 comp = ich9_1a; 107 break; 108 default: 109 return -1; 110 } 111 112 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 113 pci_realize_and_unref(ehci, bus, &error_fatal); 114 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 115 116 for (i = 0; i < 3; i++) { 117 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 118 comp[i].name); 119 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 120 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 121 pci_realize_and_unref(uhci, bus, &error_fatal); 122 } 123 return 0; 124 } 125 126 /* PC hardware initialisation */ 127 static void pc_q35_init(MachineState *machine) 128 { 129 PCMachineState *pcms = PC_MACHINE(machine); 130 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 131 X86MachineState *x86ms = X86_MACHINE(machine); 132 Object *phb; 133 PCIDevice *lpc; 134 DeviceState *lpc_dev; 135 MemoryRegion *system_memory = get_system_memory(); 136 MemoryRegion *system_io = get_system_io(); 137 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 138 GSIState *gsi_state; 139 ISABus *isa_bus; 140 int i; 141 ram_addr_t lowmem; 142 DriveInfo *hd[MAX_SATA_PORTS]; 143 MachineClass *mc = MACHINE_GET_CLASS(machine); 144 bool acpi_pcihp; 145 bool keep_pci_slot_hpc; 146 uint64_t pci_hole64_size = 0; 147 148 assert(pcmc->pci_enabled); 149 150 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 151 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 152 * also known as MMCFG). 153 * If it doesn't, we need to split it in chunks below and above 4G. 154 * In any case, try to make sure that guest addresses aligned at 155 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 156 */ 157 if (machine->ram_size >= 0xb0000000) { 158 lowmem = 0x80000000; 159 } else { 160 lowmem = 0xb0000000; 161 } 162 163 /* Handle the machine opt max-ram-below-4g. It is basically doing 164 * min(qemu limit, user limit). 165 */ 166 if (!pcms->max_ram_below_4g) { 167 pcms->max_ram_below_4g = 4 * GiB; 168 } 169 if (lowmem > pcms->max_ram_below_4g) { 170 lowmem = pcms->max_ram_below_4g; 171 if (machine->ram_size - lowmem > lowmem && 172 lowmem & (1 * GiB - 1)) { 173 warn_report("There is possibly poor performance as the ram size " 174 " (0x%" PRIx64 ") is more then twice the size of" 175 " max-ram-below-4g (%"PRIu64") and" 176 " max-ram-below-4g is not a multiple of 1G.", 177 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 178 } 179 } 180 181 if (machine->ram_size >= lowmem) { 182 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 183 x86ms->below_4g_mem_size = lowmem; 184 } else { 185 x86ms->above_4g_mem_size = 0; 186 x86ms->below_4g_mem_size = machine->ram_size; 187 } 188 189 pc_machine_init_sgx_epc(pcms); 190 x86_cpus_init(x86ms, pcmc->default_cpu_version); 191 192 if (kvm_enabled()) { 193 kvmclock_create(pcmc->kvmclock_create_always); 194 } 195 196 /* create pci host bus */ 197 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 198 199 pci_hole64_size = object_property_get_uint(phb, 200 PCI_HOST_PROP_PCI_HOLE64_SIZE, 201 &error_abort); 202 203 /* allocate ram and load rom/bios */ 204 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 205 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 206 207 object_property_add_child(OBJECT(machine), "q35", phb); 208 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 209 OBJECT(machine->ram), NULL); 210 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 211 OBJECT(pci_memory), NULL); 212 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 213 OBJECT(system_memory), NULL); 214 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 215 OBJECT(system_io), NULL); 216 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 217 x86ms->below_4g_mem_size, NULL); 218 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 219 x86ms->above_4g_mem_size, NULL); 220 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 221 pcms->default_bus_bypass_iommu, NULL); 222 object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES, 223 x86_machine_is_smm_enabled(x86ms), NULL); 224 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 225 226 /* pci */ 227 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 228 229 /* irq lines */ 230 gsi_state = pc_gsi_create(&x86ms->gsi, true); 231 232 /* create ISA bus */ 233 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 234 TYPE_ICH9_LPC_DEVICE); 235 lpc_dev = DEVICE(lpc); 236 qdev_prop_set_bit(lpc_dev, "smm-enabled", 237 x86_machine_is_smm_enabled(x86ms)); 238 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 239 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 240 } 241 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal); 242 243 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 244 245 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 246 TYPE_HOTPLUG_HANDLER, 247 (Object **)&x86ms->acpi_dev, 248 object_property_allow_set_link, 249 OBJ_PROP_LINK_STRONG); 250 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 251 OBJECT(lpc), &error_abort); 252 253 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 254 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 255 NULL); 256 257 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 258 "x-keep-pci-slot-hpc", 259 NULL); 260 261 if (!keep_pci_slot_hpc && acpi_pcihp) { 262 object_register_sugar_prop(TYPE_PCIE_SLOT, 263 "x-do-not-expose-native-hotplug-cap", 264 "true", true); 265 } 266 267 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 268 269 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 270 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 271 } 272 273 ioapic_init_gsi(gsi_state, OBJECT(phb)); 274 275 if (tcg_enabled()) { 276 x86_register_ferr_irq(x86ms->gsi[13]); 277 } 278 279 /* init basic PC hardware */ 280 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy, 281 0xff0104); 282 283 if (pcms->sata_enabled) { 284 PCIDevice *pdev; 285 AHCIPCIState *ich9; 286 287 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 288 pdev = pci_create_simple_multifunction(pcms->pcibus, 289 PCI_DEVFN(ICH9_SATA1_DEV, 290 ICH9_SATA1_FUNC), 291 "ich9-ahci"); 292 ich9 = ICH9_AHCI(pdev); 293 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 294 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 295 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 296 ide_drive_get(hd, ich9->ahci.ports); 297 ahci_ide_create_devs(&ich9->ahci, hd); 298 } 299 300 if (machine_usb(machine)) { 301 /* Should we create 6 UHCI according to ich9 spec? */ 302 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d); 303 } 304 305 if (pcms->smbus_enabled) { 306 PCIDevice *smb; 307 308 /* TODO: Populate SPD eeprom data. */ 309 smb = pci_create_simple_multifunction(pcms->pcibus, 310 PCI_DEVFN(ICH9_SMB_DEV, 311 ICH9_SMB_FUNC), 312 TYPE_ICH9_SMB_DEVICE); 313 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 314 315 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 316 } 317 318 /* the rest devices to which pci devfn is automatically assigned */ 319 pc_vga_init(isa_bus, pcms->pcibus); 320 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 321 322 if (machine->nvdimms_state->is_enabled) { 323 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 324 x86_nvdimm_acpi_dsmio, 325 x86ms->fw_cfg, OBJECT(pcms)); 326 } 327 } 328 329 #define DEFINE_Q35_MACHINE(major, minor) \ 330 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, major, minor); 331 332 #define DEFINE_Q35_MACHINE_BUGFIX(major, minor, micro) \ 333 DEFINE_PC_VER_MACHINE(pc_q35, "pc-q35", pc_q35_init, major, minor, micro); 334 335 static void pc_q35_machine_options(MachineClass *m) 336 { 337 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 338 pcmc->pci_root_uid = 0; 339 pcmc->default_cpu_version = 1; 340 341 m->family = "pc_q35"; 342 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 343 m->units_per_default_bus = 1; 344 m->default_machine_opts = "firmware=bios-256k.bin"; 345 m->default_display = "std"; 346 m->default_nic = "e1000e"; 347 m->default_kernel_irqchip_split = false; 348 m->no_floppy = 1; 349 m->max_cpus = 4096; 350 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 351 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 352 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 353 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 354 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 355 compat_props_add(m->compat_props, 356 pc_q35_compat_defaults, pc_q35_compat_defaults_len); 357 } 358 359 static void pc_q35_machine_9_1_options(MachineClass *m) 360 { 361 pc_q35_machine_options(m); 362 m->alias = "q35"; 363 } 364 365 DEFINE_Q35_MACHINE(9, 1); 366 367 static void pc_q35_machine_9_0_options(MachineClass *m) 368 { 369 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 370 pc_q35_machine_9_1_options(m); 371 m->alias = NULL; 372 m->smbios_memory_device_size = 16 * GiB; 373 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); 374 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); 375 pcmc->isa_bios_alias = false; 376 } 377 378 DEFINE_Q35_MACHINE(9, 0); 379 380 static void pc_q35_machine_8_2_options(MachineClass *m) 381 { 382 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 383 pc_q35_machine_9_0_options(m); 384 m->max_cpus = 1024; 385 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 386 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 387 /* For pc-q35-8.2 and 8.1, use SMBIOS 3.X by default */ 388 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 389 } 390 391 DEFINE_Q35_MACHINE(8, 2); 392 393 static void pc_q35_machine_8_1_options(MachineClass *m) 394 { 395 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 396 pc_q35_machine_8_2_options(m); 397 pcmc->broken_32bit_mem_addr_check = true; 398 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 399 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 400 } 401 402 DEFINE_Q35_MACHINE(8, 1); 403 404 static void pc_q35_machine_8_0_options(MachineClass *m) 405 { 406 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 407 408 pc_q35_machine_8_1_options(m); 409 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 410 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 411 412 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 413 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 414 m->max_cpus = 288; 415 } 416 417 DEFINE_Q35_MACHINE(8, 0); 418 419 static void pc_q35_machine_7_2_options(MachineClass *m) 420 { 421 pc_q35_machine_8_0_options(m); 422 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 423 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 424 } 425 426 DEFINE_Q35_MACHINE(7, 2); 427 428 static void pc_q35_machine_7_1_options(MachineClass *m) 429 { 430 pc_q35_machine_7_2_options(m); 431 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 432 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 433 } 434 435 DEFINE_Q35_MACHINE(7, 1); 436 437 static void pc_q35_machine_7_0_options(MachineClass *m) 438 { 439 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 440 pc_q35_machine_7_1_options(m); 441 pcmc->enforce_amd_1tb_hole = false; 442 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 443 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 444 } 445 446 DEFINE_Q35_MACHINE(7, 0); 447 448 static void pc_q35_machine_6_2_options(MachineClass *m) 449 { 450 pc_q35_machine_7_0_options(m); 451 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 452 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 453 } 454 455 DEFINE_Q35_MACHINE(6, 2); 456 457 static void pc_q35_machine_6_1_options(MachineClass *m) 458 { 459 pc_q35_machine_6_2_options(m); 460 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 461 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 462 m->smp_props.prefer_sockets = true; 463 } 464 465 DEFINE_Q35_MACHINE(6, 1); 466 467 static void pc_q35_machine_6_0_options(MachineClass *m) 468 { 469 pc_q35_machine_6_1_options(m); 470 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 471 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 472 } 473 474 DEFINE_Q35_MACHINE(6, 0); 475 476 static void pc_q35_machine_5_2_options(MachineClass *m) 477 { 478 pc_q35_machine_6_0_options(m); 479 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 480 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 481 } 482 483 DEFINE_Q35_MACHINE(5, 2); 484 485 static void pc_q35_machine_5_1_options(MachineClass *m) 486 { 487 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 488 489 pc_q35_machine_5_2_options(m); 490 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 491 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 492 pcmc->kvmclock_create_always = false; 493 pcmc->pci_root_uid = 1; 494 } 495 496 DEFINE_Q35_MACHINE(5, 1); 497 498 static void pc_q35_machine_5_0_options(MachineClass *m) 499 { 500 pc_q35_machine_5_1_options(m); 501 m->numa_mem_supported = true; 502 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 503 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 504 m->auto_enable_numa_with_memdev = false; 505 } 506 507 DEFINE_Q35_MACHINE(5, 0); 508 509 static void pc_q35_machine_4_2_options(MachineClass *m) 510 { 511 pc_q35_machine_5_0_options(m); 512 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 513 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 514 } 515 516 DEFINE_Q35_MACHINE(4, 2); 517 518 static void pc_q35_machine_4_1_options(MachineClass *m) 519 { 520 pc_q35_machine_4_2_options(m); 521 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 522 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 523 } 524 525 DEFINE_Q35_MACHINE(4, 1); 526 527 static void pc_q35_machine_4_0_1_options(MachineClass *m) 528 { 529 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 530 pc_q35_machine_4_1_options(m); 531 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 532 /* 533 * This is the default machine for the 4.0-stable branch. It is basically 534 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 535 * 4.0 compat props. 536 */ 537 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 538 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 539 } 540 541 DEFINE_Q35_MACHINE_BUGFIX(4, 0, 1); 542 543 static void pc_q35_machine_4_0_options(MachineClass *m) 544 { 545 pc_q35_machine_4_0_1_options(m); 546 m->default_kernel_irqchip_split = true; 547 /* Compat props are applied by the 4.0.1 machine */ 548 } 549 550 DEFINE_Q35_MACHINE(4, 0); 551 552 static void pc_q35_machine_3_1_options(MachineClass *m) 553 { 554 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 555 556 pc_q35_machine_4_0_options(m); 557 m->default_kernel_irqchip_split = false; 558 m->smbus_no_migration_support = true; 559 pcmc->pvh_enabled = false; 560 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 561 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 562 } 563 564 DEFINE_Q35_MACHINE(3, 1); 565 566 static void pc_q35_machine_3_0_options(MachineClass *m) 567 { 568 pc_q35_machine_3_1_options(m); 569 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 570 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 571 } 572 573 DEFINE_Q35_MACHINE(3, 0); 574 575 static void pc_q35_machine_2_12_options(MachineClass *m) 576 { 577 pc_q35_machine_3_0_options(m); 578 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 579 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 580 } 581 582 DEFINE_Q35_MACHINE(2, 12); 583 584 static void pc_q35_machine_2_11_options(MachineClass *m) 585 { 586 pc_q35_machine_2_12_options(m); 587 m->default_nic = "e1000"; 588 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 589 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 590 } 591 592 DEFINE_Q35_MACHINE(2, 11); 593 594 static void pc_q35_machine_2_10_options(MachineClass *m) 595 { 596 pc_q35_machine_2_11_options(m); 597 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 598 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 599 m->auto_enable_numa_with_memhp = false; 600 } 601 602 DEFINE_Q35_MACHINE(2, 10); 603 604 static void pc_q35_machine_2_9_options(MachineClass *m) 605 { 606 pc_q35_machine_2_10_options(m); 607 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 608 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 609 } 610 611 DEFINE_Q35_MACHINE(2, 9); 612 613 static void pc_q35_machine_2_8_options(MachineClass *m) 614 { 615 pc_q35_machine_2_9_options(m); 616 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 617 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 618 } 619 620 DEFINE_Q35_MACHINE(2, 8); 621 622 static void pc_q35_machine_2_7_options(MachineClass *m) 623 { 624 pc_q35_machine_2_8_options(m); 625 m->max_cpus = 255; 626 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 627 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 628 } 629 630 DEFINE_Q35_MACHINE(2, 7); 631 632 static void pc_q35_machine_2_6_options(MachineClass *m) 633 { 634 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 635 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 636 637 pc_q35_machine_2_7_options(m); 638 pcmc->legacy_cpu_hotplug = true; 639 x86mc->fwcfg_dma_enabled = false; 640 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 641 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 642 } 643 644 DEFINE_Q35_MACHINE(2, 6); 645 646 static void pc_q35_machine_2_5_options(MachineClass *m) 647 { 648 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 649 650 pc_q35_machine_2_6_options(m); 651 x86mc->save_tsc_khz = false; 652 m->legacy_fw_cfg_order = 1; 653 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 654 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 655 } 656 657 DEFINE_Q35_MACHINE(2, 5); 658 659 static void pc_q35_machine_2_4_options(MachineClass *m) 660 { 661 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 662 663 pc_q35_machine_2_5_options(m); 664 m->hw_version = "2.4.0"; 665 pcmc->broken_reserved_end = true; 666 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 667 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 668 } 669 670 DEFINE_Q35_MACHINE(2, 4); 671