1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/rtc/mc146818rtc.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "hw/pci/pcie_port.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/i386/x86.h" 42 #include "hw/i386/pc.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/i386/amd_iommu.h" 45 #include "hw/i386/intel_iommu.h" 46 #include "hw/display/ramfb.h" 47 #include "hw/firmware/smbios.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci.h" 50 #include "hw/usb.h" 51 #include "hw/usb/hcd-uhci.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "sysemu/numa.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 #include "hw/mem/nvdimm.h" 57 #include "hw/i386/acpi-build.h" 58 59 /* ICH9 AHCI has 6 ports */ 60 #define MAX_SATA_PORTS 6 61 62 struct ehci_companions { 63 const char *name; 64 int func; 65 int port; 66 }; 67 68 static const struct ehci_companions ich9_1d[] = { 69 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 70 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 71 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 72 }; 73 74 static const struct ehci_companions ich9_1a[] = { 75 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 76 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 77 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 78 }; 79 80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 81 { 82 const struct ehci_companions *comp; 83 PCIDevice *ehci, *uhci; 84 BusState *usbbus; 85 const char *name; 86 int i; 87 88 switch (slot) { 89 case 0x1d: 90 name = "ich9-usb-ehci1"; 91 comp = ich9_1d; 92 break; 93 case 0x1a: 94 name = "ich9-usb-ehci2"; 95 comp = ich9_1a; 96 break; 97 default: 98 return -1; 99 } 100 101 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 102 pci_realize_and_unref(ehci, bus, &error_fatal); 103 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 104 105 for (i = 0; i < 3; i++) { 106 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 107 comp[i].name); 108 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 109 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 110 pci_realize_and_unref(uhci, bus, &error_fatal); 111 } 112 return 0; 113 } 114 115 /* PC hardware initialisation */ 116 static void pc_q35_init(MachineState *machine) 117 { 118 PCMachineState *pcms = PC_MACHINE(machine); 119 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 120 X86MachineState *x86ms = X86_MACHINE(machine); 121 Q35PCIHost *q35_host; 122 PCIHostState *phb; 123 PCIBus *host_bus; 124 PCIDevice *lpc; 125 DeviceState *lpc_dev; 126 BusState *idebus[MAX_SATA_PORTS]; 127 ISADevice *rtc_state; 128 MemoryRegion *system_io = get_system_io(); 129 MemoryRegion *pci_memory; 130 MemoryRegion *rom_memory; 131 MemoryRegion *ram_memory; 132 GSIState *gsi_state; 133 ISABus *isa_bus; 134 int i; 135 PCIDevice *ahci; 136 ram_addr_t lowmem; 137 DriveInfo *hd[MAX_SATA_PORTS]; 138 MachineClass *mc = MACHINE_GET_CLASS(machine); 139 bool acpi_pcihp; 140 bool keep_pci_slot_hpc; 141 uint64_t pci_hole64_size = 0; 142 143 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 144 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 145 * also known as MMCFG). 146 * If it doesn't, we need to split it in chunks below and above 4G. 147 * In any case, try to make sure that guest addresses aligned at 148 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 149 */ 150 if (machine->ram_size >= 0xb0000000) { 151 lowmem = 0x80000000; 152 } else { 153 lowmem = 0xb0000000; 154 } 155 156 /* Handle the machine opt max-ram-below-4g. It is basically doing 157 * min(qemu limit, user limit). 158 */ 159 if (!pcms->max_ram_below_4g) { 160 pcms->max_ram_below_4g = 4 * GiB; 161 } 162 if (lowmem > pcms->max_ram_below_4g) { 163 lowmem = pcms->max_ram_below_4g; 164 if (machine->ram_size - lowmem > lowmem && 165 lowmem & (1 * GiB - 1)) { 166 warn_report("There is possibly poor performance as the ram size " 167 " (0x%" PRIx64 ") is more then twice the size of" 168 " max-ram-below-4g (%"PRIu64") and" 169 " max-ram-below-4g is not a multiple of 1G.", 170 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 171 } 172 } 173 174 if (machine->ram_size >= lowmem) { 175 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 176 x86ms->below_4g_mem_size = lowmem; 177 } else { 178 x86ms->above_4g_mem_size = 0; 179 x86ms->below_4g_mem_size = machine->ram_size; 180 } 181 182 pc_machine_init_sgx_epc(pcms); 183 x86_cpus_init(x86ms, pcmc->default_cpu_version); 184 185 kvmclock_create(pcmc->kvmclock_create_always); 186 187 /* pci enabled */ 188 if (pcmc->pci_enabled) { 189 pci_memory = g_new(MemoryRegion, 1); 190 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 191 rom_memory = pci_memory; 192 } else { 193 pci_memory = NULL; 194 rom_memory = get_system_memory(); 195 } 196 197 pc_guest_info_init(pcms); 198 199 if (pcmc->smbios_defaults) { 200 /* These values are guest ABI, do not change */ 201 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 202 mc->name, pcmc->smbios_legacy_mode, 203 pcmc->smbios_uuid_encoded, 204 pcms->smbios_entry_point_type); 205 } 206 207 /* create pci host bus */ 208 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 209 210 if (pcmc->pci_enabled) { 211 pci_hole64_size = object_property_get_uint(OBJECT(q35_host), 212 PCI_HOST_PROP_PCI_HOLE64_SIZE, 213 &error_abort); 214 } 215 216 /* allocate ram and load rom/bios */ 217 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, 218 pci_hole64_size); 219 220 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 221 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 222 OBJECT(ram_memory), NULL); 223 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 224 OBJECT(pci_memory), NULL); 225 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 226 OBJECT(get_system_memory()), NULL); 227 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 228 OBJECT(system_io), NULL); 229 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 230 x86ms->below_4g_mem_size, NULL); 231 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 232 x86ms->above_4g_mem_size, NULL); 233 /* pci */ 234 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 235 phb = PCI_HOST_BRIDGE(q35_host); 236 host_bus = phb->bus; 237 /* create ISA bus */ 238 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 239 ICH9_LPC_FUNC), true, 240 TYPE_ICH9_LPC_DEVICE); 241 242 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 243 TYPE_HOTPLUG_HANDLER, 244 (Object **)&x86ms->acpi_dev, 245 object_property_allow_set_link, 246 OBJ_PROP_LINK_STRONG); 247 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 248 OBJECT(lpc), &error_abort); 249 250 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 251 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 252 NULL); 253 254 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 255 "x-keep-pci-slot-hpc", 256 NULL); 257 258 if (!keep_pci_slot_hpc && acpi_pcihp) { 259 object_register_sugar_prop(TYPE_PCIE_SLOT, 260 "x-do-not-expose-native-hotplug-cap", 261 "true", true); 262 } 263 264 /* irq lines */ 265 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 266 267 lpc_dev = DEVICE(lpc); 268 for (i = 0; i < GSI_NUM_PINS; i++) { 269 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 270 } 271 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 272 273 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 274 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 275 } 276 277 if (pcmc->pci_enabled) { 278 ioapic_init_gsi(gsi_state, "q35"); 279 } 280 281 if (tcg_enabled()) { 282 x86_register_ferr_irq(x86ms->gsi[13]); 283 } 284 285 assert(pcms->vmport != ON_OFF_AUTO__MAX); 286 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 287 pcms->vmport = ON_OFF_AUTO_ON; 288 } 289 290 /* init basic PC hardware */ 291 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 292 0xff0104); 293 294 /* connect pm stuff to lpc */ 295 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 296 297 if (pcms->sata_enabled) { 298 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 299 ahci = pci_create_simple_multifunction(host_bus, 300 PCI_DEVFN(ICH9_SATA1_DEV, 301 ICH9_SATA1_FUNC), 302 true, "ich9-ahci"); 303 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 304 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 305 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 306 ide_drive_get(hd, ahci_get_num_ports(ahci)); 307 ahci_ide_create_devs(ahci, hd); 308 } else { 309 idebus[0] = idebus[1] = NULL; 310 } 311 312 if (machine_usb(machine)) { 313 /* Should we create 6 UHCI according to ich9 spec? */ 314 ehci_create_ich9_with_companions(host_bus, 0x1d); 315 } 316 317 if (pcms->smbus_enabled) { 318 /* TODO: Populate SPD eeprom data. */ 319 pcms->smbus = ich9_smb_init(host_bus, 320 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 321 0xb100); 322 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 323 } 324 325 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 326 327 /* the rest devices to which pci devfn is automatically assigned */ 328 pc_vga_init(isa_bus, host_bus); 329 pc_nic_init(pcmc, isa_bus, host_bus); 330 331 if (machine->nvdimms_state->is_enabled) { 332 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 333 x86_nvdimm_acpi_dsmio, 334 x86ms->fw_cfg, OBJECT(pcms)); 335 } 336 } 337 338 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 339 static void pc_init_##suffix(MachineState *machine) \ 340 { \ 341 void (*compat)(MachineState *m) = (compatfn); \ 342 if (compat) { \ 343 compat(machine); \ 344 } \ 345 pc_q35_init(machine); \ 346 } \ 347 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 348 349 350 static void pc_q35_machine_options(MachineClass *m) 351 { 352 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 353 pcmc->default_nic_model = "e1000e"; 354 pcmc->pci_root_uid = 0; 355 pcmc->default_cpu_version = 1; 356 357 m->family = "pc_q35"; 358 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 359 m->units_per_default_bus = 1; 360 m->default_machine_opts = "firmware=bios-256k.bin"; 361 m->default_display = "std"; 362 m->default_kernel_irqchip_split = false; 363 m->no_floppy = 1; 364 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 365 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 366 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 367 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 368 m->max_cpus = 288; 369 } 370 371 static void pc_q35_8_0_machine_options(MachineClass *m) 372 { 373 pc_q35_machine_options(m); 374 m->alias = "q35"; 375 } 376 377 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 378 pc_q35_8_0_machine_options); 379 380 static void pc_q35_7_2_machine_options(MachineClass *m) 381 { 382 pc_q35_8_0_machine_options(m); 383 m->alias = NULL; 384 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 385 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 386 } 387 388 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 389 pc_q35_7_2_machine_options); 390 391 static void pc_q35_7_1_machine_options(MachineClass *m) 392 { 393 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 394 pc_q35_7_2_machine_options(m); 395 pcmc->legacy_no_rng_seed = true; 396 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 397 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 398 } 399 400 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 401 pc_q35_7_1_machine_options); 402 403 static void pc_q35_7_0_machine_options(MachineClass *m) 404 { 405 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 406 pc_q35_7_1_machine_options(m); 407 pcmc->enforce_amd_1tb_hole = false; 408 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 409 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 410 } 411 412 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 413 pc_q35_7_0_machine_options); 414 415 static void pc_q35_6_2_machine_options(MachineClass *m) 416 { 417 pc_q35_7_0_machine_options(m); 418 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 419 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 420 } 421 422 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 423 pc_q35_6_2_machine_options); 424 425 static void pc_q35_6_1_machine_options(MachineClass *m) 426 { 427 pc_q35_6_2_machine_options(m); 428 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 429 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 430 m->smp_props.prefer_sockets = true; 431 } 432 433 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 434 pc_q35_6_1_machine_options); 435 436 static void pc_q35_6_0_machine_options(MachineClass *m) 437 { 438 pc_q35_6_1_machine_options(m); 439 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 440 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 441 } 442 443 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 444 pc_q35_6_0_machine_options); 445 446 static void pc_q35_5_2_machine_options(MachineClass *m) 447 { 448 pc_q35_6_0_machine_options(m); 449 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 450 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 451 } 452 453 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 454 pc_q35_5_2_machine_options); 455 456 static void pc_q35_5_1_machine_options(MachineClass *m) 457 { 458 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 459 460 pc_q35_5_2_machine_options(m); 461 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 462 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 463 pcmc->kvmclock_create_always = false; 464 pcmc->pci_root_uid = 1; 465 } 466 467 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 468 pc_q35_5_1_machine_options); 469 470 static void pc_q35_5_0_machine_options(MachineClass *m) 471 { 472 pc_q35_5_1_machine_options(m); 473 m->numa_mem_supported = true; 474 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 475 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 476 m->auto_enable_numa_with_memdev = false; 477 } 478 479 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 480 pc_q35_5_0_machine_options); 481 482 static void pc_q35_4_2_machine_options(MachineClass *m) 483 { 484 pc_q35_5_0_machine_options(m); 485 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 486 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 487 } 488 489 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 490 pc_q35_4_2_machine_options); 491 492 static void pc_q35_4_1_machine_options(MachineClass *m) 493 { 494 pc_q35_4_2_machine_options(m); 495 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 496 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 497 } 498 499 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 500 pc_q35_4_1_machine_options); 501 502 static void pc_q35_4_0_1_machine_options(MachineClass *m) 503 { 504 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 505 pc_q35_4_1_machine_options(m); 506 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 507 /* 508 * This is the default machine for the 4.0-stable branch. It is basically 509 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 510 * 4.0 compat props. 511 */ 512 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 513 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 514 } 515 516 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 517 pc_q35_4_0_1_machine_options); 518 519 static void pc_q35_4_0_machine_options(MachineClass *m) 520 { 521 pc_q35_4_0_1_machine_options(m); 522 m->default_kernel_irqchip_split = true; 523 /* Compat props are applied by the 4.0.1 machine */ 524 } 525 526 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 527 pc_q35_4_0_machine_options); 528 529 static void pc_q35_3_1_machine_options(MachineClass *m) 530 { 531 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 532 533 pc_q35_4_0_machine_options(m); 534 m->default_kernel_irqchip_split = false; 535 m->smbus_no_migration_support = true; 536 pcmc->pvh_enabled = false; 537 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 538 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 539 } 540 541 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 542 pc_q35_3_1_machine_options); 543 544 static void pc_q35_3_0_machine_options(MachineClass *m) 545 { 546 pc_q35_3_1_machine_options(m); 547 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 548 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 549 } 550 551 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 552 pc_q35_3_0_machine_options); 553 554 static void pc_q35_2_12_machine_options(MachineClass *m) 555 { 556 pc_q35_3_0_machine_options(m); 557 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 558 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 559 } 560 561 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 562 pc_q35_2_12_machine_options); 563 564 static void pc_q35_2_11_machine_options(MachineClass *m) 565 { 566 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 567 568 pc_q35_2_12_machine_options(m); 569 pcmc->default_nic_model = "e1000"; 570 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 571 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 572 } 573 574 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 575 pc_q35_2_11_machine_options); 576 577 static void pc_q35_2_10_machine_options(MachineClass *m) 578 { 579 pc_q35_2_11_machine_options(m); 580 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 581 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 582 m->auto_enable_numa_with_memhp = false; 583 } 584 585 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 586 pc_q35_2_10_machine_options); 587 588 static void pc_q35_2_9_machine_options(MachineClass *m) 589 { 590 pc_q35_2_10_machine_options(m); 591 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 592 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 593 } 594 595 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 596 pc_q35_2_9_machine_options); 597 598 static void pc_q35_2_8_machine_options(MachineClass *m) 599 { 600 pc_q35_2_9_machine_options(m); 601 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 602 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 603 } 604 605 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 606 pc_q35_2_8_machine_options); 607 608 static void pc_q35_2_7_machine_options(MachineClass *m) 609 { 610 pc_q35_2_8_machine_options(m); 611 m->max_cpus = 255; 612 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 613 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 614 } 615 616 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 617 pc_q35_2_7_machine_options); 618 619 static void pc_q35_2_6_machine_options(MachineClass *m) 620 { 621 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 622 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 623 624 pc_q35_2_7_machine_options(m); 625 pcmc->legacy_cpu_hotplug = true; 626 x86mc->fwcfg_dma_enabled = false; 627 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 628 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 629 } 630 631 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 632 pc_q35_2_6_machine_options); 633 634 static void pc_q35_2_5_machine_options(MachineClass *m) 635 { 636 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 637 638 pc_q35_2_6_machine_options(m); 639 x86mc->save_tsc_khz = false; 640 m->legacy_fw_cfg_order = 1; 641 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 642 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 643 } 644 645 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 646 pc_q35_2_5_machine_options); 647 648 static void pc_q35_2_4_machine_options(MachineClass *m) 649 { 650 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 651 652 pc_q35_2_5_machine_options(m); 653 m->hw_version = "2.4.0"; 654 pcmc->broken_reserved_end = true; 655 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 656 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 657 } 658 659 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 660 pc_q35_2_4_machine_options); 661