1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/char/parallel-isa.h" 35 #include "hw/loader.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "sysemu/tcg.h" 39 #include "sysemu/kvm.h" 40 #include "hw/i386/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/pci/pcie_port.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/virtio/virtio-iommu.h" 49 #include "hw/display/ramfb.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci-pci.h" 52 #include "hw/intc/ioapic.h" 53 #include "hw/southbridge/ich9.h" 54 #include "hw/usb.h" 55 #include "hw/usb/hcd-uhci.h" 56 #include "qapi/error.h" 57 #include "qemu/error-report.h" 58 #include "sysemu/numa.h" 59 #include "hw/hyperv/vmbus-bridge.h" 60 #include "hw/mem/nvdimm.h" 61 #include "hw/i386/acpi-build.h" 62 #include "target/i386/cpu.h" 63 64 /* ICH9 AHCI has 6 ports */ 65 #define MAX_SATA_PORTS 6 66 67 static GlobalProperty pc_q35_compat_defaults[] = { 68 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "39" }, 69 }; 70 static const size_t pc_q35_compat_defaults_len = 71 G_N_ELEMENTS(pc_q35_compat_defaults); 72 73 struct ehci_companions { 74 const char *name; 75 int func; 76 int port; 77 }; 78 79 static const struct ehci_companions ich9_1d[] = { 80 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 81 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 82 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 83 }; 84 85 static const struct ehci_companions ich9_1a[] = { 86 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 87 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 88 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 89 }; 90 91 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 92 { 93 const struct ehci_companions *comp; 94 PCIDevice *ehci, *uhci; 95 BusState *usbbus; 96 const char *name; 97 int i; 98 99 switch (slot) { 100 case 0x1d: 101 name = "ich9-usb-ehci1"; 102 comp = ich9_1d; 103 break; 104 case 0x1a: 105 name = "ich9-usb-ehci2"; 106 comp = ich9_1a; 107 break; 108 default: 109 return -1; 110 } 111 112 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 113 pci_realize_and_unref(ehci, bus, &error_fatal); 114 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 115 116 for (i = 0; i < 3; i++) { 117 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 118 comp[i].name); 119 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 120 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 121 pci_realize_and_unref(uhci, bus, &error_fatal); 122 } 123 return 0; 124 } 125 126 /* PC hardware initialisation */ 127 static void pc_q35_init(MachineState *machine) 128 { 129 PCMachineState *pcms = PC_MACHINE(machine); 130 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 131 X86MachineState *x86ms = X86_MACHINE(machine); 132 Object *phb; 133 PCIDevice *lpc; 134 DeviceState *lpc_dev; 135 MemoryRegion *system_memory = get_system_memory(); 136 MemoryRegion *system_io = get_system_io(); 137 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 138 GSIState *gsi_state; 139 ISABus *isa_bus; 140 int i; 141 ram_addr_t lowmem; 142 DriveInfo *hd[MAX_SATA_PORTS]; 143 MachineClass *mc = MACHINE_GET_CLASS(machine); 144 bool acpi_pcihp; 145 bool keep_pci_slot_hpc; 146 uint64_t pci_hole64_size = 0; 147 148 assert(pcmc->pci_enabled); 149 150 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 151 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 152 * also known as MMCFG). 153 * If it doesn't, we need to split it in chunks below and above 4G. 154 * In any case, try to make sure that guest addresses aligned at 155 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 156 */ 157 if (machine->ram_size >= 0xb0000000) { 158 lowmem = 0x80000000; 159 } else { 160 lowmem = 0xb0000000; 161 } 162 163 /* Handle the machine opt max-ram-below-4g. It is basically doing 164 * min(qemu limit, user limit). 165 */ 166 if (!pcms->max_ram_below_4g) { 167 pcms->max_ram_below_4g = 4 * GiB; 168 } 169 if (lowmem > pcms->max_ram_below_4g) { 170 lowmem = pcms->max_ram_below_4g; 171 if (machine->ram_size - lowmem > lowmem && 172 lowmem & (1 * GiB - 1)) { 173 warn_report("There is possibly poor performance as the ram size " 174 " (0x%" PRIx64 ") is more then twice the size of" 175 " max-ram-below-4g (%"PRIu64") and" 176 " max-ram-below-4g is not a multiple of 1G.", 177 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 178 } 179 } 180 181 if (machine->ram_size >= lowmem) { 182 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 183 x86ms->below_4g_mem_size = lowmem; 184 } else { 185 x86ms->above_4g_mem_size = 0; 186 x86ms->below_4g_mem_size = machine->ram_size; 187 } 188 189 pc_machine_init_sgx_epc(pcms); 190 x86_cpus_init(x86ms, pcmc->default_cpu_version); 191 192 if (kvm_enabled()) { 193 kvmclock_create(pcmc->kvmclock_create_always); 194 } 195 196 /* create pci host bus */ 197 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 198 199 pci_hole64_size = object_property_get_uint(phb, 200 PCI_HOST_PROP_PCI_HOLE64_SIZE, 201 &error_abort); 202 203 /* allocate ram and load rom/bios */ 204 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 205 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 206 207 object_property_add_child(OBJECT(machine), "q35", phb); 208 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 209 OBJECT(machine->ram), NULL); 210 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 211 OBJECT(pci_memory), NULL); 212 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 213 OBJECT(system_memory), NULL); 214 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 215 OBJECT(system_io), NULL); 216 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 217 x86ms->below_4g_mem_size, NULL); 218 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 219 x86ms->above_4g_mem_size, NULL); 220 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 221 pcms->default_bus_bypass_iommu, NULL); 222 object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES, 223 x86_machine_is_smm_enabled(x86ms), NULL); 224 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 225 226 /* pci */ 227 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 228 229 /* irq lines */ 230 gsi_state = pc_gsi_create(&x86ms->gsi, true); 231 232 /* create ISA bus */ 233 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 234 TYPE_ICH9_LPC_DEVICE); 235 lpc_dev = DEVICE(lpc); 236 qdev_prop_set_bit(lpc_dev, "smm-enabled", 237 x86_machine_is_smm_enabled(x86ms)); 238 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 239 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 240 } 241 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal); 242 243 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 244 245 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 246 TYPE_HOTPLUG_HANDLER, 247 (Object **)&x86ms->acpi_dev, 248 object_property_allow_set_link, 249 OBJ_PROP_LINK_STRONG); 250 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 251 OBJECT(lpc), &error_abort); 252 253 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 254 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 255 NULL); 256 257 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 258 "x-keep-pci-slot-hpc", 259 NULL); 260 261 if (!keep_pci_slot_hpc && acpi_pcihp) { 262 object_register_sugar_prop(TYPE_PCIE_SLOT, 263 "x-do-not-expose-native-hotplug-cap", 264 "true", true); 265 } 266 267 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 268 269 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 270 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 271 } 272 273 ioapic_init_gsi(gsi_state, OBJECT(phb)); 274 275 if (tcg_enabled()) { 276 x86_register_ferr_irq(x86ms->gsi[13]); 277 } 278 279 assert(pcms->vmport != ON_OFF_AUTO__MAX); 280 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 281 pcms->vmport = ON_OFF_AUTO_ON; 282 } 283 284 /* init basic PC hardware */ 285 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy, 286 0xff0104); 287 288 if (pcms->sata_enabled) { 289 PCIDevice *pdev; 290 AHCIPCIState *ich9; 291 292 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 293 pdev = pci_create_simple_multifunction(pcms->pcibus, 294 PCI_DEVFN(ICH9_SATA1_DEV, 295 ICH9_SATA1_FUNC), 296 "ich9-ahci"); 297 ich9 = ICH9_AHCI(pdev); 298 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 299 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 300 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 301 ide_drive_get(hd, ich9->ahci.ports); 302 ahci_ide_create_devs(&ich9->ahci, hd); 303 } 304 305 if (machine_usb(machine)) { 306 /* Should we create 6 UHCI according to ich9 spec? */ 307 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d); 308 } 309 310 if (pcms->smbus_enabled) { 311 PCIDevice *smb; 312 313 /* TODO: Populate SPD eeprom data. */ 314 smb = pci_create_simple_multifunction(pcms->pcibus, 315 PCI_DEVFN(ICH9_SMB_DEV, 316 ICH9_SMB_FUNC), 317 TYPE_ICH9_SMB_DEVICE); 318 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 319 320 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 321 } 322 323 /* the rest devices to which pci devfn is automatically assigned */ 324 pc_vga_init(isa_bus, pcms->pcibus); 325 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 326 327 if (machine->nvdimms_state->is_enabled) { 328 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 329 x86_nvdimm_acpi_dsmio, 330 x86ms->fw_cfg, OBJECT(pcms)); 331 } 332 } 333 334 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 335 static void pc_init_##suffix(MachineState *machine) \ 336 { \ 337 void (*compat)(MachineState *m) = (compatfn); \ 338 if (compat) { \ 339 compat(machine); \ 340 } \ 341 pc_q35_init(machine); \ 342 } \ 343 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 344 345 346 static void pc_q35_machine_options(MachineClass *m) 347 { 348 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 349 pcmc->pci_root_uid = 0; 350 pcmc->default_cpu_version = 1; 351 352 m->family = "pc_q35"; 353 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 354 m->units_per_default_bus = 1; 355 m->default_machine_opts = "firmware=bios-256k.bin"; 356 m->default_display = "std"; 357 m->default_nic = "e1000e"; 358 m->default_kernel_irqchip_split = false; 359 m->no_floppy = 1; 360 m->max_cpus = 4096; 361 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 362 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 363 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 364 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 365 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 366 compat_props_add(m->compat_props, 367 pc_q35_compat_defaults, pc_q35_compat_defaults_len); 368 } 369 370 static void pc_q35_9_1_machine_options(MachineClass *m) 371 { 372 pc_q35_machine_options(m); 373 m->alias = "q35"; 374 } 375 376 DEFINE_Q35_MACHINE(v9_1, "pc-q35-9.1", NULL, 377 pc_q35_9_1_machine_options); 378 379 static void pc_q35_9_0_machine_options(MachineClass *m) 380 { 381 pc_q35_9_1_machine_options(m); 382 m->alias = NULL; 383 compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); 384 compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); 385 } 386 387 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, 388 pc_q35_9_0_machine_options); 389 390 static void pc_q35_8_2_machine_options(MachineClass *m) 391 { 392 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 393 pc_q35_9_0_machine_options(m); 394 m->max_cpus = 1024; 395 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 396 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 397 /* For pc-q35-8.2 and 8.1, use SMBIOS 3.X by default */ 398 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 399 } 400 401 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 402 pc_q35_8_2_machine_options); 403 404 static void pc_q35_8_1_machine_options(MachineClass *m) 405 { 406 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 407 pc_q35_8_2_machine_options(m); 408 pcmc->broken_32bit_mem_addr_check = true; 409 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 410 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 411 } 412 413 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 414 pc_q35_8_1_machine_options); 415 416 static void pc_q35_8_0_machine_options(MachineClass *m) 417 { 418 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 419 420 pc_q35_8_1_machine_options(m); 421 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 422 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 423 424 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 425 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 426 m->max_cpus = 288; 427 } 428 429 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 430 pc_q35_8_0_machine_options); 431 432 static void pc_q35_7_2_machine_options(MachineClass *m) 433 { 434 pc_q35_8_0_machine_options(m); 435 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 436 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 437 } 438 439 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 440 pc_q35_7_2_machine_options); 441 442 static void pc_q35_7_1_machine_options(MachineClass *m) 443 { 444 pc_q35_7_2_machine_options(m); 445 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 446 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 447 } 448 449 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 450 pc_q35_7_1_machine_options); 451 452 static void pc_q35_7_0_machine_options(MachineClass *m) 453 { 454 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 455 pc_q35_7_1_machine_options(m); 456 pcmc->enforce_amd_1tb_hole = false; 457 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 458 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 459 } 460 461 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 462 pc_q35_7_0_machine_options); 463 464 static void pc_q35_6_2_machine_options(MachineClass *m) 465 { 466 pc_q35_7_0_machine_options(m); 467 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 468 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 469 } 470 471 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 472 pc_q35_6_2_machine_options); 473 474 static void pc_q35_6_1_machine_options(MachineClass *m) 475 { 476 pc_q35_6_2_machine_options(m); 477 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 478 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 479 m->smp_props.prefer_sockets = true; 480 } 481 482 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 483 pc_q35_6_1_machine_options); 484 485 static void pc_q35_6_0_machine_options(MachineClass *m) 486 { 487 pc_q35_6_1_machine_options(m); 488 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 489 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 490 } 491 492 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 493 pc_q35_6_0_machine_options); 494 495 static void pc_q35_5_2_machine_options(MachineClass *m) 496 { 497 pc_q35_6_0_machine_options(m); 498 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 499 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 500 } 501 502 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 503 pc_q35_5_2_machine_options); 504 505 static void pc_q35_5_1_machine_options(MachineClass *m) 506 { 507 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 508 509 pc_q35_5_2_machine_options(m); 510 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 511 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 512 pcmc->kvmclock_create_always = false; 513 pcmc->pci_root_uid = 1; 514 } 515 516 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 517 pc_q35_5_1_machine_options); 518 519 static void pc_q35_5_0_machine_options(MachineClass *m) 520 { 521 pc_q35_5_1_machine_options(m); 522 m->numa_mem_supported = true; 523 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 524 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 525 m->auto_enable_numa_with_memdev = false; 526 } 527 528 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 529 pc_q35_5_0_machine_options); 530 531 static void pc_q35_4_2_machine_options(MachineClass *m) 532 { 533 pc_q35_5_0_machine_options(m); 534 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 535 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 536 } 537 538 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 539 pc_q35_4_2_machine_options); 540 541 static void pc_q35_4_1_machine_options(MachineClass *m) 542 { 543 pc_q35_4_2_machine_options(m); 544 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 545 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 546 } 547 548 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 549 pc_q35_4_1_machine_options); 550 551 static void pc_q35_4_0_1_machine_options(MachineClass *m) 552 { 553 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 554 pc_q35_4_1_machine_options(m); 555 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 556 /* 557 * This is the default machine for the 4.0-stable branch. It is basically 558 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 559 * 4.0 compat props. 560 */ 561 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 562 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 563 } 564 565 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 566 pc_q35_4_0_1_machine_options); 567 568 static void pc_q35_4_0_machine_options(MachineClass *m) 569 { 570 pc_q35_4_0_1_machine_options(m); 571 m->default_kernel_irqchip_split = true; 572 /* Compat props are applied by the 4.0.1 machine */ 573 } 574 575 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 576 pc_q35_4_0_machine_options); 577 578 static void pc_q35_3_1_machine_options(MachineClass *m) 579 { 580 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 581 582 pc_q35_4_0_machine_options(m); 583 m->default_kernel_irqchip_split = false; 584 m->smbus_no_migration_support = true; 585 pcmc->pvh_enabled = false; 586 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 587 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 588 } 589 590 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 591 pc_q35_3_1_machine_options); 592 593 static void pc_q35_3_0_machine_options(MachineClass *m) 594 { 595 pc_q35_3_1_machine_options(m); 596 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 597 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 598 } 599 600 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 601 pc_q35_3_0_machine_options); 602 603 static void pc_q35_2_12_machine_options(MachineClass *m) 604 { 605 pc_q35_3_0_machine_options(m); 606 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 607 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 608 } 609 610 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 611 pc_q35_2_12_machine_options); 612 613 static void pc_q35_2_11_machine_options(MachineClass *m) 614 { 615 pc_q35_2_12_machine_options(m); 616 m->default_nic = "e1000"; 617 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 618 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 619 } 620 621 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 622 pc_q35_2_11_machine_options); 623 624 static void pc_q35_2_10_machine_options(MachineClass *m) 625 { 626 pc_q35_2_11_machine_options(m); 627 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 628 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 629 m->auto_enable_numa_with_memhp = false; 630 } 631 632 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 633 pc_q35_2_10_machine_options); 634 635 static void pc_q35_2_9_machine_options(MachineClass *m) 636 { 637 pc_q35_2_10_machine_options(m); 638 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 639 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 640 } 641 642 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 643 pc_q35_2_9_machine_options); 644 645 static void pc_q35_2_8_machine_options(MachineClass *m) 646 { 647 pc_q35_2_9_machine_options(m); 648 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 649 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 650 } 651 652 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 653 pc_q35_2_8_machine_options); 654 655 static void pc_q35_2_7_machine_options(MachineClass *m) 656 { 657 pc_q35_2_8_machine_options(m); 658 m->max_cpus = 255; 659 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 660 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 661 } 662 663 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 664 pc_q35_2_7_machine_options); 665 666 static void pc_q35_2_6_machine_options(MachineClass *m) 667 { 668 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 669 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 670 671 pc_q35_2_7_machine_options(m); 672 pcmc->legacy_cpu_hotplug = true; 673 x86mc->fwcfg_dma_enabled = false; 674 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 675 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 676 } 677 678 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 679 pc_q35_2_6_machine_options); 680 681 static void pc_q35_2_5_machine_options(MachineClass *m) 682 { 683 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 684 685 pc_q35_2_6_machine_options(m); 686 x86mc->save_tsc_khz = false; 687 m->legacy_fw_cfg_order = 1; 688 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 689 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 690 } 691 692 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 693 pc_q35_2_5_machine_options); 694 695 static void pc_q35_2_4_machine_options(MachineClass *m) 696 { 697 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 698 699 pc_q35_2_5_machine_options(m); 700 m->hw_version = "2.4.0"; 701 pcmc->broken_reserved_end = true; 702 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 703 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 704 } 705 706 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 707 pc_q35_2_4_machine_options); 708