xref: /openbmc/qemu/hw/i386/pc_q35.c (revision c1774bdb)
1 /*
2  * Q35 chipset based pc system emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2009, 2010
6  *               Isaku Yamahata <yamahata at valinux co jp>
7  *               VA Linux Systems Japan K.K.
8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9  *
10  * This is based on pc.c, but heavily modified.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a copy
13  * of this software and associated documentation files (the "Software"), to deal
14  * in the Software without restriction, including without limitation the rights
15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16  * copies of the Software, and to permit persons to whom the Software is
17  * furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice shall be included in
20  * all copies or substantial portions of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28  * THE SOFTWARE.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "hw/char/parallel-isa.h"
34 #include "hw/loader.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/rtc/mc146818rtc.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/kvm.h"
39 #include "hw/i386/kvm/clock.h"
40 #include "hw/pci-host/q35.h"
41 #include "hw/pci/pcie_port.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/i386/x86.h"
44 #include "hw/i386/pc.h"
45 #include "hw/i386/amd_iommu.h"
46 #include "hw/i386/intel_iommu.h"
47 #include "hw/display/ramfb.h"
48 #include "hw/firmware/smbios.h"
49 #include "hw/ide/pci.h"
50 #include "hw/ide/ahci.h"
51 #include "hw/intc/ioapic.h"
52 #include "hw/southbridge/ich9.h"
53 #include "hw/usb.h"
54 #include "hw/usb/hcd-uhci.h"
55 #include "qapi/error.h"
56 #include "qemu/error-report.h"
57 #include "sysemu/numa.h"
58 #include "hw/hyperv/vmbus-bridge.h"
59 #include "hw/mem/nvdimm.h"
60 #include "hw/i386/acpi-build.h"
61 #include "target/i386/cpu.h"
62 
63 /* ICH9 AHCI has 6 ports */
64 #define MAX_SATA_PORTS     6
65 
66 struct ehci_companions {
67     const char *name;
68     int func;
69     int port;
70 };
71 
72 static const struct ehci_companions ich9_1d[] = {
73     { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
74     { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
75     { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
76 };
77 
78 static const struct ehci_companions ich9_1a[] = {
79     { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
80     { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
81     { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
82 };
83 
84 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
85 {
86     const struct ehci_companions *comp;
87     PCIDevice *ehci, *uhci;
88     BusState *usbbus;
89     const char *name;
90     int i;
91 
92     switch (slot) {
93     case 0x1d:
94         name = "ich9-usb-ehci1";
95         comp = ich9_1d;
96         break;
97     case 0x1a:
98         name = "ich9-usb-ehci2";
99         comp = ich9_1a;
100         break;
101     default:
102         return -1;
103     }
104 
105     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name);
106     pci_realize_and_unref(ehci, bus, &error_fatal);
107     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
108 
109     for (i = 0; i < 3; i++) {
110         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func),
111                                      comp[i].name);
112         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
113         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
114         pci_realize_and_unref(uhci, bus, &error_fatal);
115     }
116     return 0;
117 }
118 
119 /* PC hardware initialisation */
120 static void pc_q35_init(MachineState *machine)
121 {
122     PCMachineState *pcms = PC_MACHINE(machine);
123     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
124     X86MachineState *x86ms = X86_MACHINE(machine);
125     Object *phb;
126     PCIBus *host_bus;
127     PCIDevice *lpc;
128     DeviceState *lpc_dev;
129     BusState *idebus[MAX_SATA_PORTS];
130     ISADevice *rtc_state;
131     MemoryRegion *system_memory = get_system_memory();
132     MemoryRegion *system_io = get_system_io();
133     MemoryRegion *pci_memory;
134     MemoryRegion *rom_memory;
135     GSIState *gsi_state;
136     ISABus *isa_bus;
137     int i;
138     PCIDevice *ahci;
139     ram_addr_t lowmem;
140     DriveInfo *hd[MAX_SATA_PORTS];
141     MachineClass *mc = MACHINE_GET_CLASS(machine);
142     bool acpi_pcihp;
143     bool keep_pci_slot_hpc;
144     uint64_t pci_hole64_size = 0;
145 
146     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
147      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
148      * also known as MMCFG).
149      * If it doesn't, we need to split it in chunks below and above 4G.
150      * In any case, try to make sure that guest addresses aligned at
151      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
152      */
153     if (machine->ram_size >= 0xb0000000) {
154         lowmem = 0x80000000;
155     } else {
156         lowmem = 0xb0000000;
157     }
158 
159     /* Handle the machine opt max-ram-below-4g.  It is basically doing
160      * min(qemu limit, user limit).
161      */
162     if (!pcms->max_ram_below_4g) {
163         pcms->max_ram_below_4g = 4 * GiB;
164     }
165     if (lowmem > pcms->max_ram_below_4g) {
166         lowmem = pcms->max_ram_below_4g;
167         if (machine->ram_size - lowmem > lowmem &&
168             lowmem & (1 * GiB - 1)) {
169             warn_report("There is possibly poor performance as the ram size "
170                         " (0x%" PRIx64 ") is more then twice the size of"
171                         " max-ram-below-4g (%"PRIu64") and"
172                         " max-ram-below-4g is not a multiple of 1G.",
173                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
174         }
175     }
176 
177     if (machine->ram_size >= lowmem) {
178         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
179         x86ms->below_4g_mem_size = lowmem;
180     } else {
181         x86ms->above_4g_mem_size = 0;
182         x86ms->below_4g_mem_size = machine->ram_size;
183     }
184 
185     pc_machine_init_sgx_epc(pcms);
186     x86_cpus_init(x86ms, pcmc->default_cpu_version);
187 
188     if (kvm_enabled()) {
189         kvmclock_create(pcmc->kvmclock_create_always);
190     }
191 
192     /* pci enabled */
193     if (pcmc->pci_enabled) {
194         pci_memory = g_new(MemoryRegion, 1);
195         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
196         rom_memory = pci_memory;
197     } else {
198         pci_memory = NULL;
199         rom_memory = system_memory;
200     }
201 
202     pc_guest_info_init(pcms);
203 
204     if (pcmc->smbios_defaults) {
205         /* These values are guest ABI, do not change */
206         smbios_set_defaults("QEMU", mc->desc,
207                             mc->name, pcmc->smbios_legacy_mode,
208                             pcmc->smbios_uuid_encoded,
209                             pcms->smbios_entry_point_type);
210     }
211 
212     /* create pci host bus */
213     phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE));
214 
215     if (pcmc->pci_enabled) {
216         pci_hole64_size = object_property_get_uint(phb,
217                                                    PCI_HOST_PROP_PCI_HOLE64_SIZE,
218                                                    &error_abort);
219     }
220 
221     /* allocate ram and load rom/bios */
222     pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size);
223 
224     object_property_add_child(OBJECT(machine), "q35", phb);
225     object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
226                              OBJECT(machine->ram), NULL);
227     object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
228                              OBJECT(pci_memory), NULL);
229     object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
230                              OBJECT(system_memory), NULL);
231     object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
232                              OBJECT(system_io), NULL);
233     object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
234                             x86ms->below_4g_mem_size, NULL);
235     object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
236                             x86ms->above_4g_mem_size, NULL);
237     object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU,
238                              pcms->default_bus_bypass_iommu, NULL);
239     sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
240 
241     /* pci */
242     host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
243     pcms->bus = host_bus;
244 
245     /* create ISA bus */
246     lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
247                                 TYPE_ICH9_LPC_DEVICE);
248     qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
249                       x86_machine_is_smm_enabled(x86ms));
250     pci_realize_and_unref(lpc, host_bus, &error_fatal);
251 
252     rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
253 
254     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
255                              TYPE_HOTPLUG_HANDLER,
256                              (Object **)&x86ms->acpi_dev,
257                              object_property_allow_set_link,
258                              OBJ_PROP_LINK_STRONG);
259     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
260                              OBJECT(lpc), &error_abort);
261 
262     acpi_pcihp = object_property_get_bool(OBJECT(lpc),
263                                           ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
264                                           NULL);
265 
266     keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
267                                                  "x-keep-pci-slot-hpc",
268                                                  NULL);
269 
270     if (!keep_pci_slot_hpc && acpi_pcihp) {
271         object_register_sugar_prop(TYPE_PCIE_SLOT,
272                                    "x-do-not-expose-native-hotplug-cap",
273                                    "true", true);
274     }
275 
276     /* irq lines */
277     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
278 
279     lpc_dev = DEVICE(lpc);
280     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
281         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
282     }
283     isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
284 
285     if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
286         pc_i8259_create(isa_bus, gsi_state->i8259_irq);
287     }
288 
289     if (pcmc->pci_enabled) {
290         ioapic_init_gsi(gsi_state, "q35");
291     }
292 
293     if (tcg_enabled()) {
294         x86_register_ferr_irq(x86ms->gsi[13]);
295     }
296 
297     assert(pcms->vmport != ON_OFF_AUTO__MAX);
298     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
299         pcms->vmport = ON_OFF_AUTO_ON;
300     }
301 
302     /* init basic PC hardware */
303     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy,
304                          0xff0104);
305 
306     if (pcms->sata_enabled) {
307         /* ahci and SATA device, for q35 1 ahci controller is built-in */
308         ahci = pci_create_simple_multifunction(host_bus,
309                                                PCI_DEVFN(ICH9_SATA1_DEV,
310                                                          ICH9_SATA1_FUNC),
311                                                "ich9-ahci");
312         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
313         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
314         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
315         ide_drive_get(hd, ahci_get_num_ports(ahci));
316         ahci_ide_create_devs(ahci, hd);
317     } else {
318         idebus[0] = idebus[1] = NULL;
319     }
320 
321     if (machine_usb(machine)) {
322         /* Should we create 6 UHCI according to ich9 spec? */
323         ehci_create_ich9_with_companions(host_bus, 0x1d);
324     }
325 
326     if (pcms->smbus_enabled) {
327         PCIDevice *smb;
328 
329         /* TODO: Populate SPD eeprom data.  */
330         smb = pci_create_simple_multifunction(host_bus,
331                                               PCI_DEVFN(ICH9_SMB_DEV,
332                                                         ICH9_SMB_FUNC),
333                                               TYPE_ICH9_SMB_DEVICE);
334         pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
335 
336         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
337     }
338 
339     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
340 
341     /* the rest devices to which pci devfn is automatically assigned */
342     pc_vga_init(isa_bus, host_bus);
343     pc_nic_init(pcmc, isa_bus, host_bus);
344 
345     if (machine->nvdimms_state->is_enabled) {
346         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
347                                x86_nvdimm_acpi_dsmio,
348                                x86ms->fw_cfg, OBJECT(pcms));
349     }
350 }
351 
352 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
353     static void pc_init_##suffix(MachineState *machine) \
354     { \
355         void (*compat)(MachineState *m) = (compatfn); \
356         if (compat) { \
357             compat(machine); \
358         } \
359         pc_q35_init(machine); \
360     } \
361     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
362 
363 
364 static void pc_q35_machine_options(MachineClass *m)
365 {
366     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
367     pcmc->pci_root_uid = 0;
368     pcmc->default_cpu_version = 1;
369 
370     m->family = "pc_q35";
371     m->desc = "Standard PC (Q35 + ICH9, 2009)";
372     m->units_per_default_bus = 1;
373     m->default_machine_opts = "firmware=bios-256k.bin";
374     m->default_display = "std";
375     m->default_nic = "e1000e";
376     m->default_kernel_irqchip_split = false;
377     m->no_floppy = 1;
378     m->max_cpus = 1024;
379     m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
380     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
381     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
382     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
383     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
384 }
385 
386 static void pc_q35_8_2_machine_options(MachineClass *m)
387 {
388     pc_q35_machine_options(m);
389     m->alias = "q35";
390 }
391 
392 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL,
393                    pc_q35_8_2_machine_options);
394 
395 static void pc_q35_8_1_machine_options(MachineClass *m)
396 {
397     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
398     pc_q35_8_2_machine_options(m);
399     m->alias = NULL;
400     pcmc->broken_32bit_mem_addr_check = true;
401     compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len);
402     compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len);
403 }
404 
405 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL,
406                    pc_q35_8_1_machine_options);
407 
408 static void pc_q35_8_0_machine_options(MachineClass *m)
409 {
410     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
411 
412     pc_q35_8_1_machine_options(m);
413     compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len);
414     compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len);
415 
416     /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */
417     pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
418     m->max_cpus = 288;
419 }
420 
421 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
422                    pc_q35_8_0_machine_options);
423 
424 static void pc_q35_7_2_machine_options(MachineClass *m)
425 {
426     pc_q35_8_0_machine_options(m);
427     compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
428     compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
429 }
430 
431 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL,
432                    pc_q35_7_2_machine_options);
433 
434 static void pc_q35_7_1_machine_options(MachineClass *m)
435 {
436     pc_q35_7_2_machine_options(m);
437     compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
438     compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
439 }
440 
441 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
442                    pc_q35_7_1_machine_options);
443 
444 static void pc_q35_7_0_machine_options(MachineClass *m)
445 {
446     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
447     pc_q35_7_1_machine_options(m);
448     pcmc->enforce_amd_1tb_hole = false;
449     compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
450     compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
451 }
452 
453 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL,
454                    pc_q35_7_0_machine_options);
455 
456 static void pc_q35_6_2_machine_options(MachineClass *m)
457 {
458     pc_q35_7_0_machine_options(m);
459     compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
460     compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
461 }
462 
463 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
464                    pc_q35_6_2_machine_options);
465 
466 static void pc_q35_6_1_machine_options(MachineClass *m)
467 {
468     pc_q35_6_2_machine_options(m);
469     compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
470     compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
471     m->smp_props.prefer_sockets = true;
472 }
473 
474 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
475                    pc_q35_6_1_machine_options);
476 
477 static void pc_q35_6_0_machine_options(MachineClass *m)
478 {
479     pc_q35_6_1_machine_options(m);
480     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
481     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
482 }
483 
484 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
485                    pc_q35_6_0_machine_options);
486 
487 static void pc_q35_5_2_machine_options(MachineClass *m)
488 {
489     pc_q35_6_0_machine_options(m);
490     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
491     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
492 }
493 
494 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
495                    pc_q35_5_2_machine_options);
496 
497 static void pc_q35_5_1_machine_options(MachineClass *m)
498 {
499     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
500 
501     pc_q35_5_2_machine_options(m);
502     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
503     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
504     pcmc->kvmclock_create_always = false;
505     pcmc->pci_root_uid = 1;
506 }
507 
508 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
509                    pc_q35_5_1_machine_options);
510 
511 static void pc_q35_5_0_machine_options(MachineClass *m)
512 {
513     pc_q35_5_1_machine_options(m);
514     m->numa_mem_supported = true;
515     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
516     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
517     m->auto_enable_numa_with_memdev = false;
518 }
519 
520 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
521                    pc_q35_5_0_machine_options);
522 
523 static void pc_q35_4_2_machine_options(MachineClass *m)
524 {
525     pc_q35_5_0_machine_options(m);
526     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
527     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
528 }
529 
530 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
531                    pc_q35_4_2_machine_options);
532 
533 static void pc_q35_4_1_machine_options(MachineClass *m)
534 {
535     pc_q35_4_2_machine_options(m);
536     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
537     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
538 }
539 
540 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
541                    pc_q35_4_1_machine_options);
542 
543 static void pc_q35_4_0_1_machine_options(MachineClass *m)
544 {
545     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
546     pc_q35_4_1_machine_options(m);
547     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
548     /*
549      * This is the default machine for the 4.0-stable branch. It is basically
550      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
551      * 4.0 compat props.
552      */
553     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
554     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
555 }
556 
557 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
558                    pc_q35_4_0_1_machine_options);
559 
560 static void pc_q35_4_0_machine_options(MachineClass *m)
561 {
562     pc_q35_4_0_1_machine_options(m);
563     m->default_kernel_irqchip_split = true;
564     /* Compat props are applied by the 4.0.1 machine */
565 }
566 
567 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
568                    pc_q35_4_0_machine_options);
569 
570 static void pc_q35_3_1_machine_options(MachineClass *m)
571 {
572     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
573 
574     pc_q35_4_0_machine_options(m);
575     m->default_kernel_irqchip_split = false;
576     m->smbus_no_migration_support = true;
577     pcmc->pvh_enabled = false;
578     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
579     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
580 }
581 
582 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
583                    pc_q35_3_1_machine_options);
584 
585 static void pc_q35_3_0_machine_options(MachineClass *m)
586 {
587     pc_q35_3_1_machine_options(m);
588     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
589     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
590 }
591 
592 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
593                     pc_q35_3_0_machine_options);
594 
595 static void pc_q35_2_12_machine_options(MachineClass *m)
596 {
597     pc_q35_3_0_machine_options(m);
598     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
599     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
600 }
601 
602 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
603                    pc_q35_2_12_machine_options);
604 
605 static void pc_q35_2_11_machine_options(MachineClass *m)
606 {
607     pc_q35_2_12_machine_options(m);
608     m->default_nic = "e1000";
609     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
610     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
611 }
612 
613 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
614                    pc_q35_2_11_machine_options);
615 
616 static void pc_q35_2_10_machine_options(MachineClass *m)
617 {
618     pc_q35_2_11_machine_options(m);
619     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
620     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
621     m->auto_enable_numa_with_memhp = false;
622 }
623 
624 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
625                    pc_q35_2_10_machine_options);
626 
627 static void pc_q35_2_9_machine_options(MachineClass *m)
628 {
629     pc_q35_2_10_machine_options(m);
630     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
631     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
632 }
633 
634 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
635                    pc_q35_2_9_machine_options);
636 
637 static void pc_q35_2_8_machine_options(MachineClass *m)
638 {
639     pc_q35_2_9_machine_options(m);
640     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
641     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
642 }
643 
644 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
645                    pc_q35_2_8_machine_options);
646 
647 static void pc_q35_2_7_machine_options(MachineClass *m)
648 {
649     pc_q35_2_8_machine_options(m);
650     m->max_cpus = 255;
651     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
652     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
653 }
654 
655 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
656                    pc_q35_2_7_machine_options);
657 
658 static void pc_q35_2_6_machine_options(MachineClass *m)
659 {
660     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
661     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
662 
663     pc_q35_2_7_machine_options(m);
664     pcmc->legacy_cpu_hotplug = true;
665     x86mc->fwcfg_dma_enabled = false;
666     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
667     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
668 }
669 
670 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
671                    pc_q35_2_6_machine_options);
672 
673 static void pc_q35_2_5_machine_options(MachineClass *m)
674 {
675     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
676 
677     pc_q35_2_6_machine_options(m);
678     x86mc->save_tsc_khz = false;
679     m->legacy_fw_cfg_order = 1;
680     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
681     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
682 }
683 
684 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
685                    pc_q35_2_5_machine_options);
686 
687 static void pc_q35_2_4_machine_options(MachineClass *m)
688 {
689     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
690 
691     pc_q35_2_5_machine_options(m);
692     m->hw_version = "2.4.0";
693     pcmc->broken_reserved_end = true;
694     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
695     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
696 }
697 
698 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
699                    pc_q35_2_4_machine_options);
700