1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 48 /* ICH9 AHCI has 6 ports */ 49 #define MAX_SATA_PORTS 6 50 51 static bool has_pci_info; 52 static bool has_acpi_build = true; 53 static bool smbios_type1_defaults = true; 54 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 55 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 56 * pages in the host. 57 */ 58 static bool gigabyte_align = true; 59 60 /* PC hardware initialisation */ 61 static void pc_q35_init(QEMUMachineInitArgs *args) 62 { 63 ram_addr_t below_4g_mem_size, above_4g_mem_size; 64 Q35PCIHost *q35_host; 65 PCIHostState *phb; 66 PCIBus *host_bus; 67 PCIDevice *lpc; 68 BusState *idebus[MAX_SATA_PORTS]; 69 ISADevice *rtc_state; 70 ISADevice *floppy; 71 MemoryRegion *pci_memory; 72 MemoryRegion *rom_memory; 73 MemoryRegion *ram_memory; 74 GSIState *gsi_state; 75 ISABus *isa_bus; 76 int pci_enabled = 1; 77 qemu_irq *cpu_irq; 78 qemu_irq *gsi; 79 qemu_irq *i8259; 80 int i; 81 ICH9LPCState *ich9_lpc; 82 PCIDevice *ahci; 83 DeviceState *icc_bridge; 84 PcGuestInfo *guest_info; 85 86 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 87 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 88 exit(1); 89 } 90 91 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 92 object_property_add_child(qdev_get_machine(), "icc-bridge", 93 OBJECT(icc_bridge), NULL); 94 95 pc_cpus_init(args->cpu_model, icc_bridge); 96 pc_acpi_init("q35-acpi-dsdt.aml"); 97 98 kvmclock_create(); 99 100 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 101 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 102 * also known as MMCFG). 103 * If it doesn't, we need to split it in chunks below and above 4G. 104 * In any case, try to make sure that guest addresses aligned at 105 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 106 * For old machine types, use whatever split we used historically to avoid 107 * breaking migration. 108 */ 109 if (args->ram_size >= 0xb0000000) { 110 ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 111 above_4g_mem_size = args->ram_size - lowmem; 112 below_4g_mem_size = lowmem; 113 } else { 114 above_4g_mem_size = 0; 115 below_4g_mem_size = args->ram_size; 116 } 117 118 /* pci enabled */ 119 if (pci_enabled) { 120 pci_memory = g_new(MemoryRegion, 1); 121 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 122 rom_memory = pci_memory; 123 } else { 124 pci_memory = NULL; 125 rom_memory = get_system_memory(); 126 } 127 128 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 129 guest_info->has_pci_info = has_pci_info; 130 guest_info->isapc_ram_fw = false; 131 guest_info->has_acpi_build = has_acpi_build; 132 133 if (smbios_type1_defaults) { 134 /* These values are guest ABI, do not change */ 135 smbios_set_type1_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 136 args->machine->name); 137 } 138 139 /* allocate ram and load rom/bios */ 140 if (!xen_enabled()) { 141 pc_memory_init(get_system_memory(), 142 args->kernel_filename, args->kernel_cmdline, 143 args->initrd_filename, 144 below_4g_mem_size, above_4g_mem_size, 145 rom_memory, &ram_memory, guest_info); 146 } 147 148 /* irq lines */ 149 gsi_state = g_malloc0(sizeof(*gsi_state)); 150 if (kvm_irqchip_in_kernel()) { 151 kvm_pc_setup_irq_routing(pci_enabled); 152 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 153 GSI_NUM_PINS); 154 } else { 155 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 156 } 157 158 /* create pci host bus */ 159 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 160 161 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 162 q35_host->mch.ram_memory = ram_memory; 163 q35_host->mch.pci_address_space = pci_memory; 164 q35_host->mch.system_memory = get_system_memory(); 165 q35_host->mch.address_space_io = get_system_io(); 166 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 167 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 168 q35_host->mch.guest_info = guest_info; 169 /* pci */ 170 qdev_init_nofail(DEVICE(q35_host)); 171 phb = PCI_HOST_BRIDGE(q35_host); 172 host_bus = phb->bus; 173 /* create ISA bus */ 174 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 175 ICH9_LPC_FUNC), true, 176 TYPE_ICH9_LPC_DEVICE); 177 ich9_lpc = ICH9_LPC_DEVICE(lpc); 178 ich9_lpc->pic = gsi; 179 ich9_lpc->ioapic = gsi_state->ioapic_irq; 180 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 181 ICH9_LPC_NB_PIRQS); 182 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 183 isa_bus = ich9_lpc->isa_bus; 184 185 /*end early*/ 186 isa_bus_irqs(isa_bus, gsi); 187 188 if (kvm_irqchip_in_kernel()) { 189 i8259 = kvm_i8259_init(isa_bus); 190 } else if (xen_enabled()) { 191 i8259 = xen_interrupt_controller_init(); 192 } else { 193 cpu_irq = pc_allocate_cpu_irq(); 194 i8259 = i8259_init(isa_bus, cpu_irq[0]); 195 } 196 197 for (i = 0; i < ISA_NUM_IRQS; i++) { 198 gsi_state->i8259_irq[i] = i8259[i]; 199 } 200 if (pci_enabled) { 201 ioapic_init_gsi(gsi_state, NULL); 202 } 203 qdev_init_nofail(icc_bridge); 204 205 pc_register_ferr_irq(gsi[13]); 206 207 /* init basic PC hardware */ 208 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104); 209 210 /* connect pm stuff to lpc */ 211 ich9_lpc_pm_init(lpc); 212 213 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 214 ahci = pci_create_simple_multifunction(host_bus, 215 PCI_DEVFN(ICH9_SATA1_DEV, 216 ICH9_SATA1_FUNC), 217 true, "ich9-ahci"); 218 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 219 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 220 221 if (usb_enabled(false)) { 222 /* Should we create 6 UHCI according to ich9 spec? */ 223 ehci_create_ich9_with_companions(host_bus, 0x1d); 224 } 225 226 /* TODO: Populate SPD eeprom data. */ 227 smbus_eeprom_init(ich9_smb_init(host_bus, 228 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 229 0xb100), 230 8, NULL, 0); 231 232 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, 233 floppy, idebus[0], idebus[1], rtc_state); 234 235 /* the rest devices to which pci devfn is automatically assigned */ 236 pc_vga_init(isa_bus, host_bus); 237 pc_nic_init(isa_bus, host_bus); 238 if (pci_enabled) { 239 pc_pci_device_init(host_bus); 240 } 241 } 242 243 static void pc_compat_1_7(QEMUMachineInitArgs *args) 244 { 245 smbios_type1_defaults = false; 246 gigabyte_align = false; 247 option_rom_has_mr = true; 248 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); 249 } 250 251 static void pc_compat_1_6(QEMUMachineInitArgs *args) 252 { 253 pc_compat_1_7(args); 254 has_pci_info = false; 255 rom_file_has_mr = false; 256 has_acpi_build = false; 257 } 258 259 static void pc_compat_1_5(QEMUMachineInitArgs *args) 260 { 261 pc_compat_1_6(args); 262 } 263 264 static void pc_compat_1_4(QEMUMachineInitArgs *args) 265 { 266 pc_compat_1_5(args); 267 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 268 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 269 } 270 271 static void pc_q35_init_1_7(QEMUMachineInitArgs *args) 272 { 273 pc_compat_1_7(args); 274 pc_q35_init(args); 275 } 276 277 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 278 { 279 pc_compat_1_6(args); 280 pc_q35_init(args); 281 } 282 283 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 284 { 285 pc_compat_1_5(args); 286 pc_q35_init(args); 287 } 288 289 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 290 { 291 pc_compat_1_4(args); 292 pc_q35_init(args); 293 } 294 295 #define PC_Q35_MACHINE_OPTIONS \ 296 PC_DEFAULT_MACHINE_OPTIONS, \ 297 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 298 .hot_add_cpu = pc_hot_add_cpu 299 300 #define PC_Q35_2_0_MACHINE_OPTIONS \ 301 PC_Q35_MACHINE_OPTIONS, \ 302 .default_machine_opts = "firmware=bios-256k.bin" 303 304 static QEMUMachine pc_q35_machine_v2_0 = { 305 PC_Q35_2_0_MACHINE_OPTIONS, 306 .name = "pc-q35-2.0", 307 .alias = "q35", 308 .init = pc_q35_init, 309 }; 310 311 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 312 313 static QEMUMachine pc_q35_machine_v1_7 = { 314 PC_Q35_1_7_MACHINE_OPTIONS, 315 .name = "pc-q35-1.7", 316 .init = pc_q35_init_1_7, 317 .compat_props = (GlobalProperty[]) { 318 PC_Q35_COMPAT_1_7, 319 { /* end of list */ } 320 }, 321 }; 322 323 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 324 325 static QEMUMachine pc_q35_machine_v1_6 = { 326 PC_Q35_1_6_MACHINE_OPTIONS, 327 .name = "pc-q35-1.6", 328 .init = pc_q35_init_1_6, 329 .compat_props = (GlobalProperty[]) { 330 PC_Q35_COMPAT_1_6, 331 { /* end of list */ } 332 }, 333 }; 334 335 static QEMUMachine pc_q35_machine_v1_5 = { 336 PC_Q35_1_6_MACHINE_OPTIONS, 337 .name = "pc-q35-1.5", 338 .init = pc_q35_init_1_5, 339 .compat_props = (GlobalProperty[]) { 340 PC_Q35_COMPAT_1_5, 341 { /* end of list */ } 342 }, 343 }; 344 345 #define PC_Q35_1_4_MACHINE_OPTIONS \ 346 PC_Q35_1_6_MACHINE_OPTIONS, \ 347 .hot_add_cpu = NULL 348 349 static QEMUMachine pc_q35_machine_v1_4 = { 350 PC_Q35_1_4_MACHINE_OPTIONS, 351 .name = "pc-q35-1.4", 352 .init = pc_q35_init_1_4, 353 .compat_props = (GlobalProperty[]) { 354 PC_COMPAT_1_4, 355 { /* end of list */ } 356 }, 357 }; 358 359 static void pc_q35_machine_init(void) 360 { 361 qemu_register_machine(&pc_q35_machine_v2_0); 362 qemu_register_machine(&pc_q35_machine_v1_7); 363 qemu_register_machine(&pc_q35_machine_v1_6); 364 qemu_register_machine(&pc_q35_machine_v1_5); 365 qemu_register_machine(&pc_q35_machine_v1_4); 366 } 367 368 machine_init(pc_q35_machine_init); 369