1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "sysemu/arch_init.h" 32 #include "hw/i2c/smbus.h" 33 #include "hw/boards.h" 34 #include "hw/timer/mc146818rtc.h" 35 #include "hw/xen/xen.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "exec/address-spaces.h" 40 #include "hw/i386/ich9.h" 41 #include "hw/ide/pci.h" 42 #include "hw/ide/ahci.h" 43 #include "hw/usb.h" 44 #include "hw/cpu/icc_bus.h" 45 46 /* ICH9 AHCI has 6 ports */ 47 #define MAX_SATA_PORTS 6 48 49 static bool has_pvpanic; 50 static bool has_pci_info = true; 51 52 /* PC hardware initialisation */ 53 static void pc_q35_init(QEMUMachineInitArgs *args) 54 { 55 ram_addr_t ram_size = args->ram_size; 56 const char *cpu_model = args->cpu_model; 57 const char *kernel_filename = args->kernel_filename; 58 const char *kernel_cmdline = args->kernel_cmdline; 59 const char *initrd_filename = args->initrd_filename; 60 const char *boot_device = args->boot_device; 61 ram_addr_t below_4g_mem_size, above_4g_mem_size; 62 Q35PCIHost *q35_host; 63 PCIHostState *phb; 64 PCIBus *host_bus; 65 PCIDevice *lpc; 66 BusState *idebus[MAX_SATA_PORTS]; 67 ISADevice *rtc_state; 68 ISADevice *floppy; 69 MemoryRegion *pci_memory; 70 MemoryRegion *rom_memory; 71 MemoryRegion *ram_memory; 72 GSIState *gsi_state; 73 ISABus *isa_bus; 74 int pci_enabled = 1; 75 qemu_irq *cpu_irq; 76 qemu_irq *gsi; 77 qemu_irq *i8259; 78 int i; 79 ICH9LPCState *ich9_lpc; 80 PCIDevice *ahci; 81 DeviceState *icc_bridge; 82 PcGuestInfo *guest_info; 83 84 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 85 object_property_add_child(qdev_get_machine(), "icc-bridge", 86 OBJECT(icc_bridge), NULL); 87 88 pc_cpus_init(cpu_model, icc_bridge); 89 pc_acpi_init("q35-acpi-dsdt.aml"); 90 91 kvmclock_create(); 92 93 if (ram_size >= 0xb0000000) { 94 above_4g_mem_size = ram_size - 0xb0000000; 95 below_4g_mem_size = 0xb0000000; 96 } else { 97 above_4g_mem_size = 0; 98 below_4g_mem_size = ram_size; 99 } 100 101 /* pci enabled */ 102 if (pci_enabled) { 103 pci_memory = g_new(MemoryRegion, 1); 104 memory_region_init(pci_memory, NULL, "pci", INT64_MAX); 105 rom_memory = pci_memory; 106 } else { 107 pci_memory = NULL; 108 rom_memory = get_system_memory(); 109 } 110 111 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 112 guest_info->has_pci_info = has_pci_info; 113 guest_info->isapc_ram_fw = false; 114 115 /* allocate ram and load rom/bios */ 116 if (!xen_enabled()) { 117 pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, 118 initrd_filename, below_4g_mem_size, above_4g_mem_size, 119 rom_memory, &ram_memory, guest_info); 120 } 121 122 /* irq lines */ 123 gsi_state = g_malloc0(sizeof(*gsi_state)); 124 if (kvm_irqchip_in_kernel()) { 125 kvm_pc_setup_irq_routing(pci_enabled); 126 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 127 GSI_NUM_PINS); 128 } else { 129 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 130 } 131 132 /* create pci host bus */ 133 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 134 135 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 136 q35_host->mch.ram_memory = ram_memory; 137 q35_host->mch.pci_address_space = pci_memory; 138 q35_host->mch.system_memory = get_system_memory(); 139 q35_host->mch.address_space_io = get_system_io(); 140 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 141 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 142 q35_host->mch.guest_info = guest_info; 143 /* pci */ 144 qdev_init_nofail(DEVICE(q35_host)); 145 phb = PCI_HOST_BRIDGE(q35_host); 146 host_bus = phb->bus; 147 /* create ISA bus */ 148 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 149 ICH9_LPC_FUNC), true, 150 TYPE_ICH9_LPC_DEVICE); 151 ich9_lpc = ICH9_LPC_DEVICE(lpc); 152 ich9_lpc->pic = gsi; 153 ich9_lpc->ioapic = gsi_state->ioapic_irq; 154 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 155 ICH9_LPC_NB_PIRQS); 156 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 157 isa_bus = ich9_lpc->isa_bus; 158 159 /*end early*/ 160 isa_bus_irqs(isa_bus, gsi); 161 162 if (kvm_irqchip_in_kernel()) { 163 i8259 = kvm_i8259_init(isa_bus); 164 } else if (xen_enabled()) { 165 i8259 = xen_interrupt_controller_init(); 166 } else { 167 cpu_irq = pc_allocate_cpu_irq(); 168 i8259 = i8259_init(isa_bus, cpu_irq[0]); 169 } 170 171 for (i = 0; i < ISA_NUM_IRQS; i++) { 172 gsi_state->i8259_irq[i] = i8259[i]; 173 } 174 if (pci_enabled) { 175 ioapic_init_gsi(gsi_state, NULL); 176 } 177 qdev_init_nofail(icc_bridge); 178 179 pc_register_ferr_irq(gsi[13]); 180 181 /* init basic PC hardware */ 182 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 183 184 /* connect pm stuff to lpc */ 185 ich9_lpc_pm_init(lpc); 186 187 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 188 ahci = pci_create_simple_multifunction(host_bus, 189 PCI_DEVFN(ICH9_SATA1_DEV, 190 ICH9_SATA1_FUNC), 191 true, "ich9-ahci"); 192 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 193 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 194 195 if (usb_enabled(false)) { 196 /* Should we create 6 UHCI according to ich9 spec? */ 197 ehci_create_ich9_with_companions(host_bus, 0x1d); 198 } 199 200 /* TODO: Populate SPD eeprom data. */ 201 smbus_eeprom_init(ich9_smb_init(host_bus, 202 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 203 0xb100), 204 8, NULL, 0); 205 206 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, 207 floppy, idebus[0], idebus[1], rtc_state); 208 209 /* the rest devices to which pci devfn is automatically assigned */ 210 pc_vga_init(isa_bus, host_bus); 211 pc_nic_init(isa_bus, host_bus); 212 if (pci_enabled) { 213 pc_pci_device_init(host_bus); 214 } 215 216 if (has_pvpanic) { 217 pvpanic_init(isa_bus); 218 } 219 } 220 221 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 222 { 223 has_pci_info = false; 224 pc_q35_init(args); 225 } 226 227 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 228 { 229 has_pvpanic = true; 230 pc_q35_init_1_6(args); 231 } 232 233 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 234 { 235 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 236 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 237 has_pci_info = false; 238 pc_q35_init(args); 239 } 240 241 static QEMUMachine pc_q35_machine_v1_6 = { 242 .name = "pc-q35-1.6", 243 .alias = "q35", 244 .desc = "Standard PC (Q35 + ICH9, 2009)", 245 .init = pc_q35_init_1_6, 246 .hot_add_cpu = pc_hot_add_cpu, 247 .max_cpus = 255, 248 DEFAULT_MACHINE_OPTIONS, 249 }; 250 251 static QEMUMachine pc_q35_machine_v1_5 = { 252 .name = "pc-q35-1.5", 253 .desc = "Standard PC (Q35 + ICH9, 2009)", 254 .init = pc_q35_init_1_5, 255 .hot_add_cpu = pc_hot_add_cpu, 256 .max_cpus = 255, 257 .compat_props = (GlobalProperty[]) { 258 PC_COMPAT_1_5, 259 { /* end of list */ } 260 }, 261 DEFAULT_MACHINE_OPTIONS, 262 }; 263 264 static QEMUMachine pc_q35_machine_v1_4 = { 265 .name = "pc-q35-1.4", 266 .desc = "Standard PC (Q35 + ICH9, 2009)", 267 .init = pc_q35_init_1_4, 268 .max_cpus = 255, 269 .compat_props = (GlobalProperty[]) { 270 PC_COMPAT_1_4, 271 { /* end of list */ } 272 }, 273 DEFAULT_MACHINE_OPTIONS, 274 }; 275 276 static void pc_q35_machine_init(void) 277 { 278 qemu_register_machine(&pc_q35_machine_v1_6); 279 qemu_register_machine(&pc_q35_machine_v1_5); 280 qemu_register_machine(&pc_q35_machine_v1_4); 281 } 282 283 machine_init(pc_q35_machine_init); 284