1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "sysemu/arch_init.h" 32 #include "hw/i2c/smbus.h" 33 #include "hw/boards.h" 34 #include "hw/timer/mc146818rtc.h" 35 #include "hw/xen/xen.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "exec/address-spaces.h" 40 #include "hw/i386/ich9.h" 41 #include "hw/ide/pci.h" 42 #include "hw/ide/ahci.h" 43 #include "hw/usb.h" 44 45 /* ICH9 AHCI has 6 ports */ 46 #define MAX_SATA_PORTS 6 47 48 static bool has_pvpanic = true; 49 50 /* PC hardware initialisation */ 51 static void pc_q35_init(QEMUMachineInitArgs *args) 52 { 53 ram_addr_t ram_size = args->ram_size; 54 const char *cpu_model = args->cpu_model; 55 const char *kernel_filename = args->kernel_filename; 56 const char *kernel_cmdline = args->kernel_cmdline; 57 const char *initrd_filename = args->initrd_filename; 58 const char *boot_device = args->boot_device; 59 ram_addr_t below_4g_mem_size, above_4g_mem_size; 60 Q35PCIHost *q35_host; 61 PCIBus *host_bus; 62 PCIDevice *lpc; 63 BusState *idebus[MAX_SATA_PORTS]; 64 ISADevice *rtc_state; 65 ISADevice *floppy; 66 MemoryRegion *pci_memory; 67 MemoryRegion *rom_memory; 68 MemoryRegion *ram_memory; 69 GSIState *gsi_state; 70 ISABus *isa_bus; 71 int pci_enabled = 1; 72 qemu_irq *cpu_irq; 73 qemu_irq *gsi; 74 qemu_irq *i8259; 75 int i; 76 ICH9LPCState *ich9_lpc; 77 PCIDevice *ahci; 78 79 pc_cpus_init(cpu_model); 80 pc_acpi_init("q35-acpi-dsdt.aml"); 81 82 kvmclock_create(); 83 84 if (ram_size >= 0xb0000000) { 85 above_4g_mem_size = ram_size - 0xb0000000; 86 below_4g_mem_size = 0xb0000000; 87 } else { 88 above_4g_mem_size = 0; 89 below_4g_mem_size = ram_size; 90 } 91 92 /* pci enabled */ 93 if (pci_enabled) { 94 pci_memory = g_new(MemoryRegion, 1); 95 memory_region_init(pci_memory, "pci", INT64_MAX); 96 rom_memory = pci_memory; 97 } else { 98 pci_memory = NULL; 99 rom_memory = get_system_memory(); 100 } 101 102 /* allocate ram and load rom/bios */ 103 if (!xen_enabled()) { 104 pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, 105 initrd_filename, below_4g_mem_size, above_4g_mem_size, 106 rom_memory, &ram_memory); 107 } 108 109 /* irq lines */ 110 gsi_state = g_malloc0(sizeof(*gsi_state)); 111 if (kvm_irqchip_in_kernel()) { 112 kvm_pc_setup_irq_routing(pci_enabled); 113 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 114 GSI_NUM_PINS); 115 } else { 116 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 117 } 118 119 /* create pci host bus */ 120 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 121 122 q35_host->mch.ram_memory = ram_memory; 123 q35_host->mch.pci_address_space = pci_memory; 124 q35_host->mch.system_memory = get_system_memory(); 125 q35_host->mch.address_space_io = get_system_io();; 126 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 127 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 128 /* pci */ 129 qdev_init_nofail(DEVICE(q35_host)); 130 host_bus = q35_host->host.pci.bus; 131 /* create ISA bus */ 132 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 133 ICH9_LPC_FUNC), true, 134 TYPE_ICH9_LPC_DEVICE); 135 ich9_lpc = ICH9_LPC_DEVICE(lpc); 136 ich9_lpc->pic = gsi; 137 ich9_lpc->ioapic = gsi_state->ioapic_irq; 138 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 139 ICH9_LPC_NB_PIRQS); 140 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 141 isa_bus = ich9_lpc->isa_bus; 142 143 /*end early*/ 144 isa_bus_irqs(isa_bus, gsi); 145 146 if (kvm_irqchip_in_kernel()) { 147 i8259 = kvm_i8259_init(isa_bus); 148 } else if (xen_enabled()) { 149 i8259 = xen_interrupt_controller_init(); 150 } else { 151 cpu_irq = pc_allocate_cpu_irq(); 152 i8259 = i8259_init(isa_bus, cpu_irq[0]); 153 } 154 155 for (i = 0; i < ISA_NUM_IRQS; i++) { 156 gsi_state->i8259_irq[i] = i8259[i]; 157 } 158 if (pci_enabled) { 159 ioapic_init_gsi(gsi_state, NULL); 160 } 161 162 pc_register_ferr_irq(gsi[13]); 163 164 /* init basic PC hardware */ 165 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 166 167 /* connect pm stuff to lpc */ 168 ich9_lpc_pm_init(lpc); 169 170 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 171 ahci = pci_create_simple_multifunction(host_bus, 172 PCI_DEVFN(ICH9_SATA1_DEV, 173 ICH9_SATA1_FUNC), 174 true, "ich9-ahci"); 175 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 176 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 177 178 if (usb_enabled(false)) { 179 /* Should we create 6 UHCI according to ich9 spec? */ 180 ehci_create_ich9_with_companions(host_bus, 0x1d); 181 } 182 183 /* TODO: Populate SPD eeprom data. */ 184 smbus_eeprom_init(ich9_smb_init(host_bus, 185 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 186 0xb100), 187 8, NULL, 0); 188 189 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, 190 floppy, idebus[0], idebus[1], rtc_state); 191 192 /* the rest devices to which pci devfn is automatically assigned */ 193 pc_vga_init(isa_bus, host_bus); 194 pc_nic_init(isa_bus, host_bus); 195 if (pci_enabled) { 196 pc_pci_device_init(host_bus); 197 } 198 199 if (has_pvpanic) { 200 pvpanic_init(isa_bus); 201 } 202 } 203 204 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 205 { 206 pc_sysfw_flash_vs_rom_bug_compatible = true; 207 has_pvpanic = false; 208 pc_q35_init(args); 209 } 210 211 static QEMUMachine pc_q35_machine_v1_5 = { 212 .name = "pc-q35-1.5", 213 .alias = "q35", 214 .desc = "Standard PC (Q35 + ICH9, 2009)", 215 .init = pc_q35_init, 216 .max_cpus = 255, 217 DEFAULT_MACHINE_OPTIONS, 218 }; 219 220 static QEMUMachine pc_q35_machine_v1_4 = { 221 .name = "pc-q35-1.4", 222 .desc = "Standard PC (Q35 + ICH9, 2009)", 223 .init = pc_q35_init_1_4, 224 .max_cpus = 255, 225 .compat_props = (GlobalProperty[]) { 226 PC_COMPAT_1_4, 227 { /* end of list */ } 228 }, 229 DEFAULT_MACHINE_OPTIONS, 230 }; 231 232 static void pc_q35_machine_init(void) 233 { 234 qemu_register_machine(&pc_q35_machine_v1_5); 235 qemu_register_machine(&pc_q35_machine_v1_4); 236 } 237 238 machine_init(pc_q35_machine_init); 239