1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "hw/xen/xen.h" 38 #include "sysemu/kvm.h" 39 #include "hw/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "hw/qdev-properties.h" 42 #include "exec/address-spaces.h" 43 #include "hw/i386/x86.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/ich9.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/display/ramfb.h" 49 #include "hw/firmware/smbios.h" 50 #include "hw/ide/pci.h" 51 #include "hw/ide/ahci.h" 52 #include "hw/usb.h" 53 #include "qapi/error.h" 54 #include "qemu/error-report.h" 55 #include "sysemu/numa.h" 56 #include "hw/hyperv/vmbus-bridge.h" 57 #include "hw/mem/nvdimm.h" 58 #include "hw/i386/acpi-build.h" 59 60 /* ICH9 AHCI has 6 ports */ 61 #define MAX_SATA_PORTS 6 62 63 struct ehci_companions { 64 const char *name; 65 int func; 66 int port; 67 }; 68 69 static const struct ehci_companions ich9_1d[] = { 70 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 71 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 72 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 73 }; 74 75 static const struct ehci_companions ich9_1a[] = { 76 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 77 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 78 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 79 }; 80 81 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 82 { 83 const struct ehci_companions *comp; 84 PCIDevice *ehci, *uhci; 85 BusState *usbbus; 86 const char *name; 87 int i; 88 89 switch (slot) { 90 case 0x1d: 91 name = "ich9-usb-ehci1"; 92 comp = ich9_1d; 93 break; 94 case 0x1a: 95 name = "ich9-usb-ehci2"; 96 comp = ich9_1a; 97 break; 98 default: 99 return -1; 100 } 101 102 ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); 103 qdev_init_nofail(&ehci->qdev); 104 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 105 106 for (i = 0; i < 3; i++) { 107 uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), 108 true, comp[i].name); 109 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 110 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 111 qdev_init_nofail(&uhci->qdev); 112 } 113 return 0; 114 } 115 116 /* PC hardware initialisation */ 117 static void pc_q35_init(MachineState *machine) 118 { 119 PCMachineState *pcms = PC_MACHINE(machine); 120 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 121 X86MachineState *x86ms = X86_MACHINE(machine); 122 Q35PCIHost *q35_host; 123 PCIHostState *phb; 124 PCIBus *host_bus; 125 PCIDevice *lpc; 126 DeviceState *lpc_dev; 127 BusState *idebus[MAX_SATA_PORTS]; 128 ISADevice *rtc_state; 129 MemoryRegion *system_io = get_system_io(); 130 MemoryRegion *pci_memory; 131 MemoryRegion *rom_memory; 132 MemoryRegion *ram_memory; 133 GSIState *gsi_state; 134 ISABus *isa_bus; 135 int i; 136 ICH9LPCState *ich9_lpc; 137 PCIDevice *ahci; 138 ram_addr_t lowmem; 139 DriveInfo *hd[MAX_SATA_PORTS]; 140 MachineClass *mc = MACHINE_GET_CLASS(machine); 141 142 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 143 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 144 * also known as MMCFG). 145 * If it doesn't, we need to split it in chunks below and above 4G. 146 * In any case, try to make sure that guest addresses aligned at 147 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 148 */ 149 if (machine->ram_size >= 0xb0000000) { 150 lowmem = 0x80000000; 151 } else { 152 lowmem = 0xb0000000; 153 } 154 155 /* Handle the machine opt max-ram-below-4g. It is basically doing 156 * min(qemu limit, user limit). 157 */ 158 if (!x86ms->max_ram_below_4g) { 159 x86ms->max_ram_below_4g = 4 * GiB; 160 } 161 if (lowmem > x86ms->max_ram_below_4g) { 162 lowmem = x86ms->max_ram_below_4g; 163 if (machine->ram_size - lowmem > lowmem && 164 lowmem & (1 * GiB - 1)) { 165 warn_report("There is possibly poor performance as the ram size " 166 " (0x%" PRIx64 ") is more then twice the size of" 167 " max-ram-below-4g (%"PRIu64") and" 168 " max-ram-below-4g is not a multiple of 1G.", 169 (uint64_t)machine->ram_size, x86ms->max_ram_below_4g); 170 } 171 } 172 173 if (machine->ram_size >= lowmem) { 174 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 175 x86ms->below_4g_mem_size = lowmem; 176 } else { 177 x86ms->above_4g_mem_size = 0; 178 x86ms->below_4g_mem_size = machine->ram_size; 179 } 180 181 if (xen_enabled()) { 182 xen_hvm_init(pcms, &ram_memory); 183 } 184 185 x86_cpus_init(x86ms, pcmc->default_cpu_version); 186 187 kvmclock_create(); 188 189 /* pci enabled */ 190 if (pcmc->pci_enabled) { 191 pci_memory = g_new(MemoryRegion, 1); 192 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 193 rom_memory = pci_memory; 194 } else { 195 pci_memory = NULL; 196 rom_memory = get_system_memory(); 197 } 198 199 pc_guest_info_init(pcms); 200 201 if (pcmc->smbios_defaults) { 202 /* These values are guest ABI, do not change */ 203 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 204 mc->name, pcmc->smbios_legacy_mode, 205 pcmc->smbios_uuid_encoded, 206 SMBIOS_ENTRY_POINT_21); 207 } 208 209 /* allocate ram and load rom/bios */ 210 if (!xen_enabled()) { 211 pc_memory_init(pcms, get_system_memory(), 212 rom_memory, &ram_memory); 213 } 214 215 /* create pci host bus */ 216 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 217 218 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 219 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 220 MCH_HOST_PROP_RAM_MEM, NULL); 221 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 222 MCH_HOST_PROP_PCI_MEM, NULL); 223 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 224 MCH_HOST_PROP_SYSTEM_MEM, NULL); 225 object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 226 MCH_HOST_PROP_IO_MEM, NULL); 227 object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size, 228 PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 229 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size, 230 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 231 /* pci */ 232 qdev_init_nofail(DEVICE(q35_host)); 233 phb = PCI_HOST_BRIDGE(q35_host); 234 host_bus = phb->bus; 235 /* create ISA bus */ 236 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 237 ICH9_LPC_FUNC), true, 238 TYPE_ICH9_LPC_DEVICE); 239 240 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 241 TYPE_HOTPLUG_HANDLER, 242 (Object **)&pcms->acpi_dev, 243 object_property_allow_set_link, 244 OBJ_PROP_LINK_STRONG); 245 object_property_set_link(OBJECT(machine), OBJECT(lpc), 246 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 247 248 /* irq lines */ 249 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 250 251 ich9_lpc = ICH9_LPC_DEVICE(lpc); 252 lpc_dev = DEVICE(lpc); 253 for (i = 0; i < GSI_NUM_PINS; i++) { 254 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 255 } 256 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 257 ICH9_LPC_NB_PIRQS); 258 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 259 isa_bus = ich9_lpc->isa_bus; 260 261 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 262 263 if (pcmc->pci_enabled) { 264 ioapic_init_gsi(gsi_state, "q35"); 265 } 266 267 if (tcg_enabled()) { 268 x86_register_ferr_irq(x86ms->gsi[13]); 269 } 270 271 assert(pcms->vmport != ON_OFF_AUTO__MAX); 272 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 273 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 274 } 275 276 /* init basic PC hardware */ 277 pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 278 (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled, 279 0xff0104); 280 281 /* connect pm stuff to lpc */ 282 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 283 284 if (pcms->sata_enabled) { 285 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 286 ahci = pci_create_simple_multifunction(host_bus, 287 PCI_DEVFN(ICH9_SATA1_DEV, 288 ICH9_SATA1_FUNC), 289 true, "ich9-ahci"); 290 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 291 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 292 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 293 ide_drive_get(hd, ahci_get_num_ports(ahci)); 294 ahci_ide_create_devs(ahci, hd); 295 } else { 296 idebus[0] = idebus[1] = NULL; 297 } 298 299 if (machine_usb(machine)) { 300 /* Should we create 6 UHCI according to ich9 spec? */ 301 ehci_create_ich9_with_companions(host_bus, 0x1d); 302 } 303 304 if (pcms->smbus_enabled) { 305 /* TODO: Populate SPD eeprom data. */ 306 pcms->smbus = ich9_smb_init(host_bus, 307 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 308 0xb100); 309 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 310 } 311 312 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 313 314 /* the rest devices to which pci devfn is automatically assigned */ 315 pc_vga_init(isa_bus, host_bus); 316 pc_nic_init(pcmc, isa_bus, host_bus); 317 318 if (machine->nvdimms_state->is_enabled) { 319 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 320 x86_nvdimm_acpi_dsmio, 321 x86ms->fw_cfg, OBJECT(pcms)); 322 } 323 } 324 325 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 326 static void pc_init_##suffix(MachineState *machine) \ 327 { \ 328 void (*compat)(MachineState *m) = (compatfn); \ 329 if (compat) { \ 330 compat(machine); \ 331 } \ 332 pc_q35_init(machine); \ 333 } \ 334 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 335 336 337 static void pc_q35_machine_options(MachineClass *m) 338 { 339 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 340 pcmc->default_nic_model = "e1000e"; 341 342 m->family = "pc_q35"; 343 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 344 m->units_per_default_bus = 1; 345 m->default_machine_opts = "firmware=bios-256k.bin"; 346 m->default_display = "std"; 347 m->default_kernel_irqchip_split = false; 348 m->no_floppy = 1; 349 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 350 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 351 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 352 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 353 m->max_cpus = 288; 354 } 355 356 static void pc_q35_5_1_machine_options(MachineClass *m) 357 { 358 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 359 pc_q35_machine_options(m); 360 m->alias = "q35"; 361 pcmc->default_cpu_version = 1; 362 } 363 364 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 365 pc_q35_5_1_machine_options); 366 367 static void pc_q35_5_0_machine_options(MachineClass *m) 368 { 369 pc_q35_5_1_machine_options(m); 370 m->alias = NULL; 371 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 372 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 373 } 374 375 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 376 pc_q35_5_0_machine_options); 377 378 static void pc_q35_4_2_machine_options(MachineClass *m) 379 { 380 pc_q35_5_0_machine_options(m); 381 m->alias = NULL; 382 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 383 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 384 } 385 386 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 387 pc_q35_4_2_machine_options); 388 389 static void pc_q35_4_1_machine_options(MachineClass *m) 390 { 391 pc_q35_4_2_machine_options(m); 392 m->alias = NULL; 393 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 394 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 395 } 396 397 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 398 pc_q35_4_1_machine_options); 399 400 static void pc_q35_4_0_1_machine_options(MachineClass *m) 401 { 402 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 403 pc_q35_4_1_machine_options(m); 404 m->alias = NULL; 405 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 406 /* 407 * This is the default machine for the 4.0-stable branch. It is basically 408 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 409 * 4.0 compat props. 410 */ 411 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 412 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 413 } 414 415 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 416 pc_q35_4_0_1_machine_options); 417 418 static void pc_q35_4_0_machine_options(MachineClass *m) 419 { 420 pc_q35_4_0_1_machine_options(m); 421 m->default_kernel_irqchip_split = true; 422 m->alias = NULL; 423 /* Compat props are applied by the 4.0.1 machine */ 424 } 425 426 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 427 pc_q35_4_0_machine_options); 428 429 static void pc_q35_3_1_machine_options(MachineClass *m) 430 { 431 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 432 433 pc_q35_4_0_machine_options(m); 434 m->default_kernel_irqchip_split = false; 435 pcmc->do_not_add_smb_acpi = true; 436 m->smbus_no_migration_support = true; 437 m->alias = NULL; 438 pcmc->pvh_enabled = false; 439 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 440 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 441 } 442 443 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 444 pc_q35_3_1_machine_options); 445 446 static void pc_q35_3_0_machine_options(MachineClass *m) 447 { 448 pc_q35_3_1_machine_options(m); 449 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 450 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 451 } 452 453 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 454 pc_q35_3_0_machine_options); 455 456 static void pc_q35_2_12_machine_options(MachineClass *m) 457 { 458 pc_q35_3_0_machine_options(m); 459 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 460 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 461 } 462 463 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 464 pc_q35_2_12_machine_options); 465 466 static void pc_q35_2_11_machine_options(MachineClass *m) 467 { 468 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 469 470 pc_q35_2_12_machine_options(m); 471 pcmc->default_nic_model = "e1000"; 472 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 473 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 474 } 475 476 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 477 pc_q35_2_11_machine_options); 478 479 static void pc_q35_2_10_machine_options(MachineClass *m) 480 { 481 pc_q35_2_11_machine_options(m); 482 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 483 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 484 m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 485 m->auto_enable_numa_with_memhp = false; 486 } 487 488 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 489 pc_q35_2_10_machine_options); 490 491 static void pc_q35_2_9_machine_options(MachineClass *m) 492 { 493 pc_q35_2_10_machine_options(m); 494 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 495 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 496 } 497 498 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 499 pc_q35_2_9_machine_options); 500 501 static void pc_q35_2_8_machine_options(MachineClass *m) 502 { 503 pc_q35_2_9_machine_options(m); 504 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 505 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 506 } 507 508 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 509 pc_q35_2_8_machine_options); 510 511 static void pc_q35_2_7_machine_options(MachineClass *m) 512 { 513 pc_q35_2_8_machine_options(m); 514 m->max_cpus = 255; 515 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 516 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 517 } 518 519 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 520 pc_q35_2_7_machine_options); 521 522 static void pc_q35_2_6_machine_options(MachineClass *m) 523 { 524 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 525 526 pc_q35_2_7_machine_options(m); 527 pcmc->legacy_cpu_hotplug = true; 528 pcmc->linuxboot_dma_enabled = false; 529 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 530 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 531 } 532 533 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 534 pc_q35_2_6_machine_options); 535 536 static void pc_q35_2_5_machine_options(MachineClass *m) 537 { 538 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 539 540 pc_q35_2_6_machine_options(m); 541 x86mc->save_tsc_khz = false; 542 m->legacy_fw_cfg_order = 1; 543 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 544 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 545 } 546 547 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 548 pc_q35_2_5_machine_options); 549 550 static void pc_q35_2_4_machine_options(MachineClass *m) 551 { 552 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 553 554 pc_q35_2_5_machine_options(m); 555 m->hw_version = "2.4.0"; 556 pcmc->broken_reserved_end = true; 557 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 558 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 559 } 560 561 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 562 pc_q35_2_4_machine_options); 563