1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 #include "qemu/error-report.h" 48 49 /* ICH9 AHCI has 6 ports */ 50 #define MAX_SATA_PORTS 6 51 52 static bool has_acpi_build = true; 53 static bool rsdp_in_ram = true; 54 static bool smbios_defaults = true; 55 static bool smbios_legacy_mode; 56 static bool smbios_uuid_encoded = true; 57 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 58 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 59 * pages in the host. 60 */ 61 static bool gigabyte_align = true; 62 static bool has_reserved_memory = true; 63 64 /* PC hardware initialisation */ 65 static void pc_q35_init(MachineState *machine) 66 { 67 PCMachineState *pc_machine = PC_MACHINE(machine); 68 ram_addr_t below_4g_mem_size, above_4g_mem_size; 69 Q35PCIHost *q35_host; 70 PCIHostState *phb; 71 PCIBus *host_bus; 72 PCIDevice *lpc; 73 BusState *idebus[MAX_SATA_PORTS]; 74 ISADevice *rtc_state; 75 ISADevice *floppy; 76 MemoryRegion *pci_memory; 77 MemoryRegion *rom_memory; 78 MemoryRegion *ram_memory; 79 GSIState *gsi_state; 80 ISABus *isa_bus; 81 int pci_enabled = 1; 82 qemu_irq *cpu_irq; 83 qemu_irq *gsi; 84 qemu_irq *i8259; 85 int i; 86 ICH9LPCState *ich9_lpc; 87 PCIDevice *ahci; 88 DeviceState *icc_bridge; 89 PcGuestInfo *guest_info; 90 ram_addr_t lowmem; 91 DriveInfo *hd[MAX_SATA_PORTS]; 92 93 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 94 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 95 * also known as MMCFG). 96 * If it doesn't, we need to split it in chunks below and above 4G. 97 * In any case, try to make sure that guest addresses aligned at 98 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 99 * For old machine types, use whatever split we used historically to avoid 100 * breaking migration. 101 */ 102 if (machine->ram_size >= 0xb0000000) { 103 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 104 } else { 105 lowmem = 0xb0000000; 106 } 107 108 /* Handle the machine opt max-ram-below-4g. It is basically doing 109 * min(qemu limit, user limit). 110 */ 111 if (lowmem > pc_machine->max_ram_below_4g) { 112 lowmem = pc_machine->max_ram_below_4g; 113 if (machine->ram_size - lowmem > lowmem && 114 lowmem & ((1ULL << 30) - 1)) { 115 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 116 ") not a multiple of 1G; possible bad performance.", 117 pc_machine->max_ram_below_4g); 118 } 119 } 120 121 if (machine->ram_size >= lowmem) { 122 above_4g_mem_size = machine->ram_size - lowmem; 123 below_4g_mem_size = lowmem; 124 } else { 125 above_4g_mem_size = 0; 126 below_4g_mem_size = machine->ram_size; 127 } 128 129 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size, 130 &ram_memory) != 0) { 131 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 132 exit(1); 133 } 134 135 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 136 object_property_add_child(qdev_get_machine(), "icc-bridge", 137 OBJECT(icc_bridge), NULL); 138 139 pc_cpus_init(machine->cpu_model, icc_bridge); 140 pc_acpi_init("q35-acpi-dsdt.aml"); 141 142 kvmclock_create(); 143 144 /* pci enabled */ 145 if (pci_enabled) { 146 pci_memory = g_new(MemoryRegion, 1); 147 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 148 rom_memory = pci_memory; 149 } else { 150 pci_memory = NULL; 151 rom_memory = get_system_memory(); 152 } 153 154 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 155 guest_info->isapc_ram_fw = false; 156 guest_info->has_acpi_build = has_acpi_build; 157 guest_info->has_reserved_memory = has_reserved_memory; 158 guest_info->rsdp_in_ram = rsdp_in_ram; 159 160 /* Migration was not supported in 2.0 for Q35, so do not bother 161 * with this hack (see hw/i386/acpi-build.c). 162 */ 163 guest_info->legacy_acpi_table_size = 0; 164 165 if (smbios_defaults) { 166 MachineClass *mc = MACHINE_GET_CLASS(machine); 167 /* These values are guest ABI, do not change */ 168 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 169 mc->name, smbios_legacy_mode, smbios_uuid_encoded); 170 } 171 172 /* allocate ram and load rom/bios */ 173 if (!xen_enabled()) { 174 pc_memory_init(machine, get_system_memory(), 175 below_4g_mem_size, above_4g_mem_size, 176 rom_memory, &ram_memory, guest_info); 177 } 178 179 /* irq lines */ 180 gsi_state = g_malloc0(sizeof(*gsi_state)); 181 if (kvm_irqchip_in_kernel()) { 182 kvm_pc_setup_irq_routing(pci_enabled); 183 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 184 GSI_NUM_PINS); 185 } else { 186 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 187 } 188 189 /* create pci host bus */ 190 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 191 192 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 193 q35_host->mch.ram_memory = ram_memory; 194 q35_host->mch.pci_address_space = pci_memory; 195 q35_host->mch.system_memory = get_system_memory(); 196 q35_host->mch.address_space_io = get_system_io(); 197 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 198 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 199 q35_host->mch.guest_info = guest_info; 200 /* pci */ 201 qdev_init_nofail(DEVICE(q35_host)); 202 phb = PCI_HOST_BRIDGE(q35_host); 203 host_bus = phb->bus; 204 /* create ISA bus */ 205 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 206 ICH9_LPC_FUNC), true, 207 TYPE_ICH9_LPC_DEVICE); 208 209 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 210 TYPE_HOTPLUG_HANDLER, 211 (Object **)&pc_machine->acpi_dev, 212 object_property_allow_set_link, 213 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 214 object_property_set_link(OBJECT(machine), OBJECT(lpc), 215 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 216 217 ich9_lpc = ICH9_LPC_DEVICE(lpc); 218 ich9_lpc->pic = gsi; 219 ich9_lpc->ioapic = gsi_state->ioapic_irq; 220 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 221 ICH9_LPC_NB_PIRQS); 222 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 223 isa_bus = ich9_lpc->isa_bus; 224 225 /*end early*/ 226 isa_bus_irqs(isa_bus, gsi); 227 228 if (kvm_irqchip_in_kernel()) { 229 i8259 = kvm_i8259_init(isa_bus); 230 } else if (xen_enabled()) { 231 i8259 = xen_interrupt_controller_init(); 232 } else { 233 cpu_irq = pc_allocate_cpu_irq(); 234 i8259 = i8259_init(isa_bus, cpu_irq[0]); 235 } 236 237 for (i = 0; i < ISA_NUM_IRQS; i++) { 238 gsi_state->i8259_irq[i] = i8259[i]; 239 } 240 if (pci_enabled) { 241 ioapic_init_gsi(gsi_state, "q35"); 242 } 243 qdev_init_nofail(icc_bridge); 244 245 pc_register_ferr_irq(gsi[13]); 246 247 assert(pc_machine->vmport != ON_OFF_AUTO_MAX); 248 if (pc_machine->vmport == ON_OFF_AUTO_AUTO) { 249 pc_machine->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 250 } 251 252 /* init basic PC hardware */ 253 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, 254 (pc_machine->vmport != ON_OFF_AUTO_ON), 0xff0104); 255 256 /* connect pm stuff to lpc */ 257 ich9_lpc_pm_init(lpc); 258 259 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 260 ahci = pci_create_simple_multifunction(host_bus, 261 PCI_DEVFN(ICH9_SATA1_DEV, 262 ICH9_SATA1_FUNC), 263 true, "ich9-ahci"); 264 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 265 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 266 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 267 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 268 ahci_ide_create_devs(ahci, hd); 269 270 if (usb_enabled()) { 271 /* Should we create 6 UHCI according to ich9 spec? */ 272 ehci_create_ich9_with_companions(host_bus, 0x1d); 273 } 274 275 /* TODO: Populate SPD eeprom data. */ 276 smbus_eeprom_init(ich9_smb_init(host_bus, 277 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 278 0xb100), 279 8, NULL, 0); 280 281 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 282 machine, floppy, idebus[0], idebus[1], rtc_state); 283 284 /* the rest devices to which pci devfn is automatically assigned */ 285 pc_vga_init(isa_bus, host_bus); 286 pc_nic_init(isa_bus, host_bus); 287 if (pci_enabled) { 288 pc_pci_device_init(host_bus); 289 } 290 } 291 292 static void pc_compat_2_2(MachineState *machine) 293 { 294 rsdp_in_ram = false; 295 x86_cpu_compat_set_features("kvm64", FEAT_1_EDX, 0, CPUID_VME); 296 x86_cpu_compat_set_features("kvm32", FEAT_1_EDX, 0, CPUID_VME); 297 x86_cpu_compat_set_features("Conroe", FEAT_1_EDX, 0, CPUID_VME); 298 x86_cpu_compat_set_features("Penryn", FEAT_1_EDX, 0, CPUID_VME); 299 x86_cpu_compat_set_features("Nehalem", FEAT_1_EDX, 0, CPUID_VME); 300 x86_cpu_compat_set_features("Westmere", FEAT_1_EDX, 0, CPUID_VME); 301 x86_cpu_compat_set_features("SandyBridge", FEAT_1_EDX, 0, CPUID_VME); 302 x86_cpu_compat_set_features("Haswell", FEAT_1_EDX, 0, CPUID_VME); 303 x86_cpu_compat_set_features("Broadwell", FEAT_1_EDX, 0, CPUID_VME); 304 x86_cpu_compat_set_features("Opteron_G1", FEAT_1_EDX, 0, CPUID_VME); 305 x86_cpu_compat_set_features("Opteron_G2", FEAT_1_EDX, 0, CPUID_VME); 306 x86_cpu_compat_set_features("Opteron_G3", FEAT_1_EDX, 0, CPUID_VME); 307 x86_cpu_compat_set_features("Opteron_G4", FEAT_1_EDX, 0, CPUID_VME); 308 x86_cpu_compat_set_features("Opteron_G5", FEAT_1_EDX, 0, CPUID_VME); 309 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_F16C); 310 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); 311 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C); 312 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND); 313 machine->suppress_vmdesc = true; 314 } 315 316 static void pc_compat_2_1(MachineState *machine) 317 { 318 PCMachineState *pcms = PC_MACHINE(machine); 319 320 pc_compat_2_2(machine); 321 pcms->enforce_aligned_dimm = false; 322 smbios_uuid_encoded = false; 323 x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); 324 x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); 325 x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM); 326 } 327 328 static void pc_compat_2_0(MachineState *machine) 329 { 330 pc_compat_2_1(machine); 331 smbios_legacy_mode = true; 332 has_reserved_memory = false; 333 pc_set_legacy_acpi_data_size(); 334 } 335 336 static void pc_compat_1_7(MachineState *machine) 337 { 338 pc_compat_2_0(machine); 339 smbios_defaults = false; 340 gigabyte_align = false; 341 option_rom_has_mr = true; 342 x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC); 343 } 344 345 static void pc_compat_1_6(MachineState *machine) 346 { 347 pc_compat_1_7(machine); 348 rom_file_has_mr = false; 349 has_acpi_build = false; 350 } 351 352 static void pc_compat_1_5(MachineState *machine) 353 { 354 pc_compat_1_6(machine); 355 } 356 357 static void pc_compat_1_4(MachineState *machine) 358 { 359 pc_compat_1_5(machine); 360 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 361 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 362 } 363 364 static void pc_q35_init_2_2(MachineState *machine) 365 { 366 pc_compat_2_2(machine); 367 pc_q35_init(machine); 368 } 369 370 static void pc_q35_init_2_1(MachineState *machine) 371 { 372 pc_compat_2_1(machine); 373 pc_q35_init(machine); 374 } 375 376 static void pc_q35_init_2_0(MachineState *machine) 377 { 378 pc_compat_2_0(machine); 379 pc_q35_init(machine); 380 } 381 382 static void pc_q35_init_1_7(MachineState *machine) 383 { 384 pc_compat_1_7(machine); 385 pc_q35_init(machine); 386 } 387 388 static void pc_q35_init_1_6(MachineState *machine) 389 { 390 pc_compat_1_6(machine); 391 pc_q35_init(machine); 392 } 393 394 static void pc_q35_init_1_5(MachineState *machine) 395 { 396 pc_compat_1_5(machine); 397 pc_q35_init(machine); 398 } 399 400 static void pc_q35_init_1_4(MachineState *machine) 401 { 402 pc_compat_1_4(machine); 403 pc_q35_init(machine); 404 } 405 406 #define PC_Q35_MACHINE_OPTIONS \ 407 PC_DEFAULT_MACHINE_OPTIONS, \ 408 .family = "pc_q35", \ 409 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 410 .hot_add_cpu = pc_hot_add_cpu, \ 411 .units_per_default_bus = 1 412 413 #define PC_Q35_2_3_MACHINE_OPTIONS \ 414 PC_Q35_MACHINE_OPTIONS, \ 415 .default_machine_opts = "firmware=bios-256k.bin", \ 416 .default_display = "std" 417 418 static QEMUMachine pc_q35_machine_v2_3 = { 419 PC_Q35_2_3_MACHINE_OPTIONS, 420 .name = "pc-q35-2.3", 421 .alias = "q35", 422 .init = pc_q35_init, 423 }; 424 425 #define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS 426 427 static QEMUMachine pc_q35_machine_v2_2 = { 428 PC_Q35_2_2_MACHINE_OPTIONS, 429 .name = "pc-q35-2.2", 430 .init = pc_q35_init_2_2, 431 }; 432 433 #define PC_Q35_2_1_MACHINE_OPTIONS \ 434 PC_Q35_MACHINE_OPTIONS, \ 435 .default_machine_opts = "firmware=bios-256k.bin" 436 437 static QEMUMachine pc_q35_machine_v2_1 = { 438 PC_Q35_2_1_MACHINE_OPTIONS, 439 .name = "pc-q35-2.1", 440 .init = pc_q35_init_2_1, 441 .compat_props = (GlobalProperty[]) { 442 HW_COMPAT_2_1, 443 { /* end of list */ } 444 }, 445 }; 446 447 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS 448 449 static QEMUMachine pc_q35_machine_v2_0 = { 450 PC_Q35_2_0_MACHINE_OPTIONS, 451 .name = "pc-q35-2.0", 452 .init = pc_q35_init_2_0, 453 .compat_props = (GlobalProperty[]) { 454 PC_COMPAT_2_0, 455 { /* end of list */ } 456 }, 457 }; 458 459 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 460 461 static QEMUMachine pc_q35_machine_v1_7 = { 462 PC_Q35_1_7_MACHINE_OPTIONS, 463 .name = "pc-q35-1.7", 464 .init = pc_q35_init_1_7, 465 .compat_props = (GlobalProperty[]) { 466 PC_COMPAT_1_7, 467 { /* end of list */ } 468 }, 469 }; 470 471 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 472 473 static QEMUMachine pc_q35_machine_v1_6 = { 474 PC_Q35_1_6_MACHINE_OPTIONS, 475 .name = "pc-q35-1.6", 476 .init = pc_q35_init_1_6, 477 .compat_props = (GlobalProperty[]) { 478 PC_COMPAT_1_6, 479 { /* end of list */ } 480 }, 481 }; 482 483 static QEMUMachine pc_q35_machine_v1_5 = { 484 PC_Q35_1_6_MACHINE_OPTIONS, 485 .name = "pc-q35-1.5", 486 .init = pc_q35_init_1_5, 487 .compat_props = (GlobalProperty[]) { 488 PC_COMPAT_1_5, 489 { /* end of list */ } 490 }, 491 }; 492 493 #define PC_Q35_1_4_MACHINE_OPTIONS \ 494 PC_Q35_1_6_MACHINE_OPTIONS, \ 495 .hot_add_cpu = NULL 496 497 static QEMUMachine pc_q35_machine_v1_4 = { 498 PC_Q35_1_4_MACHINE_OPTIONS, 499 .name = "pc-q35-1.4", 500 .init = pc_q35_init_1_4, 501 .compat_props = (GlobalProperty[]) { 502 PC_COMPAT_1_4, 503 { /* end of list */ } 504 }, 505 }; 506 507 static void pc_q35_machine_init(void) 508 { 509 qemu_register_pc_machine(&pc_q35_machine_v2_3); 510 qemu_register_pc_machine(&pc_q35_machine_v2_2); 511 qemu_register_pc_machine(&pc_q35_machine_v2_1); 512 qemu_register_pc_machine(&pc_q35_machine_v2_0); 513 qemu_register_pc_machine(&pc_q35_machine_v1_7); 514 qemu_register_pc_machine(&pc_q35_machine_v1_6); 515 qemu_register_pc_machine(&pc_q35_machine_v1_5); 516 qemu_register_pc_machine(&pc_q35_machine_v1_4); 517 } 518 519 machine_init(pc_q35_machine_init); 520