1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/ide/pci.h" 43 #include "hw/ide/ahci.h" 44 #include "hw/usb.h" 45 #include "hw/cpu/icc_bus.h" 46 47 /* ICH9 AHCI has 6 ports */ 48 #define MAX_SATA_PORTS 6 49 50 static bool has_pvpanic; 51 static bool has_pci_info = true; 52 53 /* PC hardware initialisation */ 54 static void pc_q35_init(QEMUMachineInitArgs *args) 55 { 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 Q35PCIHost *q35_host; 58 PCIHostState *phb; 59 PCIBus *host_bus; 60 PCIDevice *lpc; 61 BusState *idebus[MAX_SATA_PORTS]; 62 ISADevice *rtc_state; 63 ISADevice *floppy; 64 MemoryRegion *pci_memory; 65 MemoryRegion *rom_memory; 66 MemoryRegion *ram_memory; 67 GSIState *gsi_state; 68 ISABus *isa_bus; 69 int pci_enabled = 1; 70 qemu_irq *cpu_irq; 71 qemu_irq *gsi; 72 qemu_irq *i8259; 73 int i; 74 ICH9LPCState *ich9_lpc; 75 PCIDevice *ahci; 76 DeviceState *icc_bridge; 77 PcGuestInfo *guest_info; 78 79 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 80 object_property_add_child(qdev_get_machine(), "icc-bridge", 81 OBJECT(icc_bridge), NULL); 82 83 pc_cpus_init(args->cpu_model, icc_bridge); 84 pc_acpi_init("q35-acpi-dsdt.aml"); 85 86 kvmclock_create(); 87 88 if (args->ram_size >= 0xb0000000) { 89 above_4g_mem_size = args->ram_size - 0xb0000000; 90 below_4g_mem_size = 0xb0000000; 91 } else { 92 above_4g_mem_size = 0; 93 below_4g_mem_size = args->ram_size; 94 } 95 96 /* pci enabled */ 97 if (pci_enabled) { 98 pci_memory = g_new(MemoryRegion, 1); 99 memory_region_init(pci_memory, NULL, "pci", INT64_MAX); 100 rom_memory = pci_memory; 101 } else { 102 pci_memory = NULL; 103 rom_memory = get_system_memory(); 104 } 105 106 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 107 guest_info->has_pci_info = has_pci_info; 108 guest_info->isapc_ram_fw = false; 109 110 /* allocate ram and load rom/bios */ 111 if (!xen_enabled()) { 112 pc_memory_init(get_system_memory(), 113 args->kernel_filename, args->kernel_cmdline, 114 args->initrd_filename, 115 below_4g_mem_size, above_4g_mem_size, 116 rom_memory, &ram_memory, guest_info); 117 } 118 119 /* irq lines */ 120 gsi_state = g_malloc0(sizeof(*gsi_state)); 121 if (kvm_irqchip_in_kernel()) { 122 kvm_pc_setup_irq_routing(pci_enabled); 123 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 124 GSI_NUM_PINS); 125 } else { 126 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 127 } 128 129 /* create pci host bus */ 130 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 131 132 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 133 q35_host->mch.ram_memory = ram_memory; 134 q35_host->mch.pci_address_space = pci_memory; 135 q35_host->mch.system_memory = get_system_memory(); 136 q35_host->mch.address_space_io = get_system_io(); 137 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 138 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 139 q35_host->mch.guest_info = guest_info; 140 /* pci */ 141 qdev_init_nofail(DEVICE(q35_host)); 142 phb = PCI_HOST_BRIDGE(q35_host); 143 host_bus = phb->bus; 144 /* create ISA bus */ 145 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 146 ICH9_LPC_FUNC), true, 147 TYPE_ICH9_LPC_DEVICE); 148 ich9_lpc = ICH9_LPC_DEVICE(lpc); 149 ich9_lpc->pic = gsi; 150 ich9_lpc->ioapic = gsi_state->ioapic_irq; 151 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 152 ICH9_LPC_NB_PIRQS); 153 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 154 isa_bus = ich9_lpc->isa_bus; 155 156 /*end early*/ 157 isa_bus_irqs(isa_bus, gsi); 158 159 if (kvm_irqchip_in_kernel()) { 160 i8259 = kvm_i8259_init(isa_bus); 161 } else if (xen_enabled()) { 162 i8259 = xen_interrupt_controller_init(); 163 } else { 164 cpu_irq = pc_allocate_cpu_irq(); 165 i8259 = i8259_init(isa_bus, cpu_irq[0]); 166 } 167 168 for (i = 0; i < ISA_NUM_IRQS; i++) { 169 gsi_state->i8259_irq[i] = i8259[i]; 170 } 171 if (pci_enabled) { 172 ioapic_init_gsi(gsi_state, NULL); 173 } 174 qdev_init_nofail(icc_bridge); 175 176 pc_register_ferr_irq(gsi[13]); 177 178 /* init basic PC hardware */ 179 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 180 181 /* connect pm stuff to lpc */ 182 ich9_lpc_pm_init(lpc); 183 184 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 185 ahci = pci_create_simple_multifunction(host_bus, 186 PCI_DEVFN(ICH9_SATA1_DEV, 187 ICH9_SATA1_FUNC), 188 true, "ich9-ahci"); 189 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 190 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 191 192 if (usb_enabled(false)) { 193 /* Should we create 6 UHCI according to ich9 spec? */ 194 ehci_create_ich9_with_companions(host_bus, 0x1d); 195 } 196 197 /* TODO: Populate SPD eeprom data. */ 198 smbus_eeprom_init(ich9_smb_init(host_bus, 199 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 200 0xb100), 201 8, NULL, 0); 202 203 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_device, 204 floppy, idebus[0], idebus[1], rtc_state); 205 206 /* the rest devices to which pci devfn is automatically assigned */ 207 pc_vga_init(isa_bus, host_bus); 208 pc_nic_init(isa_bus, host_bus); 209 if (pci_enabled) { 210 pc_pci_device_init(host_bus); 211 } 212 213 if (has_pvpanic) { 214 pvpanic_init(isa_bus); 215 } 216 } 217 218 static void pc_compat_1_6(QEMUMachineInitArgs *args) 219 { 220 has_pci_info = false; 221 rom_file_in_ram = false; 222 } 223 224 static void pc_compat_1_5(QEMUMachineInitArgs *args) 225 { 226 pc_compat_1_6(args); 227 has_pvpanic = true; 228 } 229 230 static void pc_compat_1_4(QEMUMachineInitArgs *args) 231 { 232 pc_compat_1_5(args); 233 has_pvpanic = false; 234 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 235 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 236 } 237 238 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 239 { 240 pc_compat_1_6(args); 241 pc_q35_init(args); 242 } 243 244 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 245 { 246 pc_compat_1_5(args); 247 pc_q35_init(args); 248 } 249 250 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 251 { 252 pc_compat_1_4(args); 253 pc_q35_init(args); 254 } 255 256 static QEMUMachine pc_q35_machine_v1_6 = { 257 .name = "pc-q35-1.6", 258 .alias = "q35", 259 .desc = "Standard PC (Q35 + ICH9, 2009)", 260 .init = pc_q35_init_1_6, 261 .hot_add_cpu = pc_hot_add_cpu, 262 .max_cpus = 255, 263 DEFAULT_MACHINE_OPTIONS, 264 }; 265 266 static QEMUMachine pc_q35_machine_v1_5 = { 267 .name = "pc-q35-1.5", 268 .desc = "Standard PC (Q35 + ICH9, 2009)", 269 .init = pc_q35_init_1_5, 270 .hot_add_cpu = pc_hot_add_cpu, 271 .max_cpus = 255, 272 .compat_props = (GlobalProperty[]) { 273 PC_COMPAT_1_5, 274 { /* end of list */ } 275 }, 276 DEFAULT_MACHINE_OPTIONS, 277 }; 278 279 static QEMUMachine pc_q35_machine_v1_4 = { 280 .name = "pc-q35-1.4", 281 .desc = "Standard PC (Q35 + ICH9, 2009)", 282 .init = pc_q35_init_1_4, 283 .max_cpus = 255, 284 .compat_props = (GlobalProperty[]) { 285 PC_COMPAT_1_4, 286 { /* end of list */ } 287 }, 288 DEFAULT_MACHINE_OPTIONS, 289 }; 290 291 static void pc_q35_machine_init(void) 292 { 293 qemu_register_machine(&pc_q35_machine_v1_6); 294 qemu_register_machine(&pc_q35_machine_v1_5); 295 qemu_register_machine(&pc_q35_machine_v1_4); 296 } 297 298 machine_init(pc_q35_machine_init); 299