1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/char/parallel-isa.h" 34 #include "hw/loader.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/kvm.h" 39 #include "hw/i386/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "hw/pci/pcie_port.h" 42 #include "hw/qdev-properties.h" 43 #include "hw/i386/x86.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci-pci.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/southbridge/ich9.h" 52 #include "hw/usb.h" 53 #include "hw/usb/hcd-uhci.h" 54 #include "qapi/error.h" 55 #include "qemu/error-report.h" 56 #include "sysemu/numa.h" 57 #include "hw/hyperv/vmbus-bridge.h" 58 #include "hw/mem/nvdimm.h" 59 #include "hw/i386/acpi-build.h" 60 #include "target/i386/cpu.h" 61 62 /* ICH9 AHCI has 6 ports */ 63 #define MAX_SATA_PORTS 6 64 65 struct ehci_companions { 66 const char *name; 67 int func; 68 int port; 69 }; 70 71 static const struct ehci_companions ich9_1d[] = { 72 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 73 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 74 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 75 }; 76 77 static const struct ehci_companions ich9_1a[] = { 78 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 79 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 80 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 81 }; 82 83 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 84 { 85 const struct ehci_companions *comp; 86 PCIDevice *ehci, *uhci; 87 BusState *usbbus; 88 const char *name; 89 int i; 90 91 switch (slot) { 92 case 0x1d: 93 name = "ich9-usb-ehci1"; 94 comp = ich9_1d; 95 break; 96 case 0x1a: 97 name = "ich9-usb-ehci2"; 98 comp = ich9_1a; 99 break; 100 default: 101 return -1; 102 } 103 104 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 105 pci_realize_and_unref(ehci, bus, &error_fatal); 106 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 107 108 for (i = 0; i < 3; i++) { 109 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 110 comp[i].name); 111 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 112 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 113 pci_realize_and_unref(uhci, bus, &error_fatal); 114 } 115 return 0; 116 } 117 118 /* PC hardware initialisation */ 119 static void pc_q35_init(MachineState *machine) 120 { 121 PCMachineState *pcms = PC_MACHINE(machine); 122 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 123 X86MachineState *x86ms = X86_MACHINE(machine); 124 Object *phb; 125 PCIBus *host_bus; 126 PCIDevice *lpc; 127 DeviceState *lpc_dev; 128 ISADevice *rtc_state; 129 MemoryRegion *system_memory = get_system_memory(); 130 MemoryRegion *system_io = get_system_io(); 131 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 132 GSIState *gsi_state; 133 ISABus *isa_bus; 134 int i; 135 ram_addr_t lowmem; 136 DriveInfo *hd[MAX_SATA_PORTS]; 137 MachineClass *mc = MACHINE_GET_CLASS(machine); 138 bool acpi_pcihp; 139 bool keep_pci_slot_hpc; 140 uint64_t pci_hole64_size = 0; 141 142 assert(pcmc->pci_enabled); 143 144 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 145 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 146 * also known as MMCFG). 147 * If it doesn't, we need to split it in chunks below and above 4G. 148 * In any case, try to make sure that guest addresses aligned at 149 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 150 */ 151 if (machine->ram_size >= 0xb0000000) { 152 lowmem = 0x80000000; 153 } else { 154 lowmem = 0xb0000000; 155 } 156 157 /* Handle the machine opt max-ram-below-4g. It is basically doing 158 * min(qemu limit, user limit). 159 */ 160 if (!pcms->max_ram_below_4g) { 161 pcms->max_ram_below_4g = 4 * GiB; 162 } 163 if (lowmem > pcms->max_ram_below_4g) { 164 lowmem = pcms->max_ram_below_4g; 165 if (machine->ram_size - lowmem > lowmem && 166 lowmem & (1 * GiB - 1)) { 167 warn_report("There is possibly poor performance as the ram size " 168 " (0x%" PRIx64 ") is more then twice the size of" 169 " max-ram-below-4g (%"PRIu64") and" 170 " max-ram-below-4g is not a multiple of 1G.", 171 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 172 } 173 } 174 175 if (machine->ram_size >= lowmem) { 176 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 177 x86ms->below_4g_mem_size = lowmem; 178 } else { 179 x86ms->above_4g_mem_size = 0; 180 x86ms->below_4g_mem_size = machine->ram_size; 181 } 182 183 pc_machine_init_sgx_epc(pcms); 184 x86_cpus_init(x86ms, pcmc->default_cpu_version); 185 186 if (kvm_enabled()) { 187 kvmclock_create(pcmc->kvmclock_create_always); 188 } 189 190 /* create pci host bus */ 191 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 192 193 pci_hole64_size = object_property_get_uint(phb, 194 PCI_HOST_PROP_PCI_HOLE64_SIZE, 195 &error_abort); 196 197 /* allocate ram and load rom/bios */ 198 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 199 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 200 201 object_property_add_child(OBJECT(machine), "q35", phb); 202 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 203 OBJECT(machine->ram), NULL); 204 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 205 OBJECT(pci_memory), NULL); 206 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 207 OBJECT(system_memory), NULL); 208 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 209 OBJECT(system_io), NULL); 210 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 211 x86ms->below_4g_mem_size, NULL); 212 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 213 x86ms->above_4g_mem_size, NULL); 214 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 215 pcms->default_bus_bypass_iommu, NULL); 216 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 217 218 /* pci */ 219 host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 220 pcms->bus = host_bus; 221 222 /* irq lines */ 223 gsi_state = pc_gsi_create(&x86ms->gsi, true); 224 225 /* create ISA bus */ 226 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 227 TYPE_ICH9_LPC_DEVICE); 228 lpc_dev = DEVICE(lpc); 229 qdev_prop_set_bit(lpc_dev, "smm-enabled", 230 x86_machine_is_smm_enabled(x86ms)); 231 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 232 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 233 } 234 pci_realize_and_unref(lpc, host_bus, &error_fatal); 235 236 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 237 238 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 239 TYPE_HOTPLUG_HANDLER, 240 (Object **)&x86ms->acpi_dev, 241 object_property_allow_set_link, 242 OBJ_PROP_LINK_STRONG); 243 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 244 OBJECT(lpc), &error_abort); 245 246 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 247 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 248 NULL); 249 250 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 251 "x-keep-pci-slot-hpc", 252 NULL); 253 254 if (!keep_pci_slot_hpc && acpi_pcihp) { 255 object_register_sugar_prop(TYPE_PCIE_SLOT, 256 "x-do-not-expose-native-hotplug-cap", 257 "true", true); 258 } 259 260 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 261 262 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 263 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 264 } 265 266 ioapic_init_gsi(gsi_state, "q35"); 267 268 if (tcg_enabled()) { 269 x86_register_ferr_irq(x86ms->gsi[13]); 270 } 271 272 assert(pcms->vmport != ON_OFF_AUTO__MAX); 273 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 274 pcms->vmport = ON_OFF_AUTO_ON; 275 } 276 277 /* init basic PC hardware */ 278 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 279 0xff0104); 280 281 if (pcms->sata_enabled) { 282 PCIDevice *pdev; 283 AHCIPCIState *ich9; 284 285 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 286 pdev = pci_create_simple_multifunction(host_bus, 287 PCI_DEVFN(ICH9_SATA1_DEV, 288 ICH9_SATA1_FUNC), 289 "ich9-ahci"); 290 ich9 = ICH9_AHCI(pdev); 291 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 292 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 293 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 294 ide_drive_get(hd, ich9->ahci.ports); 295 ahci_ide_create_devs(&ich9->ahci, hd); 296 } 297 298 if (machine_usb(machine)) { 299 /* Should we create 6 UHCI according to ich9 spec? */ 300 ehci_create_ich9_with_companions(host_bus, 0x1d); 301 } 302 303 if (pcms->smbus_enabled) { 304 PCIDevice *smb; 305 306 /* TODO: Populate SPD eeprom data. */ 307 smb = pci_create_simple_multifunction(host_bus, 308 PCI_DEVFN(ICH9_SMB_DEV, 309 ICH9_SMB_FUNC), 310 TYPE_ICH9_SMB_DEVICE); 311 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 312 313 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 314 } 315 316 pc_cmos_init(pcms, rtc_state); 317 318 /* the rest devices to which pci devfn is automatically assigned */ 319 pc_vga_init(isa_bus, host_bus); 320 pc_nic_init(pcmc, isa_bus, host_bus); 321 322 if (machine->nvdimms_state->is_enabled) { 323 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 324 x86_nvdimm_acpi_dsmio, 325 x86ms->fw_cfg, OBJECT(pcms)); 326 } 327 } 328 329 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 330 static void pc_init_##suffix(MachineState *machine) \ 331 { \ 332 void (*compat)(MachineState *m) = (compatfn); \ 333 if (compat) { \ 334 compat(machine); \ 335 } \ 336 pc_q35_init(machine); \ 337 } \ 338 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 339 340 341 static void pc_q35_machine_options(MachineClass *m) 342 { 343 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 344 pcmc->pci_root_uid = 0; 345 pcmc->default_cpu_version = 1; 346 347 m->family = "pc_q35"; 348 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 349 m->units_per_default_bus = 1; 350 m->default_machine_opts = "firmware=bios-256k.bin"; 351 m->default_display = "std"; 352 m->default_nic = "e1000e"; 353 m->default_kernel_irqchip_split = false; 354 m->no_floppy = 1; 355 m->max_cpus = 1024; 356 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 357 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 358 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 359 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 360 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 361 } 362 363 static void pc_q35_9_0_machine_options(MachineClass *m) 364 { 365 pc_q35_machine_options(m); 366 m->alias = "q35"; 367 } 368 369 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, 370 pc_q35_9_0_machine_options); 371 372 static void pc_q35_8_2_machine_options(MachineClass *m) 373 { 374 pc_q35_9_0_machine_options(m); 375 m->alias = NULL; 376 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 377 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 378 } 379 380 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 381 pc_q35_8_2_machine_options); 382 383 static void pc_q35_8_1_machine_options(MachineClass *m) 384 { 385 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 386 pc_q35_8_2_machine_options(m); 387 m->alias = NULL; 388 pcmc->broken_32bit_mem_addr_check = true; 389 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 390 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 391 } 392 393 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 394 pc_q35_8_1_machine_options); 395 396 static void pc_q35_8_0_machine_options(MachineClass *m) 397 { 398 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 399 400 pc_q35_8_1_machine_options(m); 401 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 402 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 403 404 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 405 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 406 m->max_cpus = 288; 407 } 408 409 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 410 pc_q35_8_0_machine_options); 411 412 static void pc_q35_7_2_machine_options(MachineClass *m) 413 { 414 pc_q35_8_0_machine_options(m); 415 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 416 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 417 } 418 419 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 420 pc_q35_7_2_machine_options); 421 422 static void pc_q35_7_1_machine_options(MachineClass *m) 423 { 424 pc_q35_7_2_machine_options(m); 425 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 426 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 427 } 428 429 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 430 pc_q35_7_1_machine_options); 431 432 static void pc_q35_7_0_machine_options(MachineClass *m) 433 { 434 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 435 pc_q35_7_1_machine_options(m); 436 pcmc->enforce_amd_1tb_hole = false; 437 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 438 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 439 } 440 441 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 442 pc_q35_7_0_machine_options); 443 444 static void pc_q35_6_2_machine_options(MachineClass *m) 445 { 446 pc_q35_7_0_machine_options(m); 447 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 448 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 449 } 450 451 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 452 pc_q35_6_2_machine_options); 453 454 static void pc_q35_6_1_machine_options(MachineClass *m) 455 { 456 pc_q35_6_2_machine_options(m); 457 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 458 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 459 m->smp_props.prefer_sockets = true; 460 } 461 462 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 463 pc_q35_6_1_machine_options); 464 465 static void pc_q35_6_0_machine_options(MachineClass *m) 466 { 467 pc_q35_6_1_machine_options(m); 468 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 469 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 470 } 471 472 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 473 pc_q35_6_0_machine_options); 474 475 static void pc_q35_5_2_machine_options(MachineClass *m) 476 { 477 pc_q35_6_0_machine_options(m); 478 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 479 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 480 } 481 482 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 483 pc_q35_5_2_machine_options); 484 485 static void pc_q35_5_1_machine_options(MachineClass *m) 486 { 487 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 488 489 pc_q35_5_2_machine_options(m); 490 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 491 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 492 pcmc->kvmclock_create_always = false; 493 pcmc->pci_root_uid = 1; 494 } 495 496 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 497 pc_q35_5_1_machine_options); 498 499 static void pc_q35_5_0_machine_options(MachineClass *m) 500 { 501 pc_q35_5_1_machine_options(m); 502 m->numa_mem_supported = true; 503 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 504 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 505 m->auto_enable_numa_with_memdev = false; 506 } 507 508 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 509 pc_q35_5_0_machine_options); 510 511 static void pc_q35_4_2_machine_options(MachineClass *m) 512 { 513 pc_q35_5_0_machine_options(m); 514 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 515 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 516 } 517 518 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 519 pc_q35_4_2_machine_options); 520 521 static void pc_q35_4_1_machine_options(MachineClass *m) 522 { 523 pc_q35_4_2_machine_options(m); 524 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 525 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 526 } 527 528 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 529 pc_q35_4_1_machine_options); 530 531 static void pc_q35_4_0_1_machine_options(MachineClass *m) 532 { 533 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 534 pc_q35_4_1_machine_options(m); 535 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 536 /* 537 * This is the default machine for the 4.0-stable branch. It is basically 538 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 539 * 4.0 compat props. 540 */ 541 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 542 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 543 } 544 545 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 546 pc_q35_4_0_1_machine_options); 547 548 static void pc_q35_4_0_machine_options(MachineClass *m) 549 { 550 pc_q35_4_0_1_machine_options(m); 551 m->default_kernel_irqchip_split = true; 552 /* Compat props are applied by the 4.0.1 machine */ 553 } 554 555 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 556 pc_q35_4_0_machine_options); 557 558 static void pc_q35_3_1_machine_options(MachineClass *m) 559 { 560 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 561 562 pc_q35_4_0_machine_options(m); 563 m->default_kernel_irqchip_split = false; 564 m->smbus_no_migration_support = true; 565 pcmc->pvh_enabled = false; 566 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 567 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 568 } 569 570 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 571 pc_q35_3_1_machine_options); 572 573 static void pc_q35_3_0_machine_options(MachineClass *m) 574 { 575 pc_q35_3_1_machine_options(m); 576 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 577 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 578 } 579 580 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 581 pc_q35_3_0_machine_options); 582 583 static void pc_q35_2_12_machine_options(MachineClass *m) 584 { 585 pc_q35_3_0_machine_options(m); 586 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 587 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 588 } 589 590 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 591 pc_q35_2_12_machine_options); 592 593 static void pc_q35_2_11_machine_options(MachineClass *m) 594 { 595 pc_q35_2_12_machine_options(m); 596 m->default_nic = "e1000"; 597 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 598 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 599 } 600 601 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 602 pc_q35_2_11_machine_options); 603 604 static void pc_q35_2_10_machine_options(MachineClass *m) 605 { 606 pc_q35_2_11_machine_options(m); 607 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 608 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 609 m->auto_enable_numa_with_memhp = false; 610 } 611 612 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 613 pc_q35_2_10_machine_options); 614 615 static void pc_q35_2_9_machine_options(MachineClass *m) 616 { 617 pc_q35_2_10_machine_options(m); 618 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 619 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 620 } 621 622 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 623 pc_q35_2_9_machine_options); 624 625 static void pc_q35_2_8_machine_options(MachineClass *m) 626 { 627 pc_q35_2_9_machine_options(m); 628 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 629 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 630 } 631 632 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 633 pc_q35_2_8_machine_options); 634 635 static void pc_q35_2_7_machine_options(MachineClass *m) 636 { 637 pc_q35_2_8_machine_options(m); 638 m->max_cpus = 255; 639 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 640 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 641 } 642 643 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 644 pc_q35_2_7_machine_options); 645 646 static void pc_q35_2_6_machine_options(MachineClass *m) 647 { 648 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 649 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 650 651 pc_q35_2_7_machine_options(m); 652 pcmc->legacy_cpu_hotplug = true; 653 x86mc->fwcfg_dma_enabled = false; 654 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 655 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 656 } 657 658 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 659 pc_q35_2_6_machine_options); 660 661 static void pc_q35_2_5_machine_options(MachineClass *m) 662 { 663 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 664 665 pc_q35_2_6_machine_options(m); 666 x86mc->save_tsc_khz = false; 667 m->legacy_fw_cfg_order = 1; 668 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 669 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 670 } 671 672 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 673 pc_q35_2_5_machine_options); 674 675 static void pc_q35_2_4_machine_options(MachineClass *m) 676 { 677 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 678 679 pc_q35_2_5_machine_options(m); 680 m->hw_version = "2.4.0"; 681 pcmc->broken_reserved_end = true; 682 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 683 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 684 } 685 686 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 687 pc_q35_2_4_machine_options); 688