1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/loader.h" 33 #include "sysemu/arch_init.h" 34 #include "hw/i2c/smbus.h" 35 #include "hw/boards.h" 36 #include "hw/timer/mc146818rtc.h" 37 #include "hw/xen/xen.h" 38 #include "sysemu/kvm.h" 39 #include "hw/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "exec/address-spaces.h" 42 #include "hw/i386/pc.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/smbios/smbios.h" 45 #include "hw/ide/pci.h" 46 #include "hw/ide/ahci.h" 47 #include "hw/usb.h" 48 #include "qemu/error-report.h" 49 #include "migration/migration.h" 50 51 /* ICH9 AHCI has 6 ports */ 52 #define MAX_SATA_PORTS 6 53 54 /* PC hardware initialisation */ 55 static void pc_q35_init(MachineState *machine) 56 { 57 PCMachineState *pcms = PC_MACHINE(machine); 58 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 59 Q35PCIHost *q35_host; 60 PCIHostState *phb; 61 PCIBus *host_bus; 62 PCIDevice *lpc; 63 DeviceState *lpc_dev; 64 BusState *idebus[MAX_SATA_PORTS]; 65 ISADevice *rtc_state; 66 MemoryRegion *system_io = get_system_io(); 67 MemoryRegion *pci_memory; 68 MemoryRegion *rom_memory; 69 MemoryRegion *ram_memory; 70 GSIState *gsi_state; 71 ISABus *isa_bus; 72 qemu_irq *i8259; 73 int i; 74 ICH9LPCState *ich9_lpc; 75 PCIDevice *ahci; 76 ram_addr_t lowmem; 77 DriveInfo *hd[MAX_SATA_PORTS]; 78 MachineClass *mc = MACHINE_GET_CLASS(machine); 79 80 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 81 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 82 * also known as MMCFG). 83 * If it doesn't, we need to split it in chunks below and above 4G. 84 * In any case, try to make sure that guest addresses aligned at 85 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 86 */ 87 if (machine->ram_size >= 0xb0000000) { 88 lowmem = 0x80000000; 89 } else { 90 lowmem = 0xb0000000; 91 } 92 93 /* Handle the machine opt max-ram-below-4g. It is basically doing 94 * min(qemu limit, user limit). 95 */ 96 if (!pcms->max_ram_below_4g) { 97 pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */; 98 } 99 if (lowmem > pcms->max_ram_below_4g) { 100 lowmem = pcms->max_ram_below_4g; 101 if (machine->ram_size - lowmem > lowmem && 102 lowmem & ((1ULL << 30) - 1)) { 103 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 104 ") not a multiple of 1G; possible bad performance.", 105 pcms->max_ram_below_4g); 106 } 107 } 108 109 if (machine->ram_size >= lowmem) { 110 pcms->above_4g_mem_size = machine->ram_size - lowmem; 111 pcms->below_4g_mem_size = lowmem; 112 } else { 113 pcms->above_4g_mem_size = 0; 114 pcms->below_4g_mem_size = machine->ram_size; 115 } 116 117 if (xen_enabled()) { 118 xen_hvm_init(pcms, &ram_memory); 119 } 120 121 pc_cpus_init(pcms); 122 123 kvmclock_create(); 124 125 /* pci enabled */ 126 if (pcmc->pci_enabled) { 127 pci_memory = g_new(MemoryRegion, 1); 128 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 129 rom_memory = pci_memory; 130 } else { 131 pci_memory = NULL; 132 rom_memory = get_system_memory(); 133 } 134 135 pc_guest_info_init(pcms); 136 137 if (pcmc->smbios_defaults) { 138 /* These values are guest ABI, do not change */ 139 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 140 mc->name, pcmc->smbios_legacy_mode, 141 pcmc->smbios_uuid_encoded, 142 SMBIOS_ENTRY_POINT_21); 143 } 144 145 /* allocate ram and load rom/bios */ 146 if (!xen_enabled()) { 147 pc_memory_init(pcms, get_system_memory(), 148 rom_memory, &ram_memory); 149 } 150 151 /* irq lines */ 152 gsi_state = g_malloc0(sizeof(*gsi_state)); 153 if (kvm_ioapic_in_kernel()) { 154 kvm_pc_setup_irq_routing(pcmc->pci_enabled); 155 pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 156 GSI_NUM_PINS); 157 } else { 158 pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 159 } 160 161 /* create pci host bus */ 162 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 163 164 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 165 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 166 MCH_HOST_PROP_RAM_MEM, NULL); 167 object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 168 MCH_HOST_PROP_PCI_MEM, NULL); 169 object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 170 MCH_HOST_PROP_SYSTEM_MEM, NULL); 171 object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 172 MCH_HOST_PROP_IO_MEM, NULL); 173 object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size, 174 PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 175 object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size, 176 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 177 /* pci */ 178 qdev_init_nofail(DEVICE(q35_host)); 179 phb = PCI_HOST_BRIDGE(q35_host); 180 host_bus = phb->bus; 181 /* create ISA bus */ 182 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 183 ICH9_LPC_FUNC), true, 184 TYPE_ICH9_LPC_DEVICE); 185 186 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 187 TYPE_HOTPLUG_HANDLER, 188 (Object **)&pcms->acpi_dev, 189 object_property_allow_set_link, 190 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 191 object_property_set_link(OBJECT(machine), OBJECT(lpc), 192 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 193 194 ich9_lpc = ICH9_LPC_DEVICE(lpc); 195 lpc_dev = DEVICE(lpc); 196 for (i = 0; i < GSI_NUM_PINS; i++) { 197 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]); 198 } 199 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 200 ICH9_LPC_NB_PIRQS); 201 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 202 isa_bus = ich9_lpc->isa_bus; 203 204 if (kvm_pic_in_kernel()) { 205 i8259 = kvm_i8259_init(isa_bus); 206 } else if (xen_enabled()) { 207 i8259 = xen_interrupt_controller_init(); 208 } else { 209 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 210 } 211 212 for (i = 0; i < ISA_NUM_IRQS; i++) { 213 gsi_state->i8259_irq[i] = i8259[i]; 214 } 215 g_free(i8259); 216 217 if (pcmc->pci_enabled) { 218 ioapic_init_gsi(gsi_state, "q35"); 219 } 220 221 pc_register_ferr_irq(pcms->gsi[13]); 222 223 assert(pcms->vmport != ON_OFF_AUTO__MAX); 224 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 225 pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 226 } 227 228 /* init basic PC hardware */ 229 pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy, 230 (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104); 231 232 /* connect pm stuff to lpc */ 233 ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms)); 234 235 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 236 ahci = pci_create_simple_multifunction(host_bus, 237 PCI_DEVFN(ICH9_SATA1_DEV, 238 ICH9_SATA1_FUNC), 239 true, "ich9-ahci"); 240 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 241 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 242 g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports); 243 ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); 244 ahci_ide_create_devs(ahci, hd); 245 246 if (machine_usb(machine)) { 247 /* Should we create 6 UHCI according to ich9 spec? */ 248 ehci_create_ich9_with_companions(host_bus, 0x1d); 249 } 250 251 /* TODO: Populate SPD eeprom data. */ 252 smbus_eeprom_init(ich9_smb_init(host_bus, 253 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 254 0xb100), 255 8, NULL, 0); 256 257 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 258 259 /* the rest devices to which pci devfn is automatically assigned */ 260 pc_vga_init(isa_bus, host_bus); 261 pc_nic_init(isa_bus, host_bus); 262 if (pcmc->pci_enabled) { 263 pc_pci_device_init(host_bus); 264 } 265 266 if (pcms->acpi_nvdimm_state.is_enabled) { 267 nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io, 268 pcms->fw_cfg, OBJECT(pcms)); 269 } 270 } 271 272 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 273 static void pc_init_##suffix(MachineState *machine) \ 274 { \ 275 void (*compat)(MachineState *m) = (compatfn); \ 276 if (compat) { \ 277 compat(machine); \ 278 } \ 279 pc_q35_init(machine); \ 280 } \ 281 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 282 283 284 static void pc_q35_machine_options(MachineClass *m) 285 { 286 m->family = "pc_q35"; 287 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 288 m->hot_add_cpu = pc_hot_add_cpu; 289 m->units_per_default_bus = 1; 290 m->default_machine_opts = "firmware=bios-256k.bin"; 291 m->default_display = "std"; 292 m->no_floppy = 1; 293 m->has_dynamic_sysbus = true; 294 } 295 296 static void pc_q35_2_8_machine_options(MachineClass *m) 297 { 298 pc_q35_machine_options(m); 299 m->alias = "q35"; 300 } 301 302 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 303 pc_q35_2_8_machine_options); 304 305 static void pc_q35_2_7_machine_options(MachineClass *m) 306 { 307 pc_q35_2_8_machine_options(m); 308 m->alias = NULL; 309 SET_MACHINE_COMPAT(m, PC_COMPAT_2_7); 310 } 311 312 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 313 pc_q35_2_7_machine_options); 314 315 static void pc_q35_2_6_machine_options(MachineClass *m) 316 { 317 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 318 pc_q35_2_7_machine_options(m); 319 pcmc->legacy_cpu_hotplug = true; 320 SET_MACHINE_COMPAT(m, PC_COMPAT_2_6); 321 } 322 323 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 324 pc_q35_2_6_machine_options); 325 326 static void pc_q35_2_5_machine_options(MachineClass *m) 327 { 328 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 329 pc_q35_2_6_machine_options(m); 330 pcmc->save_tsc_khz = false; 331 m->legacy_fw_cfg_order = 1; 332 SET_MACHINE_COMPAT(m, PC_COMPAT_2_5); 333 } 334 335 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 336 pc_q35_2_5_machine_options); 337 338 static void pc_q35_2_4_machine_options(MachineClass *m) 339 { 340 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 341 pc_q35_2_5_machine_options(m); 342 m->hw_version = "2.4.0"; 343 pcmc->broken_reserved_end = true; 344 SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); 345 } 346 347 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 348 pc_q35_2_4_machine_options); 349