1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/ide/pci.h" 43 #include "hw/ide/ahci.h" 44 #include "hw/usb.h" 45 #include "hw/cpu/icc_bus.h" 46 47 /* ICH9 AHCI has 6 ports */ 48 #define MAX_SATA_PORTS 6 49 50 static bool has_pvpanic; 51 static bool has_pci_info = true; 52 53 /* PC hardware initialisation */ 54 static void pc_q35_init(QEMUMachineInitArgs *args) 55 { 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 Q35PCIHost *q35_host; 58 PCIHostState *phb; 59 PCIBus *host_bus; 60 PCIDevice *lpc; 61 BusState *idebus[MAX_SATA_PORTS]; 62 ISADevice *rtc_state; 63 ISADevice *floppy; 64 MemoryRegion *pci_memory; 65 MemoryRegion *rom_memory; 66 MemoryRegion *ram_memory; 67 GSIState *gsi_state; 68 ISABus *isa_bus; 69 int pci_enabled = 1; 70 qemu_irq *cpu_irq; 71 qemu_irq *gsi; 72 qemu_irq *i8259; 73 int i; 74 ICH9LPCState *ich9_lpc; 75 PCIDevice *ahci; 76 DeviceState *icc_bridge; 77 PcGuestInfo *guest_info; 78 79 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 80 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 81 exit(1); 82 } 83 84 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 85 object_property_add_child(qdev_get_machine(), "icc-bridge", 86 OBJECT(icc_bridge), NULL); 87 88 pc_cpus_init(args->cpu_model, icc_bridge); 89 pc_acpi_init("q35-acpi-dsdt.aml"); 90 91 kvmclock_create(); 92 93 if (args->ram_size >= 0xb0000000) { 94 above_4g_mem_size = args->ram_size - 0xb0000000; 95 below_4g_mem_size = 0xb0000000; 96 } else { 97 above_4g_mem_size = 0; 98 below_4g_mem_size = args->ram_size; 99 } 100 101 /* pci enabled */ 102 if (pci_enabled) { 103 pci_memory = g_new(MemoryRegion, 1); 104 memory_region_init(pci_memory, NULL, "pci", INT64_MAX); 105 rom_memory = pci_memory; 106 } else { 107 pci_memory = NULL; 108 rom_memory = get_system_memory(); 109 } 110 111 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 112 guest_info->has_pci_info = has_pci_info; 113 guest_info->isapc_ram_fw = false; 114 115 /* allocate ram and load rom/bios */ 116 if (!xen_enabled()) { 117 pc_memory_init(get_system_memory(), 118 args->kernel_filename, args->kernel_cmdline, 119 args->initrd_filename, 120 below_4g_mem_size, above_4g_mem_size, 121 rom_memory, &ram_memory, guest_info); 122 } 123 124 /* irq lines */ 125 gsi_state = g_malloc0(sizeof(*gsi_state)); 126 if (kvm_irqchip_in_kernel()) { 127 kvm_pc_setup_irq_routing(pci_enabled); 128 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 129 GSI_NUM_PINS); 130 } else { 131 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 132 } 133 134 /* create pci host bus */ 135 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 136 137 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 138 q35_host->mch.ram_memory = ram_memory; 139 q35_host->mch.pci_address_space = pci_memory; 140 q35_host->mch.system_memory = get_system_memory(); 141 q35_host->mch.address_space_io = get_system_io(); 142 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 143 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 144 q35_host->mch.guest_info = guest_info; 145 /* pci */ 146 qdev_init_nofail(DEVICE(q35_host)); 147 phb = PCI_HOST_BRIDGE(q35_host); 148 host_bus = phb->bus; 149 /* create ISA bus */ 150 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 151 ICH9_LPC_FUNC), true, 152 TYPE_ICH9_LPC_DEVICE); 153 ich9_lpc = ICH9_LPC_DEVICE(lpc); 154 ich9_lpc->pic = gsi; 155 ich9_lpc->ioapic = gsi_state->ioapic_irq; 156 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 157 ICH9_LPC_NB_PIRQS); 158 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 159 isa_bus = ich9_lpc->isa_bus; 160 161 /*end early*/ 162 isa_bus_irqs(isa_bus, gsi); 163 164 if (kvm_irqchip_in_kernel()) { 165 i8259 = kvm_i8259_init(isa_bus); 166 } else if (xen_enabled()) { 167 i8259 = xen_interrupt_controller_init(); 168 } else { 169 cpu_irq = pc_allocate_cpu_irq(); 170 i8259 = i8259_init(isa_bus, cpu_irq[0]); 171 } 172 173 for (i = 0; i < ISA_NUM_IRQS; i++) { 174 gsi_state->i8259_irq[i] = i8259[i]; 175 } 176 if (pci_enabled) { 177 ioapic_init_gsi(gsi_state, NULL); 178 } 179 qdev_init_nofail(icc_bridge); 180 181 pc_register_ferr_irq(gsi[13]); 182 183 /* init basic PC hardware */ 184 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 185 186 /* connect pm stuff to lpc */ 187 ich9_lpc_pm_init(lpc); 188 189 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 190 ahci = pci_create_simple_multifunction(host_bus, 191 PCI_DEVFN(ICH9_SATA1_DEV, 192 ICH9_SATA1_FUNC), 193 true, "ich9-ahci"); 194 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 195 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 196 197 if (usb_enabled(false)) { 198 /* Should we create 6 UHCI according to ich9 spec? */ 199 ehci_create_ich9_with_companions(host_bus, 0x1d); 200 } 201 202 /* TODO: Populate SPD eeprom data. */ 203 smbus_eeprom_init(ich9_smb_init(host_bus, 204 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 205 0xb100), 206 8, NULL, 0); 207 208 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, 209 floppy, idebus[0], idebus[1], rtc_state); 210 211 /* the rest devices to which pci devfn is automatically assigned */ 212 pc_vga_init(isa_bus, host_bus); 213 pc_nic_init(isa_bus, host_bus); 214 if (pci_enabled) { 215 pc_pci_device_init(host_bus); 216 } 217 218 if (has_pvpanic) { 219 pvpanic_init(isa_bus); 220 } 221 } 222 223 static void pc_compat_1_6(QEMUMachineInitArgs *args) 224 { 225 has_pci_info = false; 226 rom_file_in_ram = false; 227 } 228 229 static void pc_compat_1_5(QEMUMachineInitArgs *args) 230 { 231 pc_compat_1_6(args); 232 has_pvpanic = true; 233 } 234 235 static void pc_compat_1_4(QEMUMachineInitArgs *args) 236 { 237 pc_compat_1_5(args); 238 has_pvpanic = false; 239 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 240 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 241 } 242 243 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 244 { 245 pc_compat_1_6(args); 246 pc_q35_init(args); 247 } 248 249 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 250 { 251 pc_compat_1_5(args); 252 pc_q35_init(args); 253 } 254 255 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 256 { 257 pc_compat_1_4(args); 258 pc_q35_init(args); 259 } 260 261 #define PC_Q35_MACHINE_OPTIONS \ 262 PC_DEFAULT_MACHINE_OPTIONS, \ 263 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 264 .hot_add_cpu = pc_hot_add_cpu 265 266 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 267 268 static QEMUMachine pc_q35_machine_v1_7 = { 269 PC_Q35_1_7_MACHINE_OPTIONS, 270 .name = "pc-q35-1.7", 271 .alias = "q35", 272 .init = pc_q35_init, 273 }; 274 275 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 276 277 static QEMUMachine pc_q35_machine_v1_6 = { 278 PC_Q35_1_6_MACHINE_OPTIONS, 279 .name = "pc-q35-1.6", 280 .init = pc_q35_init_1_6, 281 .compat_props = (GlobalProperty[]) { 282 PC_COMPAT_1_6, 283 { /* end of list */ } 284 }, 285 }; 286 287 static QEMUMachine pc_q35_machine_v1_5 = { 288 PC_Q35_1_6_MACHINE_OPTIONS, 289 .name = "pc-q35-1.5", 290 .init = pc_q35_init_1_5, 291 .compat_props = (GlobalProperty[]) { 292 PC_COMPAT_1_5, 293 { /* end of list */ } 294 }, 295 }; 296 297 #define PC_Q35_1_4_MACHINE_OPTIONS \ 298 PC_Q35_1_6_MACHINE_OPTIONS, \ 299 .hot_add_cpu = NULL 300 301 static QEMUMachine pc_q35_machine_v1_4 = { 302 PC_Q35_1_4_MACHINE_OPTIONS, 303 .name = "pc-q35-1.4", 304 .init = pc_q35_init_1_4, 305 .compat_props = (GlobalProperty[]) { 306 PC_COMPAT_1_4, 307 { /* end of list */ } 308 }, 309 }; 310 311 static void pc_q35_machine_init(void) 312 { 313 qemu_register_machine(&pc_q35_machine_v1_7); 314 qemu_register_machine(&pc_q35_machine_v1_6); 315 qemu_register_machine(&pc_q35_machine_v1_5); 316 qemu_register_machine(&pc_q35_machine_v1_4); 317 } 318 319 machine_init(pc_q35_machine_init); 320