1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/rtc/mc146818rtc.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "hw/pci/pcie_port.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/i386/x86.h" 42 #include "hw/i386/pc.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/i386/amd_iommu.h" 45 #include "hw/i386/intel_iommu.h" 46 #include "hw/display/ramfb.h" 47 #include "hw/firmware/smbios.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci.h" 50 #include "hw/usb.h" 51 #include "qapi/error.h" 52 #include "qemu/error-report.h" 53 #include "sysemu/numa.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 #include "hw/mem/nvdimm.h" 56 #include "hw/i386/acpi-build.h" 57 58 /* ICH9 AHCI has 6 ports */ 59 #define MAX_SATA_PORTS 6 60 61 struct ehci_companions { 62 const char *name; 63 int func; 64 int port; 65 }; 66 67 static const struct ehci_companions ich9_1d[] = { 68 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 69 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 70 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 71 }; 72 73 static const struct ehci_companions ich9_1a[] = { 74 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 75 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 76 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 77 }; 78 79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 80 { 81 const struct ehci_companions *comp; 82 PCIDevice *ehci, *uhci; 83 BusState *usbbus; 84 const char *name; 85 int i; 86 87 switch (slot) { 88 case 0x1d: 89 name = "ich9-usb-ehci1"; 90 comp = ich9_1d; 91 break; 92 case 0x1a: 93 name = "ich9-usb-ehci2"; 94 comp = ich9_1a; 95 break; 96 default: 97 return -1; 98 } 99 100 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 101 pci_realize_and_unref(ehci, bus, &error_fatal); 102 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 103 104 for (i = 0; i < 3; i++) { 105 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 106 comp[i].name); 107 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 108 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 109 pci_realize_and_unref(uhci, bus, &error_fatal); 110 } 111 return 0; 112 } 113 114 /* PC hardware initialisation */ 115 static void pc_q35_init(MachineState *machine) 116 { 117 PCMachineState *pcms = PC_MACHINE(machine); 118 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 119 X86MachineState *x86ms = X86_MACHINE(machine); 120 Q35PCIHost *q35_host; 121 PCIHostState *phb; 122 PCIBus *host_bus; 123 PCIDevice *lpc; 124 DeviceState *lpc_dev; 125 BusState *idebus[MAX_SATA_PORTS]; 126 ISADevice *rtc_state; 127 MemoryRegion *system_io = get_system_io(); 128 MemoryRegion *pci_memory; 129 MemoryRegion *rom_memory; 130 MemoryRegion *ram_memory; 131 GSIState *gsi_state; 132 ISABus *isa_bus; 133 int i; 134 ICH9LPCState *ich9_lpc; 135 PCIDevice *ahci; 136 ram_addr_t lowmem; 137 DriveInfo *hd[MAX_SATA_PORTS]; 138 MachineClass *mc = MACHINE_GET_CLASS(machine); 139 bool acpi_pcihp; 140 bool keep_pci_slot_hpc; 141 142 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 143 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 144 * also known as MMCFG). 145 * If it doesn't, we need to split it in chunks below and above 4G. 146 * In any case, try to make sure that guest addresses aligned at 147 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 148 */ 149 if (machine->ram_size >= 0xb0000000) { 150 lowmem = 0x80000000; 151 } else { 152 lowmem = 0xb0000000; 153 } 154 155 /* Handle the machine opt max-ram-below-4g. It is basically doing 156 * min(qemu limit, user limit). 157 */ 158 if (!pcms->max_ram_below_4g) { 159 pcms->max_ram_below_4g = 4 * GiB; 160 } 161 if (lowmem > pcms->max_ram_below_4g) { 162 lowmem = pcms->max_ram_below_4g; 163 if (machine->ram_size - lowmem > lowmem && 164 lowmem & (1 * GiB - 1)) { 165 warn_report("There is possibly poor performance as the ram size " 166 " (0x%" PRIx64 ") is more then twice the size of" 167 " max-ram-below-4g (%"PRIu64") and" 168 " max-ram-below-4g is not a multiple of 1G.", 169 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 170 } 171 } 172 173 if (machine->ram_size >= lowmem) { 174 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 175 x86ms->below_4g_mem_size = lowmem; 176 } else { 177 x86ms->above_4g_mem_size = 0; 178 x86ms->below_4g_mem_size = machine->ram_size; 179 } 180 181 pc_machine_init_sgx_epc(pcms); 182 x86_cpus_init(x86ms, pcmc->default_cpu_version); 183 184 kvmclock_create(pcmc->kvmclock_create_always); 185 186 /* pci enabled */ 187 if (pcmc->pci_enabled) { 188 pci_memory = g_new(MemoryRegion, 1); 189 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 190 rom_memory = pci_memory; 191 } else { 192 pci_memory = NULL; 193 rom_memory = get_system_memory(); 194 } 195 196 pc_guest_info_init(pcms); 197 198 if (pcmc->smbios_defaults) { 199 /* These values are guest ABI, do not change */ 200 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 201 mc->name, pcmc->smbios_legacy_mode, 202 pcmc->smbios_uuid_encoded, 203 pcms->smbios_entry_point_type); 204 } 205 206 /* allocate ram and load rom/bios */ 207 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); 208 209 /* create pci host bus */ 210 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 211 212 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 213 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 214 OBJECT(ram_memory), NULL); 215 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 216 OBJECT(pci_memory), NULL); 217 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 218 OBJECT(get_system_memory()), NULL); 219 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 220 OBJECT(system_io), NULL); 221 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 222 x86ms->below_4g_mem_size, NULL); 223 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 224 x86ms->above_4g_mem_size, NULL); 225 /* pci */ 226 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 227 phb = PCI_HOST_BRIDGE(q35_host); 228 host_bus = phb->bus; 229 /* create ISA bus */ 230 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 231 ICH9_LPC_FUNC), true, 232 TYPE_ICH9_LPC_DEVICE); 233 234 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 235 TYPE_HOTPLUG_HANDLER, 236 (Object **)&x86ms->acpi_dev, 237 object_property_allow_set_link, 238 OBJ_PROP_LINK_STRONG); 239 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 240 OBJECT(lpc), &error_abort); 241 242 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 243 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 244 NULL); 245 246 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 247 "x-keep-pci-slot-hpc", 248 NULL); 249 250 if (!keep_pci_slot_hpc && acpi_pcihp) { 251 object_register_sugar_prop(TYPE_PCIE_SLOT, "x-native-hotplug", 252 "false", true); 253 } 254 255 /* irq lines */ 256 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 257 258 ich9_lpc = ICH9_LPC_DEVICE(lpc); 259 lpc_dev = DEVICE(lpc); 260 for (i = 0; i < GSI_NUM_PINS; i++) { 261 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 262 } 263 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 264 ICH9_LPC_NB_PIRQS); 265 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 266 isa_bus = ich9_lpc->isa_bus; 267 268 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 269 270 if (pcmc->pci_enabled) { 271 ioapic_init_gsi(gsi_state, "q35"); 272 } 273 274 if (tcg_enabled()) { 275 x86_register_ferr_irq(x86ms->gsi[13]); 276 } 277 278 assert(pcms->vmport != ON_OFF_AUTO__MAX); 279 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 280 pcms->vmport = ON_OFF_AUTO_ON; 281 } 282 283 /* init basic PC hardware */ 284 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 285 0xff0104); 286 287 /* connect pm stuff to lpc */ 288 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 289 290 if (pcms->sata_enabled) { 291 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 292 ahci = pci_create_simple_multifunction(host_bus, 293 PCI_DEVFN(ICH9_SATA1_DEV, 294 ICH9_SATA1_FUNC), 295 true, "ich9-ahci"); 296 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 297 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 298 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 299 ide_drive_get(hd, ahci_get_num_ports(ahci)); 300 ahci_ide_create_devs(ahci, hd); 301 } else { 302 idebus[0] = idebus[1] = NULL; 303 } 304 305 if (machine_usb(machine)) { 306 /* Should we create 6 UHCI according to ich9 spec? */ 307 ehci_create_ich9_with_companions(host_bus, 0x1d); 308 } 309 310 if (pcms->smbus_enabled) { 311 /* TODO: Populate SPD eeprom data. */ 312 pcms->smbus = ich9_smb_init(host_bus, 313 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 314 0xb100); 315 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 316 } 317 318 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 319 320 /* the rest devices to which pci devfn is automatically assigned */ 321 pc_vga_init(isa_bus, host_bus); 322 pc_nic_init(pcmc, isa_bus, host_bus); 323 324 if (machine->nvdimms_state->is_enabled) { 325 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 326 x86_nvdimm_acpi_dsmio, 327 x86ms->fw_cfg, OBJECT(pcms)); 328 } 329 } 330 331 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 332 static void pc_init_##suffix(MachineState *machine) \ 333 { \ 334 void (*compat)(MachineState *m) = (compatfn); \ 335 if (compat) { \ 336 compat(machine); \ 337 } \ 338 pc_q35_init(machine); \ 339 } \ 340 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 341 342 343 static void pc_q35_machine_options(MachineClass *m) 344 { 345 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 346 pcmc->default_nic_model = "e1000e"; 347 pcmc->pci_root_uid = 0; 348 349 m->family = "pc_q35"; 350 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 351 m->units_per_default_bus = 1; 352 m->default_machine_opts = "firmware=bios-256k.bin"; 353 m->default_display = "std"; 354 m->default_kernel_irqchip_split = false; 355 m->no_floppy = 1; 356 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 357 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 358 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 359 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 360 m->max_cpus = 288; 361 } 362 363 static void pc_q35_7_0_machine_options(MachineClass *m) 364 { 365 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 366 pc_q35_machine_options(m); 367 m->alias = "q35"; 368 pcmc->default_cpu_version = 1; 369 } 370 371 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 372 pc_q35_7_0_machine_options); 373 374 static void pc_q35_6_2_machine_options(MachineClass *m) 375 { 376 pc_q35_7_0_machine_options(m); 377 m->alias = NULL; 378 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 379 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 380 } 381 382 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 383 pc_q35_6_2_machine_options); 384 385 static void pc_q35_6_1_machine_options(MachineClass *m) 386 { 387 pc_q35_6_2_machine_options(m); 388 m->alias = NULL; 389 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 390 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 391 m->smp_props.prefer_sockets = true; 392 } 393 394 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 395 pc_q35_6_1_machine_options); 396 397 static void pc_q35_6_0_machine_options(MachineClass *m) 398 { 399 pc_q35_6_1_machine_options(m); 400 m->alias = NULL; 401 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 402 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 403 } 404 405 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 406 pc_q35_6_0_machine_options); 407 408 static void pc_q35_5_2_machine_options(MachineClass *m) 409 { 410 pc_q35_6_0_machine_options(m); 411 m->alias = NULL; 412 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 413 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 414 } 415 416 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 417 pc_q35_5_2_machine_options); 418 419 static void pc_q35_5_1_machine_options(MachineClass *m) 420 { 421 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 422 423 pc_q35_5_2_machine_options(m); 424 m->alias = NULL; 425 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 426 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 427 pcmc->kvmclock_create_always = false; 428 pcmc->pci_root_uid = 1; 429 } 430 431 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 432 pc_q35_5_1_machine_options); 433 434 static void pc_q35_5_0_machine_options(MachineClass *m) 435 { 436 pc_q35_5_1_machine_options(m); 437 m->alias = NULL; 438 m->numa_mem_supported = true; 439 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 440 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 441 m->auto_enable_numa_with_memdev = false; 442 } 443 444 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 445 pc_q35_5_0_machine_options); 446 447 static void pc_q35_4_2_machine_options(MachineClass *m) 448 { 449 pc_q35_5_0_machine_options(m); 450 m->alias = NULL; 451 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 452 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 453 } 454 455 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 456 pc_q35_4_2_machine_options); 457 458 static void pc_q35_4_1_machine_options(MachineClass *m) 459 { 460 pc_q35_4_2_machine_options(m); 461 m->alias = NULL; 462 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 463 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 464 } 465 466 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 467 pc_q35_4_1_machine_options); 468 469 static void pc_q35_4_0_1_machine_options(MachineClass *m) 470 { 471 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 472 pc_q35_4_1_machine_options(m); 473 m->alias = NULL; 474 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 475 /* 476 * This is the default machine for the 4.0-stable branch. It is basically 477 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 478 * 4.0 compat props. 479 */ 480 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 481 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 482 } 483 484 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 485 pc_q35_4_0_1_machine_options); 486 487 static void pc_q35_4_0_machine_options(MachineClass *m) 488 { 489 pc_q35_4_0_1_machine_options(m); 490 m->default_kernel_irqchip_split = true; 491 m->alias = NULL; 492 /* Compat props are applied by the 4.0.1 machine */ 493 } 494 495 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 496 pc_q35_4_0_machine_options); 497 498 static void pc_q35_3_1_machine_options(MachineClass *m) 499 { 500 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 501 502 pc_q35_4_0_machine_options(m); 503 m->default_kernel_irqchip_split = false; 504 pcmc->do_not_add_smb_acpi = true; 505 m->smbus_no_migration_support = true; 506 m->alias = NULL; 507 pcmc->pvh_enabled = false; 508 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 509 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 510 } 511 512 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 513 pc_q35_3_1_machine_options); 514 515 static void pc_q35_3_0_machine_options(MachineClass *m) 516 { 517 pc_q35_3_1_machine_options(m); 518 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 519 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 520 } 521 522 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 523 pc_q35_3_0_machine_options); 524 525 static void pc_q35_2_12_machine_options(MachineClass *m) 526 { 527 pc_q35_3_0_machine_options(m); 528 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 529 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 530 } 531 532 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 533 pc_q35_2_12_machine_options); 534 535 static void pc_q35_2_11_machine_options(MachineClass *m) 536 { 537 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 538 539 pc_q35_2_12_machine_options(m); 540 pcmc->default_nic_model = "e1000"; 541 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 542 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 543 } 544 545 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 546 pc_q35_2_11_machine_options); 547 548 static void pc_q35_2_10_machine_options(MachineClass *m) 549 { 550 pc_q35_2_11_machine_options(m); 551 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 552 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 553 m->auto_enable_numa_with_memhp = false; 554 } 555 556 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 557 pc_q35_2_10_machine_options); 558 559 static void pc_q35_2_9_machine_options(MachineClass *m) 560 { 561 pc_q35_2_10_machine_options(m); 562 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 563 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 564 } 565 566 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 567 pc_q35_2_9_machine_options); 568 569 static void pc_q35_2_8_machine_options(MachineClass *m) 570 { 571 pc_q35_2_9_machine_options(m); 572 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 573 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 574 } 575 576 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 577 pc_q35_2_8_machine_options); 578 579 static void pc_q35_2_7_machine_options(MachineClass *m) 580 { 581 pc_q35_2_8_machine_options(m); 582 m->max_cpus = 255; 583 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 584 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 585 } 586 587 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 588 pc_q35_2_7_machine_options); 589 590 static void pc_q35_2_6_machine_options(MachineClass *m) 591 { 592 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 593 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 594 595 pc_q35_2_7_machine_options(m); 596 pcmc->legacy_cpu_hotplug = true; 597 x86mc->fwcfg_dma_enabled = false; 598 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 599 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 600 } 601 602 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 603 pc_q35_2_6_machine_options); 604 605 static void pc_q35_2_5_machine_options(MachineClass *m) 606 { 607 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 608 609 pc_q35_2_6_machine_options(m); 610 x86mc->save_tsc_khz = false; 611 m->legacy_fw_cfg_order = 1; 612 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 613 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 614 } 615 616 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 617 pc_q35_2_5_machine_options); 618 619 static void pc_q35_2_4_machine_options(MachineClass *m) 620 { 621 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 622 623 pc_q35_2_5_machine_options(m); 624 m->hw_version = "2.4.0"; 625 pcmc->broken_reserved_end = true; 626 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 627 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 628 } 629 630 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 631 pc_q35_2_4_machine_options); 632