1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/rtc/mc146818rtc.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "hw/pci/pcie_port.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/i386/x86.h" 42 #include "hw/i386/pc.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/i386/amd_iommu.h" 45 #include "hw/i386/intel_iommu.h" 46 #include "hw/display/ramfb.h" 47 #include "hw/firmware/smbios.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci.h" 50 #include "hw/usb.h" 51 #include "qapi/error.h" 52 #include "qemu/error-report.h" 53 #include "sysemu/numa.h" 54 #include "hw/hyperv/vmbus-bridge.h" 55 #include "hw/mem/nvdimm.h" 56 #include "hw/i386/acpi-build.h" 57 58 /* ICH9 AHCI has 6 ports */ 59 #define MAX_SATA_PORTS 6 60 61 struct ehci_companions { 62 const char *name; 63 int func; 64 int port; 65 }; 66 67 static const struct ehci_companions ich9_1d[] = { 68 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 69 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 70 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 71 }; 72 73 static const struct ehci_companions ich9_1a[] = { 74 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 75 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 76 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 77 }; 78 79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 80 { 81 const struct ehci_companions *comp; 82 PCIDevice *ehci, *uhci; 83 BusState *usbbus; 84 const char *name; 85 int i; 86 87 switch (slot) { 88 case 0x1d: 89 name = "ich9-usb-ehci1"; 90 comp = ich9_1d; 91 break; 92 case 0x1a: 93 name = "ich9-usb-ehci2"; 94 comp = ich9_1a; 95 break; 96 default: 97 return -1; 98 } 99 100 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 101 pci_realize_and_unref(ehci, bus, &error_fatal); 102 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 103 104 for (i = 0; i < 3; i++) { 105 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 106 comp[i].name); 107 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 108 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 109 pci_realize_and_unref(uhci, bus, &error_fatal); 110 } 111 return 0; 112 } 113 114 /* PC hardware initialisation */ 115 static void pc_q35_init(MachineState *machine) 116 { 117 PCMachineState *pcms = PC_MACHINE(machine); 118 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 119 X86MachineState *x86ms = X86_MACHINE(machine); 120 Q35PCIHost *q35_host; 121 PCIHostState *phb; 122 PCIBus *host_bus; 123 PCIDevice *lpc; 124 DeviceState *lpc_dev; 125 BusState *idebus[MAX_SATA_PORTS]; 126 ISADevice *rtc_state; 127 MemoryRegion *system_io = get_system_io(); 128 MemoryRegion *pci_memory; 129 MemoryRegion *rom_memory; 130 MemoryRegion *ram_memory; 131 GSIState *gsi_state; 132 ISABus *isa_bus; 133 int i; 134 ICH9LPCState *ich9_lpc; 135 PCIDevice *ahci; 136 ram_addr_t lowmem; 137 DriveInfo *hd[MAX_SATA_PORTS]; 138 MachineClass *mc = MACHINE_GET_CLASS(machine); 139 bool acpi_pcihp; 140 bool keep_pci_slot_hpc; 141 uint64_t pci_hole64_size = 0; 142 143 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 144 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 145 * also known as MMCFG). 146 * If it doesn't, we need to split it in chunks below and above 4G. 147 * In any case, try to make sure that guest addresses aligned at 148 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 149 */ 150 if (machine->ram_size >= 0xb0000000) { 151 lowmem = 0x80000000; 152 } else { 153 lowmem = 0xb0000000; 154 } 155 156 /* Handle the machine opt max-ram-below-4g. It is basically doing 157 * min(qemu limit, user limit). 158 */ 159 if (!pcms->max_ram_below_4g) { 160 pcms->max_ram_below_4g = 4 * GiB; 161 } 162 if (lowmem > pcms->max_ram_below_4g) { 163 lowmem = pcms->max_ram_below_4g; 164 if (machine->ram_size - lowmem > lowmem && 165 lowmem & (1 * GiB - 1)) { 166 warn_report("There is possibly poor performance as the ram size " 167 " (0x%" PRIx64 ") is more then twice the size of" 168 " max-ram-below-4g (%"PRIu64") and" 169 " max-ram-below-4g is not a multiple of 1G.", 170 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 171 } 172 } 173 174 if (machine->ram_size >= lowmem) { 175 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 176 x86ms->below_4g_mem_size = lowmem; 177 } else { 178 x86ms->above_4g_mem_size = 0; 179 x86ms->below_4g_mem_size = machine->ram_size; 180 } 181 182 pc_machine_init_sgx_epc(pcms); 183 x86_cpus_init(x86ms, pcmc->default_cpu_version); 184 185 kvmclock_create(pcmc->kvmclock_create_always); 186 187 /* pci enabled */ 188 if (pcmc->pci_enabled) { 189 pci_memory = g_new(MemoryRegion, 1); 190 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 191 rom_memory = pci_memory; 192 } else { 193 pci_memory = NULL; 194 rom_memory = get_system_memory(); 195 } 196 197 pc_guest_info_init(pcms); 198 199 if (pcmc->smbios_defaults) { 200 /* These values are guest ABI, do not change */ 201 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 202 mc->name, pcmc->smbios_legacy_mode, 203 pcmc->smbios_uuid_encoded, 204 pcms->smbios_entry_point_type); 205 } 206 207 /* create pci host bus */ 208 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 209 210 if (pcmc->pci_enabled) { 211 pci_hole64_size = object_property_get_uint(OBJECT(q35_host), 212 PCI_HOST_PROP_PCI_HOLE64_SIZE, 213 &error_abort); 214 } 215 216 /* allocate ram and load rom/bios */ 217 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, 218 pci_hole64_size); 219 220 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 221 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 222 OBJECT(ram_memory), NULL); 223 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 224 OBJECT(pci_memory), NULL); 225 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 226 OBJECT(get_system_memory()), NULL); 227 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 228 OBJECT(system_io), NULL); 229 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 230 x86ms->below_4g_mem_size, NULL); 231 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 232 x86ms->above_4g_mem_size, NULL); 233 /* pci */ 234 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 235 phb = PCI_HOST_BRIDGE(q35_host); 236 host_bus = phb->bus; 237 /* create ISA bus */ 238 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 239 ICH9_LPC_FUNC), true, 240 TYPE_ICH9_LPC_DEVICE); 241 242 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 243 TYPE_HOTPLUG_HANDLER, 244 (Object **)&x86ms->acpi_dev, 245 object_property_allow_set_link, 246 OBJ_PROP_LINK_STRONG); 247 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 248 OBJECT(lpc), &error_abort); 249 250 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 251 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 252 NULL); 253 254 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 255 "x-keep-pci-slot-hpc", 256 NULL); 257 258 if (!keep_pci_slot_hpc && acpi_pcihp) { 259 object_register_sugar_prop(TYPE_PCIE_SLOT, "x-native-hotplug", 260 "false", true); 261 } 262 263 /* irq lines */ 264 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 265 266 ich9_lpc = ICH9_LPC_DEVICE(lpc); 267 lpc_dev = DEVICE(lpc); 268 for (i = 0; i < GSI_NUM_PINS; i++) { 269 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 270 } 271 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 272 ICH9_LPC_NB_PIRQS); 273 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 274 isa_bus = ich9_lpc->isa_bus; 275 276 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 277 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 278 } 279 280 if (pcmc->pci_enabled) { 281 ioapic_init_gsi(gsi_state, "q35"); 282 } 283 284 if (tcg_enabled()) { 285 x86_register_ferr_irq(x86ms->gsi[13]); 286 } 287 288 assert(pcms->vmport != ON_OFF_AUTO__MAX); 289 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 290 pcms->vmport = ON_OFF_AUTO_ON; 291 } 292 293 /* init basic PC hardware */ 294 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 295 0xff0104); 296 297 /* connect pm stuff to lpc */ 298 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 299 300 if (pcms->sata_enabled) { 301 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 302 ahci = pci_create_simple_multifunction(host_bus, 303 PCI_DEVFN(ICH9_SATA1_DEV, 304 ICH9_SATA1_FUNC), 305 true, "ich9-ahci"); 306 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 307 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 308 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 309 ide_drive_get(hd, ahci_get_num_ports(ahci)); 310 ahci_ide_create_devs(ahci, hd); 311 } else { 312 idebus[0] = idebus[1] = NULL; 313 } 314 315 if (machine_usb(machine)) { 316 /* Should we create 6 UHCI according to ich9 spec? */ 317 ehci_create_ich9_with_companions(host_bus, 0x1d); 318 } 319 320 if (pcms->smbus_enabled) { 321 /* TODO: Populate SPD eeprom data. */ 322 pcms->smbus = ich9_smb_init(host_bus, 323 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 324 0xb100); 325 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 326 } 327 328 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 329 330 /* the rest devices to which pci devfn is automatically assigned */ 331 pc_vga_init(isa_bus, host_bus); 332 pc_nic_init(pcmc, isa_bus, host_bus); 333 334 if (machine->nvdimms_state->is_enabled) { 335 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 336 x86_nvdimm_acpi_dsmio, 337 x86ms->fw_cfg, OBJECT(pcms)); 338 } 339 } 340 341 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 342 static void pc_init_##suffix(MachineState *machine) \ 343 { \ 344 void (*compat)(MachineState *m) = (compatfn); \ 345 if (compat) { \ 346 compat(machine); \ 347 } \ 348 pc_q35_init(machine); \ 349 } \ 350 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 351 352 353 static void pc_q35_machine_options(MachineClass *m) 354 { 355 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 356 pcmc->default_nic_model = "e1000e"; 357 pcmc->pci_root_uid = 0; 358 359 m->family = "pc_q35"; 360 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 361 m->units_per_default_bus = 1; 362 m->default_machine_opts = "firmware=bios-256k.bin"; 363 m->default_display = "std"; 364 m->default_kernel_irqchip_split = false; 365 m->no_floppy = 1; 366 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 367 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 368 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 369 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 370 m->max_cpus = 288; 371 } 372 373 static void pc_q35_7_1_machine_options(MachineClass *m) 374 { 375 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 376 pc_q35_machine_options(m); 377 m->alias = "q35"; 378 pcmc->default_cpu_version = 1; 379 } 380 381 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 382 pc_q35_7_1_machine_options); 383 384 static void pc_q35_7_0_machine_options(MachineClass *m) 385 { 386 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 387 pc_q35_7_1_machine_options(m); 388 m->alias = NULL; 389 pcmc->legacy_no_rng_seed = true; 390 pcmc->enforce_amd_1tb_hole = false; 391 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 392 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 393 } 394 395 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 396 pc_q35_7_0_machine_options); 397 398 static void pc_q35_6_2_machine_options(MachineClass *m) 399 { 400 pc_q35_7_0_machine_options(m); 401 m->alias = NULL; 402 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 403 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 404 } 405 406 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 407 pc_q35_6_2_machine_options); 408 409 static void pc_q35_6_1_machine_options(MachineClass *m) 410 { 411 pc_q35_6_2_machine_options(m); 412 m->alias = NULL; 413 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 414 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 415 m->smp_props.prefer_sockets = true; 416 } 417 418 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 419 pc_q35_6_1_machine_options); 420 421 static void pc_q35_6_0_machine_options(MachineClass *m) 422 { 423 pc_q35_6_1_machine_options(m); 424 m->alias = NULL; 425 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 426 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 427 } 428 429 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 430 pc_q35_6_0_machine_options); 431 432 static void pc_q35_5_2_machine_options(MachineClass *m) 433 { 434 pc_q35_6_0_machine_options(m); 435 m->alias = NULL; 436 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 437 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 438 } 439 440 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 441 pc_q35_5_2_machine_options); 442 443 static void pc_q35_5_1_machine_options(MachineClass *m) 444 { 445 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 446 447 pc_q35_5_2_machine_options(m); 448 m->alias = NULL; 449 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 450 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 451 pcmc->kvmclock_create_always = false; 452 pcmc->pci_root_uid = 1; 453 } 454 455 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 456 pc_q35_5_1_machine_options); 457 458 static void pc_q35_5_0_machine_options(MachineClass *m) 459 { 460 pc_q35_5_1_machine_options(m); 461 m->alias = NULL; 462 m->numa_mem_supported = true; 463 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 464 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 465 m->auto_enable_numa_with_memdev = false; 466 } 467 468 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 469 pc_q35_5_0_machine_options); 470 471 static void pc_q35_4_2_machine_options(MachineClass *m) 472 { 473 pc_q35_5_0_machine_options(m); 474 m->alias = NULL; 475 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 476 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 477 } 478 479 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 480 pc_q35_4_2_machine_options); 481 482 static void pc_q35_4_1_machine_options(MachineClass *m) 483 { 484 pc_q35_4_2_machine_options(m); 485 m->alias = NULL; 486 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 487 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 488 } 489 490 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 491 pc_q35_4_1_machine_options); 492 493 static void pc_q35_4_0_1_machine_options(MachineClass *m) 494 { 495 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 496 pc_q35_4_1_machine_options(m); 497 m->alias = NULL; 498 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 499 /* 500 * This is the default machine for the 4.0-stable branch. It is basically 501 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 502 * 4.0 compat props. 503 */ 504 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 505 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 506 } 507 508 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 509 pc_q35_4_0_1_machine_options); 510 511 static void pc_q35_4_0_machine_options(MachineClass *m) 512 { 513 pc_q35_4_0_1_machine_options(m); 514 m->default_kernel_irqchip_split = true; 515 m->alias = NULL; 516 /* Compat props are applied by the 4.0.1 machine */ 517 } 518 519 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 520 pc_q35_4_0_machine_options); 521 522 static void pc_q35_3_1_machine_options(MachineClass *m) 523 { 524 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 525 526 pc_q35_4_0_machine_options(m); 527 m->default_kernel_irqchip_split = false; 528 m->smbus_no_migration_support = true; 529 m->alias = NULL; 530 pcmc->pvh_enabled = false; 531 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 532 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 533 } 534 535 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 536 pc_q35_3_1_machine_options); 537 538 static void pc_q35_3_0_machine_options(MachineClass *m) 539 { 540 pc_q35_3_1_machine_options(m); 541 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 542 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 543 } 544 545 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 546 pc_q35_3_0_machine_options); 547 548 static void pc_q35_2_12_machine_options(MachineClass *m) 549 { 550 pc_q35_3_0_machine_options(m); 551 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 552 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 553 } 554 555 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 556 pc_q35_2_12_machine_options); 557 558 static void pc_q35_2_11_machine_options(MachineClass *m) 559 { 560 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 561 562 pc_q35_2_12_machine_options(m); 563 pcmc->default_nic_model = "e1000"; 564 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 565 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 566 } 567 568 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 569 pc_q35_2_11_machine_options); 570 571 static void pc_q35_2_10_machine_options(MachineClass *m) 572 { 573 pc_q35_2_11_machine_options(m); 574 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 575 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 576 m->auto_enable_numa_with_memhp = false; 577 } 578 579 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 580 pc_q35_2_10_machine_options); 581 582 static void pc_q35_2_9_machine_options(MachineClass *m) 583 { 584 pc_q35_2_10_machine_options(m); 585 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 586 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 587 } 588 589 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 590 pc_q35_2_9_machine_options); 591 592 static void pc_q35_2_8_machine_options(MachineClass *m) 593 { 594 pc_q35_2_9_machine_options(m); 595 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 596 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 597 } 598 599 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 600 pc_q35_2_8_machine_options); 601 602 static void pc_q35_2_7_machine_options(MachineClass *m) 603 { 604 pc_q35_2_8_machine_options(m); 605 m->max_cpus = 255; 606 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 607 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 608 } 609 610 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 611 pc_q35_2_7_machine_options); 612 613 static void pc_q35_2_6_machine_options(MachineClass *m) 614 { 615 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 616 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 617 618 pc_q35_2_7_machine_options(m); 619 pcmc->legacy_cpu_hotplug = true; 620 x86mc->fwcfg_dma_enabled = false; 621 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 622 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 623 } 624 625 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 626 pc_q35_2_6_machine_options); 627 628 static void pc_q35_2_5_machine_options(MachineClass *m) 629 { 630 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 631 632 pc_q35_2_6_machine_options(m); 633 x86mc->save_tsc_khz = false; 634 m->legacy_fw_cfg_order = 1; 635 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 636 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 637 } 638 639 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 640 pc_q35_2_5_machine_options); 641 642 static void pc_q35_2_4_machine_options(MachineClass *m) 643 { 644 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 645 646 pc_q35_2_5_machine_options(m); 647 m->hw_version = "2.4.0"; 648 pcmc->broken_reserved_end = true; 649 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 650 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 651 } 652 653 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 654 pc_q35_2_4_machine_options); 655