1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 48 /* ICH9 AHCI has 6 ports */ 49 #define MAX_SATA_PORTS 6 50 51 static bool has_pci_info; 52 static bool has_acpi_build = true; 53 static bool smbios_defaults = true; 54 static bool smbios_legacy_mode; 55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 56 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 57 * pages in the host. 58 */ 59 static bool gigabyte_align = true; 60 static bool has_reserved_memory = true; 61 62 /* PC hardware initialisation */ 63 static void pc_q35_init(MachineState *machine) 64 { 65 ram_addr_t below_4g_mem_size, above_4g_mem_size; 66 Q35PCIHost *q35_host; 67 PCIHostState *phb; 68 PCIBus *host_bus; 69 PCIDevice *lpc; 70 BusState *idebus[MAX_SATA_PORTS]; 71 ISADevice *rtc_state; 72 ISADevice *floppy; 73 MemoryRegion *pci_memory; 74 MemoryRegion *rom_memory; 75 MemoryRegion *ram_memory; 76 GSIState *gsi_state; 77 ISABus *isa_bus; 78 int pci_enabled = 1; 79 qemu_irq *cpu_irq; 80 qemu_irq *gsi; 81 qemu_irq *i8259; 82 int i; 83 ICH9LPCState *ich9_lpc; 84 PCIDevice *ahci; 85 DeviceState *icc_bridge; 86 PcGuestInfo *guest_info; 87 88 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 89 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 90 exit(1); 91 } 92 93 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 94 object_property_add_child(qdev_get_machine(), "icc-bridge", 95 OBJECT(icc_bridge), NULL); 96 97 pc_cpus_init(machine->cpu_model, icc_bridge); 98 pc_acpi_init("q35-acpi-dsdt.aml"); 99 100 kvmclock_create(); 101 102 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 103 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 104 * also known as MMCFG). 105 * If it doesn't, we need to split it in chunks below and above 4G. 106 * In any case, try to make sure that guest addresses aligned at 107 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 108 * For old machine types, use whatever split we used historically to avoid 109 * breaking migration. 110 */ 111 if (machine->ram_size >= 0xb0000000) { 112 ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 113 above_4g_mem_size = machine->ram_size - lowmem; 114 below_4g_mem_size = lowmem; 115 } else { 116 above_4g_mem_size = 0; 117 below_4g_mem_size = machine->ram_size; 118 } 119 120 /* pci enabled */ 121 if (pci_enabled) { 122 pci_memory = g_new(MemoryRegion, 1); 123 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 124 rom_memory = pci_memory; 125 } else { 126 pci_memory = NULL; 127 rom_memory = get_system_memory(); 128 } 129 130 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 131 guest_info->has_pci_info = has_pci_info; 132 guest_info->isapc_ram_fw = false; 133 guest_info->has_acpi_build = has_acpi_build; 134 guest_info->has_reserved_memory = has_reserved_memory; 135 136 if (smbios_defaults) { 137 MachineClass *mc = MACHINE_GET_CLASS(machine); 138 /* These values are guest ABI, do not change */ 139 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 140 mc->name, smbios_legacy_mode); 141 } 142 143 /* allocate ram and load rom/bios */ 144 if (!xen_enabled()) { 145 pc_memory_init(get_system_memory(), 146 machine->kernel_filename, machine->kernel_cmdline, 147 machine->initrd_filename, 148 below_4g_mem_size, above_4g_mem_size, 149 rom_memory, &ram_memory, guest_info); 150 } 151 152 /* irq lines */ 153 gsi_state = g_malloc0(sizeof(*gsi_state)); 154 if (kvm_irqchip_in_kernel()) { 155 kvm_pc_setup_irq_routing(pci_enabled); 156 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 157 GSI_NUM_PINS); 158 } else { 159 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 160 } 161 162 /* create pci host bus */ 163 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 164 165 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 166 q35_host->mch.ram_memory = ram_memory; 167 q35_host->mch.pci_address_space = pci_memory; 168 q35_host->mch.system_memory = get_system_memory(); 169 q35_host->mch.address_space_io = get_system_io(); 170 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 171 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 172 q35_host->mch.guest_info = guest_info; 173 /* pci */ 174 qdev_init_nofail(DEVICE(q35_host)); 175 phb = PCI_HOST_BRIDGE(q35_host); 176 host_bus = phb->bus; 177 /* create ISA bus */ 178 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 179 ICH9_LPC_FUNC), true, 180 TYPE_ICH9_LPC_DEVICE); 181 ich9_lpc = ICH9_LPC_DEVICE(lpc); 182 ich9_lpc->pic = gsi; 183 ich9_lpc->ioapic = gsi_state->ioapic_irq; 184 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 185 ICH9_LPC_NB_PIRQS); 186 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 187 isa_bus = ich9_lpc->isa_bus; 188 189 /*end early*/ 190 isa_bus_irqs(isa_bus, gsi); 191 192 if (kvm_irqchip_in_kernel()) { 193 i8259 = kvm_i8259_init(isa_bus); 194 } else if (xen_enabled()) { 195 i8259 = xen_interrupt_controller_init(); 196 } else { 197 cpu_irq = pc_allocate_cpu_irq(); 198 i8259 = i8259_init(isa_bus, cpu_irq[0]); 199 } 200 201 for (i = 0; i < ISA_NUM_IRQS; i++) { 202 gsi_state->i8259_irq[i] = i8259[i]; 203 } 204 if (pci_enabled) { 205 ioapic_init_gsi(gsi_state, NULL); 206 } 207 qdev_init_nofail(icc_bridge); 208 209 pc_register_ferr_irq(gsi[13]); 210 211 /* init basic PC hardware */ 212 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104); 213 214 /* connect pm stuff to lpc */ 215 ich9_lpc_pm_init(lpc); 216 217 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 218 ahci = pci_create_simple_multifunction(host_bus, 219 PCI_DEVFN(ICH9_SATA1_DEV, 220 ICH9_SATA1_FUNC), 221 true, "ich9-ahci"); 222 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 223 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 224 225 if (usb_enabled(false)) { 226 /* Should we create 6 UHCI according to ich9 spec? */ 227 ehci_create_ich9_with_companions(host_bus, 0x1d); 228 } 229 230 /* TODO: Populate SPD eeprom data. */ 231 smbus_eeprom_init(ich9_smb_init(host_bus, 232 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 233 0xb100), 234 8, NULL, 0); 235 236 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 237 floppy, idebus[0], idebus[1], rtc_state); 238 239 /* the rest devices to which pci devfn is automatically assigned */ 240 pc_vga_init(isa_bus, host_bus); 241 pc_nic_init(isa_bus, host_bus); 242 if (pci_enabled) { 243 pc_pci_device_init(host_bus); 244 } 245 } 246 247 static void pc_compat_2_0(MachineState *machine) 248 { 249 smbios_legacy_mode = true; 250 has_reserved_memory = false; 251 } 252 253 static void pc_compat_1_7(MachineState *machine) 254 { 255 pc_compat_2_0(machine); 256 smbios_defaults = false; 257 gigabyte_align = false; 258 option_rom_has_mr = true; 259 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); 260 } 261 262 static void pc_compat_1_6(MachineState *machine) 263 { 264 pc_compat_1_7(machine); 265 has_pci_info = false; 266 rom_file_has_mr = false; 267 has_acpi_build = false; 268 } 269 270 static void pc_compat_1_5(MachineState *machine) 271 { 272 pc_compat_1_6(machine); 273 } 274 275 static void pc_compat_1_4(MachineState *machine) 276 { 277 pc_compat_1_5(machine); 278 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 279 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 280 } 281 282 static void pc_q35_init_2_0(MachineState *machine) 283 { 284 pc_compat_2_0(machine); 285 pc_q35_init(machine); 286 } 287 288 static void pc_q35_init_1_7(MachineState *machine) 289 { 290 pc_compat_1_7(machine); 291 pc_q35_init(machine); 292 } 293 294 static void pc_q35_init_1_6(MachineState *machine) 295 { 296 pc_compat_1_6(machine); 297 pc_q35_init(machine); 298 } 299 300 static void pc_q35_init_1_5(MachineState *machine) 301 { 302 pc_compat_1_5(machine); 303 pc_q35_init(machine); 304 } 305 306 static void pc_q35_init_1_4(MachineState *machine) 307 { 308 pc_compat_1_4(machine); 309 pc_q35_init(machine); 310 } 311 312 #define PC_Q35_MACHINE_OPTIONS \ 313 PC_DEFAULT_MACHINE_OPTIONS, \ 314 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 315 .hot_add_cpu = pc_hot_add_cpu 316 317 #define PC_Q35_2_1_MACHINE_OPTIONS \ 318 PC_Q35_MACHINE_OPTIONS, \ 319 .default_machine_opts = "firmware=bios-256k.bin" 320 321 static QEMUMachine pc_q35_machine_v2_1 = { 322 PC_Q35_2_1_MACHINE_OPTIONS, 323 .name = "pc-q35-2.1", 324 .alias = "q35", 325 .init = pc_q35_init, 326 }; 327 328 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS 329 330 static QEMUMachine pc_q35_machine_v2_0 = { 331 PC_Q35_2_0_MACHINE_OPTIONS, 332 .name = "pc-q35-2.0", 333 .init = pc_q35_init_2_0, 334 .compat_props = (GlobalProperty[]) { 335 PC_Q35_COMPAT_2_0, 336 { /* end of list */ } 337 }, 338 }; 339 340 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 341 342 static QEMUMachine pc_q35_machine_v1_7 = { 343 PC_Q35_1_7_MACHINE_OPTIONS, 344 .name = "pc-q35-1.7", 345 .init = pc_q35_init_1_7, 346 .compat_props = (GlobalProperty[]) { 347 PC_Q35_COMPAT_1_7, 348 { /* end of list */ } 349 }, 350 }; 351 352 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 353 354 static QEMUMachine pc_q35_machine_v1_6 = { 355 PC_Q35_1_6_MACHINE_OPTIONS, 356 .name = "pc-q35-1.6", 357 .init = pc_q35_init_1_6, 358 .compat_props = (GlobalProperty[]) { 359 PC_Q35_COMPAT_1_6, 360 { /* end of list */ } 361 }, 362 }; 363 364 static QEMUMachine pc_q35_machine_v1_5 = { 365 PC_Q35_1_6_MACHINE_OPTIONS, 366 .name = "pc-q35-1.5", 367 .init = pc_q35_init_1_5, 368 .compat_props = (GlobalProperty[]) { 369 PC_Q35_COMPAT_1_5, 370 { /* end of list */ } 371 }, 372 }; 373 374 #define PC_Q35_1_4_MACHINE_OPTIONS \ 375 PC_Q35_1_6_MACHINE_OPTIONS, \ 376 .hot_add_cpu = NULL 377 378 static QEMUMachine pc_q35_machine_v1_4 = { 379 PC_Q35_1_4_MACHINE_OPTIONS, 380 .name = "pc-q35-1.4", 381 .init = pc_q35_init_1_4, 382 .compat_props = (GlobalProperty[]) { 383 PC_COMPAT_1_4, 384 { /* end of list */ } 385 }, 386 }; 387 388 static void pc_q35_machine_init(void) 389 { 390 qemu_register_pc_machine(&pc_q35_machine_v2_1); 391 qemu_register_pc_machine(&pc_q35_machine_v2_0); 392 qemu_register_pc_machine(&pc_q35_machine_v1_7); 393 qemu_register_pc_machine(&pc_q35_machine_v1_6); 394 qemu_register_pc_machine(&pc_q35_machine_v1_5); 395 qemu_register_pc_machine(&pc_q35_machine_v1_4); 396 } 397 398 machine_init(pc_q35_machine_init); 399