1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/rtc/mc146818rtc.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "hw/pci/pcie_port.h" 40 #include "hw/qdev-properties.h" 41 #include "hw/i386/x86.h" 42 #include "hw/i386/pc.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/i386/amd_iommu.h" 45 #include "hw/i386/intel_iommu.h" 46 #include "hw/display/ramfb.h" 47 #include "hw/firmware/smbios.h" 48 #include "hw/ide/pci.h" 49 #include "hw/ide/ahci.h" 50 #include "hw/usb.h" 51 #include "hw/usb/hcd-uhci.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "sysemu/numa.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 #include "hw/mem/nvdimm.h" 57 #include "hw/i386/acpi-build.h" 58 59 /* ICH9 AHCI has 6 ports */ 60 #define MAX_SATA_PORTS 6 61 62 struct ehci_companions { 63 const char *name; 64 int func; 65 int port; 66 }; 67 68 static const struct ehci_companions ich9_1d[] = { 69 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 70 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 71 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 72 }; 73 74 static const struct ehci_companions ich9_1a[] = { 75 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 76 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 77 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 78 }; 79 80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 81 { 82 const struct ehci_companions *comp; 83 PCIDevice *ehci, *uhci; 84 BusState *usbbus; 85 const char *name; 86 int i; 87 88 switch (slot) { 89 case 0x1d: 90 name = "ich9-usb-ehci1"; 91 comp = ich9_1d; 92 break; 93 case 0x1a: 94 name = "ich9-usb-ehci2"; 95 comp = ich9_1a; 96 break; 97 default: 98 return -1; 99 } 100 101 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 102 pci_realize_and_unref(ehci, bus, &error_fatal); 103 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 104 105 for (i = 0; i < 3; i++) { 106 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 107 comp[i].name); 108 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 109 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 110 pci_realize_and_unref(uhci, bus, &error_fatal); 111 } 112 return 0; 113 } 114 115 /* PC hardware initialisation */ 116 static void pc_q35_init(MachineState *machine) 117 { 118 PCMachineState *pcms = PC_MACHINE(machine); 119 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 120 X86MachineState *x86ms = X86_MACHINE(machine); 121 Q35PCIHost *q35_host; 122 PCIHostState *phb; 123 PCIBus *host_bus; 124 PCIDevice *lpc; 125 DeviceState *lpc_dev; 126 BusState *idebus[MAX_SATA_PORTS]; 127 ISADevice *rtc_state; 128 MemoryRegion *system_io = get_system_io(); 129 MemoryRegion *pci_memory; 130 MemoryRegion *rom_memory; 131 MemoryRegion *ram_memory; 132 GSIState *gsi_state; 133 ISABus *isa_bus; 134 int i; 135 ICH9LPCState *ich9_lpc; 136 PCIDevice *ahci; 137 ram_addr_t lowmem; 138 DriveInfo *hd[MAX_SATA_PORTS]; 139 MachineClass *mc = MACHINE_GET_CLASS(machine); 140 bool acpi_pcihp; 141 bool keep_pci_slot_hpc; 142 uint64_t pci_hole64_size = 0; 143 144 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 145 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 146 * also known as MMCFG). 147 * If it doesn't, we need to split it in chunks below and above 4G. 148 * In any case, try to make sure that guest addresses aligned at 149 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 150 */ 151 if (machine->ram_size >= 0xb0000000) { 152 lowmem = 0x80000000; 153 } else { 154 lowmem = 0xb0000000; 155 } 156 157 /* Handle the machine opt max-ram-below-4g. It is basically doing 158 * min(qemu limit, user limit). 159 */ 160 if (!pcms->max_ram_below_4g) { 161 pcms->max_ram_below_4g = 4 * GiB; 162 } 163 if (lowmem > pcms->max_ram_below_4g) { 164 lowmem = pcms->max_ram_below_4g; 165 if (machine->ram_size - lowmem > lowmem && 166 lowmem & (1 * GiB - 1)) { 167 warn_report("There is possibly poor performance as the ram size " 168 " (0x%" PRIx64 ") is more then twice the size of" 169 " max-ram-below-4g (%"PRIu64") and" 170 " max-ram-below-4g is not a multiple of 1G.", 171 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 172 } 173 } 174 175 if (machine->ram_size >= lowmem) { 176 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 177 x86ms->below_4g_mem_size = lowmem; 178 } else { 179 x86ms->above_4g_mem_size = 0; 180 x86ms->below_4g_mem_size = machine->ram_size; 181 } 182 183 pc_machine_init_sgx_epc(pcms); 184 x86_cpus_init(x86ms, pcmc->default_cpu_version); 185 186 kvmclock_create(pcmc->kvmclock_create_always); 187 188 /* pci enabled */ 189 if (pcmc->pci_enabled) { 190 pci_memory = g_new(MemoryRegion, 1); 191 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 192 rom_memory = pci_memory; 193 } else { 194 pci_memory = NULL; 195 rom_memory = get_system_memory(); 196 } 197 198 pc_guest_info_init(pcms); 199 200 if (pcmc->smbios_defaults) { 201 /* These values are guest ABI, do not change */ 202 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 203 mc->name, pcmc->smbios_legacy_mode, 204 pcmc->smbios_uuid_encoded, 205 pcms->smbios_entry_point_type); 206 } 207 208 /* create pci host bus */ 209 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 210 211 if (pcmc->pci_enabled) { 212 pci_hole64_size = object_property_get_uint(OBJECT(q35_host), 213 PCI_HOST_PROP_PCI_HOLE64_SIZE, 214 &error_abort); 215 } 216 217 /* allocate ram and load rom/bios */ 218 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, 219 pci_hole64_size); 220 221 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 222 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 223 OBJECT(ram_memory), NULL); 224 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 225 OBJECT(pci_memory), NULL); 226 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 227 OBJECT(get_system_memory()), NULL); 228 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 229 OBJECT(system_io), NULL); 230 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 231 x86ms->below_4g_mem_size, NULL); 232 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 233 x86ms->above_4g_mem_size, NULL); 234 /* pci */ 235 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 236 phb = PCI_HOST_BRIDGE(q35_host); 237 host_bus = phb->bus; 238 /* create ISA bus */ 239 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 240 ICH9_LPC_FUNC), true, 241 TYPE_ICH9_LPC_DEVICE); 242 243 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 244 TYPE_HOTPLUG_HANDLER, 245 (Object **)&x86ms->acpi_dev, 246 object_property_allow_set_link, 247 OBJ_PROP_LINK_STRONG); 248 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 249 OBJECT(lpc), &error_abort); 250 251 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 252 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 253 NULL); 254 255 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 256 "x-keep-pci-slot-hpc", 257 NULL); 258 259 if (!keep_pci_slot_hpc && acpi_pcihp) { 260 object_register_sugar_prop(TYPE_PCIE_SLOT, 261 "x-do-not-expose-native-hotplug-cap", 262 "true", true); 263 } 264 265 /* irq lines */ 266 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 267 268 ich9_lpc = ICH9_LPC_DEVICE(lpc); 269 lpc_dev = DEVICE(lpc); 270 for (i = 0; i < GSI_NUM_PINS; i++) { 271 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 272 } 273 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS); 274 pci_bus_map_irqs(host_bus, ich9_lpc_map_irq); 275 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 276 isa_bus = ich9_lpc->isa_bus; 277 278 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 279 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 280 } 281 282 if (pcmc->pci_enabled) { 283 ioapic_init_gsi(gsi_state, "q35"); 284 } 285 286 if (tcg_enabled()) { 287 x86_register_ferr_irq(x86ms->gsi[13]); 288 } 289 290 assert(pcms->vmport != ON_OFF_AUTO__MAX); 291 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 292 pcms->vmport = ON_OFF_AUTO_ON; 293 } 294 295 /* init basic PC hardware */ 296 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 297 0xff0104); 298 299 /* connect pm stuff to lpc */ 300 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 301 302 if (pcms->sata_enabled) { 303 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 304 ahci = pci_create_simple_multifunction(host_bus, 305 PCI_DEVFN(ICH9_SATA1_DEV, 306 ICH9_SATA1_FUNC), 307 true, "ich9-ahci"); 308 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 309 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 310 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 311 ide_drive_get(hd, ahci_get_num_ports(ahci)); 312 ahci_ide_create_devs(ahci, hd); 313 } else { 314 idebus[0] = idebus[1] = NULL; 315 } 316 317 if (machine_usb(machine)) { 318 /* Should we create 6 UHCI according to ich9 spec? */ 319 ehci_create_ich9_with_companions(host_bus, 0x1d); 320 } 321 322 if (pcms->smbus_enabled) { 323 /* TODO: Populate SPD eeprom data. */ 324 pcms->smbus = ich9_smb_init(host_bus, 325 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 326 0xb100); 327 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 328 } 329 330 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 331 332 /* the rest devices to which pci devfn is automatically assigned */ 333 pc_vga_init(isa_bus, host_bus); 334 pc_nic_init(pcmc, isa_bus, host_bus); 335 336 if (machine->nvdimms_state->is_enabled) { 337 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 338 x86_nvdimm_acpi_dsmio, 339 x86ms->fw_cfg, OBJECT(pcms)); 340 } 341 } 342 343 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 344 static void pc_init_##suffix(MachineState *machine) \ 345 { \ 346 void (*compat)(MachineState *m) = (compatfn); \ 347 if (compat) { \ 348 compat(machine); \ 349 } \ 350 pc_q35_init(machine); \ 351 } \ 352 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 353 354 355 static void pc_q35_machine_options(MachineClass *m) 356 { 357 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 358 pcmc->default_nic_model = "e1000e"; 359 pcmc->pci_root_uid = 0; 360 pcmc->default_cpu_version = 1; 361 362 m->family = "pc_q35"; 363 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 364 m->units_per_default_bus = 1; 365 m->default_machine_opts = "firmware=bios-256k.bin"; 366 m->default_display = "std"; 367 m->default_kernel_irqchip_split = false; 368 m->no_floppy = 1; 369 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 370 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 371 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 372 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 373 m->max_cpus = 288; 374 } 375 376 static void pc_q35_8_0_machine_options(MachineClass *m) 377 { 378 pc_q35_machine_options(m); 379 m->alias = "q35"; 380 } 381 382 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 383 pc_q35_8_0_machine_options); 384 385 static void pc_q35_7_2_machine_options(MachineClass *m) 386 { 387 pc_q35_8_0_machine_options(m); 388 m->alias = NULL; 389 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 390 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 391 } 392 393 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 394 pc_q35_7_2_machine_options); 395 396 static void pc_q35_7_1_machine_options(MachineClass *m) 397 { 398 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 399 pc_q35_7_2_machine_options(m); 400 pcmc->legacy_no_rng_seed = true; 401 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 402 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 403 } 404 405 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 406 pc_q35_7_1_machine_options); 407 408 static void pc_q35_7_0_machine_options(MachineClass *m) 409 { 410 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 411 pc_q35_7_1_machine_options(m); 412 pcmc->enforce_amd_1tb_hole = false; 413 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 414 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 415 } 416 417 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 418 pc_q35_7_0_machine_options); 419 420 static void pc_q35_6_2_machine_options(MachineClass *m) 421 { 422 pc_q35_7_0_machine_options(m); 423 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 424 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 425 } 426 427 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 428 pc_q35_6_2_machine_options); 429 430 static void pc_q35_6_1_machine_options(MachineClass *m) 431 { 432 pc_q35_6_2_machine_options(m); 433 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 434 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 435 m->smp_props.prefer_sockets = true; 436 } 437 438 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 439 pc_q35_6_1_machine_options); 440 441 static void pc_q35_6_0_machine_options(MachineClass *m) 442 { 443 pc_q35_6_1_machine_options(m); 444 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 445 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 446 } 447 448 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 449 pc_q35_6_0_machine_options); 450 451 static void pc_q35_5_2_machine_options(MachineClass *m) 452 { 453 pc_q35_6_0_machine_options(m); 454 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 455 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 456 } 457 458 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 459 pc_q35_5_2_machine_options); 460 461 static void pc_q35_5_1_machine_options(MachineClass *m) 462 { 463 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 464 465 pc_q35_5_2_machine_options(m); 466 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 467 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 468 pcmc->kvmclock_create_always = false; 469 pcmc->pci_root_uid = 1; 470 } 471 472 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 473 pc_q35_5_1_machine_options); 474 475 static void pc_q35_5_0_machine_options(MachineClass *m) 476 { 477 pc_q35_5_1_machine_options(m); 478 m->numa_mem_supported = true; 479 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 480 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 481 m->auto_enable_numa_with_memdev = false; 482 } 483 484 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 485 pc_q35_5_0_machine_options); 486 487 static void pc_q35_4_2_machine_options(MachineClass *m) 488 { 489 pc_q35_5_0_machine_options(m); 490 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 491 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 492 } 493 494 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 495 pc_q35_4_2_machine_options); 496 497 static void pc_q35_4_1_machine_options(MachineClass *m) 498 { 499 pc_q35_4_2_machine_options(m); 500 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 501 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 502 } 503 504 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 505 pc_q35_4_1_machine_options); 506 507 static void pc_q35_4_0_1_machine_options(MachineClass *m) 508 { 509 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 510 pc_q35_4_1_machine_options(m); 511 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 512 /* 513 * This is the default machine for the 4.0-stable branch. It is basically 514 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 515 * 4.0 compat props. 516 */ 517 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 518 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 519 } 520 521 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 522 pc_q35_4_0_1_machine_options); 523 524 static void pc_q35_4_0_machine_options(MachineClass *m) 525 { 526 pc_q35_4_0_1_machine_options(m); 527 m->default_kernel_irqchip_split = true; 528 /* Compat props are applied by the 4.0.1 machine */ 529 } 530 531 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 532 pc_q35_4_0_machine_options); 533 534 static void pc_q35_3_1_machine_options(MachineClass *m) 535 { 536 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 537 538 pc_q35_4_0_machine_options(m); 539 m->default_kernel_irqchip_split = false; 540 m->smbus_no_migration_support = true; 541 pcmc->pvh_enabled = false; 542 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 543 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 544 } 545 546 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 547 pc_q35_3_1_machine_options); 548 549 static void pc_q35_3_0_machine_options(MachineClass *m) 550 { 551 pc_q35_3_1_machine_options(m); 552 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 553 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 554 } 555 556 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 557 pc_q35_3_0_machine_options); 558 559 static void pc_q35_2_12_machine_options(MachineClass *m) 560 { 561 pc_q35_3_0_machine_options(m); 562 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 563 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 564 } 565 566 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 567 pc_q35_2_12_machine_options); 568 569 static void pc_q35_2_11_machine_options(MachineClass *m) 570 { 571 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 572 573 pc_q35_2_12_machine_options(m); 574 pcmc->default_nic_model = "e1000"; 575 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 576 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 577 } 578 579 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 580 pc_q35_2_11_machine_options); 581 582 static void pc_q35_2_10_machine_options(MachineClass *m) 583 { 584 pc_q35_2_11_machine_options(m); 585 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 586 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 587 m->auto_enable_numa_with_memhp = false; 588 } 589 590 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 591 pc_q35_2_10_machine_options); 592 593 static void pc_q35_2_9_machine_options(MachineClass *m) 594 { 595 pc_q35_2_10_machine_options(m); 596 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 597 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 598 } 599 600 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 601 pc_q35_2_9_machine_options); 602 603 static void pc_q35_2_8_machine_options(MachineClass *m) 604 { 605 pc_q35_2_9_machine_options(m); 606 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 607 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 608 } 609 610 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 611 pc_q35_2_8_machine_options); 612 613 static void pc_q35_2_7_machine_options(MachineClass *m) 614 { 615 pc_q35_2_8_machine_options(m); 616 m->max_cpus = 255; 617 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 618 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 619 } 620 621 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 622 pc_q35_2_7_machine_options); 623 624 static void pc_q35_2_6_machine_options(MachineClass *m) 625 { 626 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 627 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 628 629 pc_q35_2_7_machine_options(m); 630 pcmc->legacy_cpu_hotplug = true; 631 x86mc->fwcfg_dma_enabled = false; 632 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 633 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 634 } 635 636 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 637 pc_q35_2_6_machine_options); 638 639 static void pc_q35_2_5_machine_options(MachineClass *m) 640 { 641 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 642 643 pc_q35_2_6_machine_options(m); 644 x86mc->save_tsc_khz = false; 645 m->legacy_fw_cfg_order = 1; 646 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 647 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 648 } 649 650 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 651 pc_q35_2_5_machine_options); 652 653 static void pc_q35_2_4_machine_options(MachineClass *m) 654 { 655 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 656 657 pc_q35_2_5_machine_options(m); 658 m->hw_version = "2.4.0"; 659 pcmc->broken_reserved_end = true; 660 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 661 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 662 } 663 664 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 665 pc_q35_2_4_machine_options); 666