1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "sysemu/arch_init.h" 32 #include "hw/i2c/smbus.h" 33 #include "hw/boards.h" 34 #include "hw/timer/mc146818rtc.h" 35 #include "hw/xen/xen.h" 36 #include "sysemu/kvm.h" 37 #include "hw/kvm/clock.h" 38 #include "hw/pci-host/q35.h" 39 #include "exec/address-spaces.h" 40 #include "hw/i386/ich9.h" 41 #include "hw/ide/pci.h" 42 #include "hw/ide/ahci.h" 43 #include "hw/usb.h" 44 #include "hw/cpu/icc_bus.h" 45 46 /* ICH9 AHCI has 6 ports */ 47 #define MAX_SATA_PORTS 6 48 49 static bool has_pvpanic = true; 50 51 /* PC hardware initialisation */ 52 static void pc_q35_init(QEMUMachineInitArgs *args) 53 { 54 ram_addr_t ram_size = args->ram_size; 55 const char *cpu_model = args->cpu_model; 56 const char *kernel_filename = args->kernel_filename; 57 const char *kernel_cmdline = args->kernel_cmdline; 58 const char *initrd_filename = args->initrd_filename; 59 const char *boot_device = args->boot_device; 60 ram_addr_t below_4g_mem_size, above_4g_mem_size; 61 Q35PCIHost *q35_host; 62 PCIBus *host_bus; 63 PCIDevice *lpc; 64 BusState *idebus[MAX_SATA_PORTS]; 65 ISADevice *rtc_state; 66 ISADevice *floppy; 67 MemoryRegion *pci_memory; 68 MemoryRegion *rom_memory; 69 MemoryRegion *ram_memory; 70 GSIState *gsi_state; 71 ISABus *isa_bus; 72 int pci_enabled = 1; 73 qemu_irq *cpu_irq; 74 qemu_irq *gsi; 75 qemu_irq *i8259; 76 int i; 77 ICH9LPCState *ich9_lpc; 78 PCIDevice *ahci; 79 DeviceState *icc_bridge; 80 PcGuestInfo *guest_info; 81 82 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 83 object_property_add_child(qdev_get_machine(), "icc-bridge", 84 OBJECT(icc_bridge), NULL); 85 86 pc_cpus_init(cpu_model, icc_bridge); 87 pc_acpi_init("q35-acpi-dsdt.aml"); 88 89 kvmclock_create(); 90 91 if (ram_size >= 0xb0000000) { 92 above_4g_mem_size = ram_size - 0xb0000000; 93 below_4g_mem_size = 0xb0000000; 94 } else { 95 above_4g_mem_size = 0; 96 below_4g_mem_size = ram_size; 97 } 98 99 /* pci enabled */ 100 if (pci_enabled) { 101 pci_memory = g_new(MemoryRegion, 1); 102 memory_region_init(pci_memory, "pci", INT64_MAX); 103 rom_memory = pci_memory; 104 } else { 105 pci_memory = NULL; 106 rom_memory = get_system_memory(); 107 } 108 109 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 110 111 /* allocate ram and load rom/bios */ 112 if (!xen_enabled()) { 113 pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline, 114 initrd_filename, below_4g_mem_size, above_4g_mem_size, 115 rom_memory, &ram_memory, guest_info); 116 } 117 118 /* irq lines */ 119 gsi_state = g_malloc0(sizeof(*gsi_state)); 120 if (kvm_irqchip_in_kernel()) { 121 kvm_pc_setup_irq_routing(pci_enabled); 122 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 123 GSI_NUM_PINS); 124 } else { 125 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 126 } 127 128 /* create pci host bus */ 129 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 130 131 q35_host->mch.ram_memory = ram_memory; 132 q35_host->mch.pci_address_space = pci_memory; 133 q35_host->mch.system_memory = get_system_memory(); 134 q35_host->mch.address_space_io = get_system_io(); 135 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 136 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 137 q35_host->mch.guest_info = guest_info; 138 /* pci */ 139 qdev_init_nofail(DEVICE(q35_host)); 140 host_bus = q35_host->host.pci.bus; 141 /* create ISA bus */ 142 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 143 ICH9_LPC_FUNC), true, 144 TYPE_ICH9_LPC_DEVICE); 145 ich9_lpc = ICH9_LPC_DEVICE(lpc); 146 ich9_lpc->pic = gsi; 147 ich9_lpc->ioapic = gsi_state->ioapic_irq; 148 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 149 ICH9_LPC_NB_PIRQS); 150 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 151 isa_bus = ich9_lpc->isa_bus; 152 153 /*end early*/ 154 isa_bus_irqs(isa_bus, gsi); 155 156 if (kvm_irqchip_in_kernel()) { 157 i8259 = kvm_i8259_init(isa_bus); 158 } else if (xen_enabled()) { 159 i8259 = xen_interrupt_controller_init(); 160 } else { 161 cpu_irq = pc_allocate_cpu_irq(); 162 i8259 = i8259_init(isa_bus, cpu_irq[0]); 163 } 164 165 for (i = 0; i < ISA_NUM_IRQS; i++) { 166 gsi_state->i8259_irq[i] = i8259[i]; 167 } 168 if (pci_enabled) { 169 ioapic_init_gsi(gsi_state, NULL); 170 } 171 qdev_init_nofail(icc_bridge); 172 173 pc_register_ferr_irq(gsi[13]); 174 175 /* init basic PC hardware */ 176 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 177 178 /* connect pm stuff to lpc */ 179 ich9_lpc_pm_init(lpc); 180 181 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 182 ahci = pci_create_simple_multifunction(host_bus, 183 PCI_DEVFN(ICH9_SATA1_DEV, 184 ICH9_SATA1_FUNC), 185 true, "ich9-ahci"); 186 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 187 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 188 189 if (usb_enabled(false)) { 190 /* Should we create 6 UHCI according to ich9 spec? */ 191 ehci_create_ich9_with_companions(host_bus, 0x1d); 192 } 193 194 /* TODO: Populate SPD eeprom data. */ 195 smbus_eeprom_init(ich9_smb_init(host_bus, 196 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 197 0xb100), 198 8, NULL, 0); 199 200 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, 201 floppy, idebus[0], idebus[1], rtc_state); 202 203 /* the rest devices to which pci devfn is automatically assigned */ 204 pc_vga_init(isa_bus, host_bus); 205 pc_nic_init(isa_bus, host_bus); 206 if (pci_enabled) { 207 pc_pci_device_init(host_bus); 208 } 209 210 if (has_pvpanic) { 211 pvpanic_init(isa_bus); 212 } 213 } 214 215 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 216 { 217 has_pvpanic = false; 218 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 219 pc_q35_init(args); 220 } 221 222 static QEMUMachine pc_q35_machine_v1_6 = { 223 .name = "pc-q35-1.6", 224 .alias = "q35", 225 .desc = "Standard PC (Q35 + ICH9, 2009)", 226 .init = pc_q35_init, 227 .hot_add_cpu = pc_hot_add_cpu, 228 .max_cpus = 255, 229 DEFAULT_MACHINE_OPTIONS, 230 }; 231 232 static QEMUMachine pc_q35_machine_v1_5 = { 233 .name = "pc-q35-1.5", 234 .desc = "Standard PC (Q35 + ICH9, 2009)", 235 .init = pc_q35_init, 236 .hot_add_cpu = pc_hot_add_cpu, 237 .max_cpus = 255, 238 .compat_props = (GlobalProperty[]) { 239 PC_COMPAT_1_5, 240 { /* end of list */ } 241 }, 242 DEFAULT_MACHINE_OPTIONS, 243 }; 244 245 static QEMUMachine pc_q35_machine_v1_4 = { 246 .name = "pc-q35-1.4", 247 .desc = "Standard PC (Q35 + ICH9, 2009)", 248 .init = pc_q35_init_1_4, 249 .max_cpus = 255, 250 .compat_props = (GlobalProperty[]) { 251 PC_COMPAT_1_4, 252 { /* end of list */ } 253 }, 254 DEFAULT_MACHINE_OPTIONS, 255 }; 256 257 static void pc_q35_machine_init(void) 258 { 259 qemu_register_machine(&pc_q35_machine_v1_6); 260 qemu_register_machine(&pc_q35_machine_v1_5); 261 qemu_register_machine(&pc_q35_machine_v1_4); 262 } 263 264 machine_init(pc_q35_machine_init); 265