1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/acpi/acpi.h" 34 #include "hw/char/parallel-isa.h" 35 #include "hw/loader.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "sysemu/tcg.h" 39 #include "sysemu/kvm.h" 40 #include "hw/i386/kvm/clock.h" 41 #include "hw/pci-host/q35.h" 42 #include "hw/pci/pcie_port.h" 43 #include "hw/qdev-properties.h" 44 #include "hw/i386/x86.h" 45 #include "hw/i386/pc.h" 46 #include "hw/i386/amd_iommu.h" 47 #include "hw/i386/intel_iommu.h" 48 #include "hw/display/ramfb.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci-pci.h" 51 #include "hw/intc/ioapic.h" 52 #include "hw/southbridge/ich9.h" 53 #include "hw/usb.h" 54 #include "hw/usb/hcd-uhci.h" 55 #include "qapi/error.h" 56 #include "qemu/error-report.h" 57 #include "sysemu/numa.h" 58 #include "hw/hyperv/vmbus-bridge.h" 59 #include "hw/mem/nvdimm.h" 60 #include "hw/i386/acpi-build.h" 61 #include "target/i386/cpu.h" 62 63 /* ICH9 AHCI has 6 ports */ 64 #define MAX_SATA_PORTS 6 65 66 struct ehci_companions { 67 const char *name; 68 int func; 69 int port; 70 }; 71 72 static const struct ehci_companions ich9_1d[] = { 73 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 74 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 75 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 76 }; 77 78 static const struct ehci_companions ich9_1a[] = { 79 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 80 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 81 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 82 }; 83 84 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 85 { 86 const struct ehci_companions *comp; 87 PCIDevice *ehci, *uhci; 88 BusState *usbbus; 89 const char *name; 90 int i; 91 92 switch (slot) { 93 case 0x1d: 94 name = "ich9-usb-ehci1"; 95 comp = ich9_1d; 96 break; 97 case 0x1a: 98 name = "ich9-usb-ehci2"; 99 comp = ich9_1a; 100 break; 101 default: 102 return -1; 103 } 104 105 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 106 pci_realize_and_unref(ehci, bus, &error_fatal); 107 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 108 109 for (i = 0; i < 3; i++) { 110 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 111 comp[i].name); 112 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 113 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 114 pci_realize_and_unref(uhci, bus, &error_fatal); 115 } 116 return 0; 117 } 118 119 /* PC hardware initialisation */ 120 static void pc_q35_init(MachineState *machine) 121 { 122 PCMachineState *pcms = PC_MACHINE(machine); 123 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 124 X86MachineState *x86ms = X86_MACHINE(machine); 125 Object *phb; 126 PCIDevice *lpc; 127 DeviceState *lpc_dev; 128 MemoryRegion *system_memory = get_system_memory(); 129 MemoryRegion *system_io = get_system_io(); 130 MemoryRegion *pci_memory = g_new(MemoryRegion, 1); 131 GSIState *gsi_state; 132 ISABus *isa_bus; 133 int i; 134 ram_addr_t lowmem; 135 DriveInfo *hd[MAX_SATA_PORTS]; 136 MachineClass *mc = MACHINE_GET_CLASS(machine); 137 bool acpi_pcihp; 138 bool keep_pci_slot_hpc; 139 uint64_t pci_hole64_size = 0; 140 141 assert(pcmc->pci_enabled); 142 143 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 144 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 145 * also known as MMCFG). 146 * If it doesn't, we need to split it in chunks below and above 4G. 147 * In any case, try to make sure that guest addresses aligned at 148 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 149 */ 150 if (machine->ram_size >= 0xb0000000) { 151 lowmem = 0x80000000; 152 } else { 153 lowmem = 0xb0000000; 154 } 155 156 /* Handle the machine opt max-ram-below-4g. It is basically doing 157 * min(qemu limit, user limit). 158 */ 159 if (!pcms->max_ram_below_4g) { 160 pcms->max_ram_below_4g = 4 * GiB; 161 } 162 if (lowmem > pcms->max_ram_below_4g) { 163 lowmem = pcms->max_ram_below_4g; 164 if (machine->ram_size - lowmem > lowmem && 165 lowmem & (1 * GiB - 1)) { 166 warn_report("There is possibly poor performance as the ram size " 167 " (0x%" PRIx64 ") is more then twice the size of" 168 " max-ram-below-4g (%"PRIu64") and" 169 " max-ram-below-4g is not a multiple of 1G.", 170 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 171 } 172 } 173 174 if (machine->ram_size >= lowmem) { 175 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 176 x86ms->below_4g_mem_size = lowmem; 177 } else { 178 x86ms->above_4g_mem_size = 0; 179 x86ms->below_4g_mem_size = machine->ram_size; 180 } 181 182 pc_machine_init_sgx_epc(pcms); 183 x86_cpus_init(x86ms, pcmc->default_cpu_version); 184 185 if (kvm_enabled()) { 186 kvmclock_create(pcmc->kvmclock_create_always); 187 } 188 189 /* create pci host bus */ 190 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 191 192 pci_hole64_size = object_property_get_uint(phb, 193 PCI_HOST_PROP_PCI_HOLE64_SIZE, 194 &error_abort); 195 196 /* allocate ram and load rom/bios */ 197 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 198 pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); 199 200 object_property_add_child(OBJECT(machine), "q35", phb); 201 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 202 OBJECT(machine->ram), NULL); 203 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 204 OBJECT(pci_memory), NULL); 205 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 206 OBJECT(system_memory), NULL); 207 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 208 OBJECT(system_io), NULL); 209 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 210 x86ms->below_4g_mem_size, NULL); 211 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 212 x86ms->above_4g_mem_size, NULL); 213 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 214 pcms->default_bus_bypass_iommu, NULL); 215 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 216 217 /* pci */ 218 pcms->pcibus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 219 220 /* irq lines */ 221 gsi_state = pc_gsi_create(&x86ms->gsi, true); 222 223 /* create ISA bus */ 224 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 225 TYPE_ICH9_LPC_DEVICE); 226 lpc_dev = DEVICE(lpc); 227 qdev_prop_set_bit(lpc_dev, "smm-enabled", 228 x86_machine_is_smm_enabled(x86ms)); 229 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 230 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 231 } 232 pci_realize_and_unref(lpc, pcms->pcibus, &error_fatal); 233 234 x86ms->rtc = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 235 236 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 237 TYPE_HOTPLUG_HANDLER, 238 (Object **)&x86ms->acpi_dev, 239 object_property_allow_set_link, 240 OBJ_PROP_LINK_STRONG); 241 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 242 OBJECT(lpc), &error_abort); 243 244 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 245 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 246 NULL); 247 248 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 249 "x-keep-pci-slot-hpc", 250 NULL); 251 252 if (!keep_pci_slot_hpc && acpi_pcihp) { 253 object_register_sugar_prop(TYPE_PCIE_SLOT, 254 "x-do-not-expose-native-hotplug-cap", 255 "true", true); 256 } 257 258 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 259 260 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 261 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 262 } 263 264 ioapic_init_gsi(gsi_state, OBJECT(phb)); 265 266 if (tcg_enabled()) { 267 x86_register_ferr_irq(x86ms->gsi[13]); 268 } 269 270 assert(pcms->vmport != ON_OFF_AUTO__MAX); 271 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 272 pcms->vmport = ON_OFF_AUTO_ON; 273 } 274 275 /* init basic PC hardware */ 276 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !mc->no_floppy, 277 0xff0104); 278 279 if (pcms->sata_enabled) { 280 PCIDevice *pdev; 281 AHCIPCIState *ich9; 282 283 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 284 pdev = pci_create_simple_multifunction(pcms->pcibus, 285 PCI_DEVFN(ICH9_SATA1_DEV, 286 ICH9_SATA1_FUNC), 287 "ich9-ahci"); 288 ich9 = ICH9_AHCI(pdev); 289 pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); 290 pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); 291 g_assert(MAX_SATA_PORTS == ich9->ahci.ports); 292 ide_drive_get(hd, ich9->ahci.ports); 293 ahci_ide_create_devs(&ich9->ahci, hd); 294 } 295 296 if (machine_usb(machine)) { 297 /* Should we create 6 UHCI according to ich9 spec? */ 298 ehci_create_ich9_with_companions(pcms->pcibus, 0x1d); 299 } 300 301 if (pcms->smbus_enabled) { 302 PCIDevice *smb; 303 304 /* TODO: Populate SPD eeprom data. */ 305 smb = pci_create_simple_multifunction(pcms->pcibus, 306 PCI_DEVFN(ICH9_SMB_DEV, 307 ICH9_SMB_FUNC), 308 TYPE_ICH9_SMB_DEVICE); 309 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 310 311 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 312 } 313 314 pc_cmos_init(pcms, x86ms->rtc); 315 316 /* the rest devices to which pci devfn is automatically assigned */ 317 pc_vga_init(isa_bus, pcms->pcibus); 318 pc_nic_init(pcmc, isa_bus, pcms->pcibus); 319 320 if (machine->nvdimms_state->is_enabled) { 321 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 322 x86_nvdimm_acpi_dsmio, 323 x86ms->fw_cfg, OBJECT(pcms)); 324 } 325 } 326 327 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 328 static void pc_init_##suffix(MachineState *machine) \ 329 { \ 330 void (*compat)(MachineState *m) = (compatfn); \ 331 if (compat) { \ 332 compat(machine); \ 333 } \ 334 pc_q35_init(machine); \ 335 } \ 336 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 337 338 339 static void pc_q35_machine_options(MachineClass *m) 340 { 341 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 342 pcmc->pci_root_uid = 0; 343 pcmc->default_cpu_version = 1; 344 345 m->family = "pc_q35"; 346 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 347 m->units_per_default_bus = 1; 348 m->default_machine_opts = "firmware=bios-256k.bin"; 349 m->default_display = "std"; 350 m->default_nic = "e1000e"; 351 m->default_kernel_irqchip_split = false; 352 m->no_floppy = 1; 353 m->max_cpus = 1024; 354 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 355 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 356 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 357 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 358 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 359 } 360 361 static void pc_q35_9_0_machine_options(MachineClass *m) 362 { 363 pc_q35_machine_options(m); 364 m->alias = "q35"; 365 } 366 367 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, 368 pc_q35_9_0_machine_options); 369 370 static void pc_q35_8_2_machine_options(MachineClass *m) 371 { 372 pc_q35_9_0_machine_options(m); 373 m->alias = NULL; 374 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 375 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 376 } 377 378 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 379 pc_q35_8_2_machine_options); 380 381 static void pc_q35_8_1_machine_options(MachineClass *m) 382 { 383 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 384 pc_q35_8_2_machine_options(m); 385 m->alias = NULL; 386 pcmc->broken_32bit_mem_addr_check = true; 387 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 388 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 389 } 390 391 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 392 pc_q35_8_1_machine_options); 393 394 static void pc_q35_8_0_machine_options(MachineClass *m) 395 { 396 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 397 398 pc_q35_8_1_machine_options(m); 399 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 400 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 401 402 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 403 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 404 m->max_cpus = 288; 405 } 406 407 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 408 pc_q35_8_0_machine_options); 409 410 static void pc_q35_7_2_machine_options(MachineClass *m) 411 { 412 pc_q35_8_0_machine_options(m); 413 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 414 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 415 } 416 417 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 418 pc_q35_7_2_machine_options); 419 420 static void pc_q35_7_1_machine_options(MachineClass *m) 421 { 422 pc_q35_7_2_machine_options(m); 423 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 424 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 425 } 426 427 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 428 pc_q35_7_1_machine_options); 429 430 static void pc_q35_7_0_machine_options(MachineClass *m) 431 { 432 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 433 pc_q35_7_1_machine_options(m); 434 pcmc->enforce_amd_1tb_hole = false; 435 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 436 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 437 } 438 439 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 440 pc_q35_7_0_machine_options); 441 442 static void pc_q35_6_2_machine_options(MachineClass *m) 443 { 444 pc_q35_7_0_machine_options(m); 445 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 446 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 447 } 448 449 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 450 pc_q35_6_2_machine_options); 451 452 static void pc_q35_6_1_machine_options(MachineClass *m) 453 { 454 pc_q35_6_2_machine_options(m); 455 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 456 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 457 m->smp_props.prefer_sockets = true; 458 } 459 460 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 461 pc_q35_6_1_machine_options); 462 463 static void pc_q35_6_0_machine_options(MachineClass *m) 464 { 465 pc_q35_6_1_machine_options(m); 466 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 467 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 468 } 469 470 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 471 pc_q35_6_0_machine_options); 472 473 static void pc_q35_5_2_machine_options(MachineClass *m) 474 { 475 pc_q35_6_0_machine_options(m); 476 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 477 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 478 } 479 480 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 481 pc_q35_5_2_machine_options); 482 483 static void pc_q35_5_1_machine_options(MachineClass *m) 484 { 485 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 486 487 pc_q35_5_2_machine_options(m); 488 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 489 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 490 pcmc->kvmclock_create_always = false; 491 pcmc->pci_root_uid = 1; 492 } 493 494 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 495 pc_q35_5_1_machine_options); 496 497 static void pc_q35_5_0_machine_options(MachineClass *m) 498 { 499 pc_q35_5_1_machine_options(m); 500 m->numa_mem_supported = true; 501 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 502 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 503 m->auto_enable_numa_with_memdev = false; 504 } 505 506 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 507 pc_q35_5_0_machine_options); 508 509 static void pc_q35_4_2_machine_options(MachineClass *m) 510 { 511 pc_q35_5_0_machine_options(m); 512 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 513 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 514 } 515 516 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 517 pc_q35_4_2_machine_options); 518 519 static void pc_q35_4_1_machine_options(MachineClass *m) 520 { 521 pc_q35_4_2_machine_options(m); 522 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 523 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 524 } 525 526 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 527 pc_q35_4_1_machine_options); 528 529 static void pc_q35_4_0_1_machine_options(MachineClass *m) 530 { 531 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 532 pc_q35_4_1_machine_options(m); 533 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 534 /* 535 * This is the default machine for the 4.0-stable branch. It is basically 536 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 537 * 4.0 compat props. 538 */ 539 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 540 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 541 } 542 543 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 544 pc_q35_4_0_1_machine_options); 545 546 static void pc_q35_4_0_machine_options(MachineClass *m) 547 { 548 pc_q35_4_0_1_machine_options(m); 549 m->default_kernel_irqchip_split = true; 550 /* Compat props are applied by the 4.0.1 machine */ 551 } 552 553 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 554 pc_q35_4_0_machine_options); 555 556 static void pc_q35_3_1_machine_options(MachineClass *m) 557 { 558 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 559 560 pc_q35_4_0_machine_options(m); 561 m->default_kernel_irqchip_split = false; 562 m->smbus_no_migration_support = true; 563 pcmc->pvh_enabled = false; 564 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 565 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 566 } 567 568 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 569 pc_q35_3_1_machine_options); 570 571 static void pc_q35_3_0_machine_options(MachineClass *m) 572 { 573 pc_q35_3_1_machine_options(m); 574 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 575 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 576 } 577 578 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 579 pc_q35_3_0_machine_options); 580 581 static void pc_q35_2_12_machine_options(MachineClass *m) 582 { 583 pc_q35_3_0_machine_options(m); 584 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 585 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 586 } 587 588 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 589 pc_q35_2_12_machine_options); 590 591 static void pc_q35_2_11_machine_options(MachineClass *m) 592 { 593 pc_q35_2_12_machine_options(m); 594 m->default_nic = "e1000"; 595 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 596 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 597 } 598 599 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 600 pc_q35_2_11_machine_options); 601 602 static void pc_q35_2_10_machine_options(MachineClass *m) 603 { 604 pc_q35_2_11_machine_options(m); 605 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 606 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 607 m->auto_enable_numa_with_memhp = false; 608 } 609 610 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 611 pc_q35_2_10_machine_options); 612 613 static void pc_q35_2_9_machine_options(MachineClass *m) 614 { 615 pc_q35_2_10_machine_options(m); 616 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 617 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 618 } 619 620 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 621 pc_q35_2_9_machine_options); 622 623 static void pc_q35_2_8_machine_options(MachineClass *m) 624 { 625 pc_q35_2_9_machine_options(m); 626 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 627 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 628 } 629 630 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 631 pc_q35_2_8_machine_options); 632 633 static void pc_q35_2_7_machine_options(MachineClass *m) 634 { 635 pc_q35_2_8_machine_options(m); 636 m->max_cpus = 255; 637 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 638 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 639 } 640 641 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 642 pc_q35_2_7_machine_options); 643 644 static void pc_q35_2_6_machine_options(MachineClass *m) 645 { 646 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 647 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 648 649 pc_q35_2_7_machine_options(m); 650 pcmc->legacy_cpu_hotplug = true; 651 x86mc->fwcfg_dma_enabled = false; 652 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 653 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 654 } 655 656 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 657 pc_q35_2_6_machine_options); 658 659 static void pc_q35_2_5_machine_options(MachineClass *m) 660 { 661 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 662 663 pc_q35_2_6_machine_options(m); 664 x86mc->save_tsc_khz = false; 665 m->legacy_fw_cfg_order = 1; 666 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 667 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 668 } 669 670 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 671 pc_q35_2_5_machine_options); 672 673 static void pc_q35_2_4_machine_options(MachineClass *m) 674 { 675 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 676 677 pc_q35_2_5_machine_options(m); 678 m->hw_version = "2.4.0"; 679 pcmc->broken_reserved_end = true; 680 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 681 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 682 } 683 684 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 685 pc_q35_2_4_machine_options); 686