1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "hw/qdev-properties.h" 41 #include "exec/address-spaces.h" 42 #include "hw/i386/x86.h" 43 #include "hw/i386/pc.h" 44 #include "hw/i386/ich9.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/firmware/smbios.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci.h" 51 #include "hw/usb.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "sysemu/numa.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 #include "hw/mem/nvdimm.h" 57 #include "hw/i386/acpi-build.h" 58 59 /* ICH9 AHCI has 6 ports */ 60 #define MAX_SATA_PORTS 6 61 62 struct ehci_companions { 63 const char *name; 64 int func; 65 int port; 66 }; 67 68 static const struct ehci_companions ich9_1d[] = { 69 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 70 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 71 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 72 }; 73 74 static const struct ehci_companions ich9_1a[] = { 75 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 76 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 77 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 78 }; 79 80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 81 { 82 const struct ehci_companions *comp; 83 PCIDevice *ehci, *uhci; 84 BusState *usbbus; 85 const char *name; 86 int i; 87 88 switch (slot) { 89 case 0x1d: 90 name = "ich9-usb-ehci1"; 91 comp = ich9_1d; 92 break; 93 case 0x1a: 94 name = "ich9-usb-ehci2"; 95 comp = ich9_1a; 96 break; 97 default: 98 return -1; 99 } 100 101 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 102 pci_realize_and_unref(ehci, bus, &error_fatal); 103 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 104 105 for (i = 0; i < 3; i++) { 106 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 107 comp[i].name); 108 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 109 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 110 pci_realize_and_unref(uhci, bus, &error_fatal); 111 } 112 return 0; 113 } 114 115 /* PC hardware initialisation */ 116 static void pc_q35_init(MachineState *machine) 117 { 118 PCMachineState *pcms = PC_MACHINE(machine); 119 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 120 X86MachineState *x86ms = X86_MACHINE(machine); 121 Q35PCIHost *q35_host; 122 PCIHostState *phb; 123 PCIBus *host_bus; 124 PCIDevice *lpc; 125 DeviceState *lpc_dev; 126 BusState *idebus[MAX_SATA_PORTS]; 127 ISADevice *rtc_state; 128 MemoryRegion *system_io = get_system_io(); 129 MemoryRegion *pci_memory; 130 MemoryRegion *rom_memory; 131 MemoryRegion *ram_memory; 132 GSIState *gsi_state; 133 ISABus *isa_bus; 134 int i; 135 ICH9LPCState *ich9_lpc; 136 PCIDevice *ahci; 137 ram_addr_t lowmem; 138 DriveInfo *hd[MAX_SATA_PORTS]; 139 MachineClass *mc = MACHINE_GET_CLASS(machine); 140 141 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 142 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 143 * also known as MMCFG). 144 * If it doesn't, we need to split it in chunks below and above 4G. 145 * In any case, try to make sure that guest addresses aligned at 146 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 147 */ 148 if (machine->ram_size >= 0xb0000000) { 149 lowmem = 0x80000000; 150 } else { 151 lowmem = 0xb0000000; 152 } 153 154 /* Handle the machine opt max-ram-below-4g. It is basically doing 155 * min(qemu limit, user limit). 156 */ 157 if (!pcms->max_ram_below_4g) { 158 pcms->max_ram_below_4g = 4 * GiB; 159 } 160 if (lowmem > pcms->max_ram_below_4g) { 161 lowmem = pcms->max_ram_below_4g; 162 if (machine->ram_size - lowmem > lowmem && 163 lowmem & (1 * GiB - 1)) { 164 warn_report("There is possibly poor performance as the ram size " 165 " (0x%" PRIx64 ") is more then twice the size of" 166 " max-ram-below-4g (%"PRIu64") and" 167 " max-ram-below-4g is not a multiple of 1G.", 168 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 169 } 170 } 171 172 if (machine->ram_size >= lowmem) { 173 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 174 x86ms->below_4g_mem_size = lowmem; 175 } else { 176 x86ms->above_4g_mem_size = 0; 177 x86ms->below_4g_mem_size = machine->ram_size; 178 } 179 180 x86_cpus_init(x86ms, pcmc->default_cpu_version); 181 182 kvmclock_create(pcmc->kvmclock_create_always); 183 184 /* pci enabled */ 185 if (pcmc->pci_enabled) { 186 pci_memory = g_new(MemoryRegion, 1); 187 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 188 rom_memory = pci_memory; 189 } else { 190 pci_memory = NULL; 191 rom_memory = get_system_memory(); 192 } 193 194 pc_guest_info_init(pcms); 195 196 if (pcmc->smbios_defaults) { 197 /* These values are guest ABI, do not change */ 198 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 199 mc->name, pcmc->smbios_legacy_mode, 200 pcmc->smbios_uuid_encoded, 201 SMBIOS_ENTRY_POINT_21); 202 } 203 204 /* allocate ram and load rom/bios */ 205 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); 206 207 /* create pci host bus */ 208 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 209 210 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 211 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 212 OBJECT(ram_memory), NULL); 213 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 214 OBJECT(pci_memory), NULL); 215 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 216 OBJECT(get_system_memory()), NULL); 217 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 218 OBJECT(system_io), NULL); 219 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 220 x86ms->below_4g_mem_size, NULL); 221 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 222 x86ms->above_4g_mem_size, NULL); 223 /* pci */ 224 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 225 phb = PCI_HOST_BRIDGE(q35_host); 226 host_bus = phb->bus; 227 /* create ISA bus */ 228 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 229 ICH9_LPC_FUNC), true, 230 TYPE_ICH9_LPC_DEVICE); 231 232 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 233 TYPE_HOTPLUG_HANDLER, 234 (Object **)&x86ms->acpi_dev, 235 object_property_allow_set_link, 236 OBJ_PROP_LINK_STRONG); 237 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 238 OBJECT(lpc), &error_abort); 239 240 /* irq lines */ 241 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 242 243 ich9_lpc = ICH9_LPC_DEVICE(lpc); 244 lpc_dev = DEVICE(lpc); 245 for (i = 0; i < GSI_NUM_PINS; i++) { 246 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 247 } 248 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 249 ICH9_LPC_NB_PIRQS); 250 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 251 isa_bus = ich9_lpc->isa_bus; 252 253 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 254 255 if (pcmc->pci_enabled) { 256 ioapic_init_gsi(gsi_state, "q35"); 257 } 258 259 if (tcg_enabled()) { 260 x86_register_ferr_irq(x86ms->gsi[13]); 261 } 262 263 assert(pcms->vmport != ON_OFF_AUTO__MAX); 264 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 265 pcms->vmport = ON_OFF_AUTO_ON; 266 } 267 268 /* init basic PC hardware */ 269 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 270 0xff0104); 271 272 /* connect pm stuff to lpc */ 273 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 274 275 if (pcms->sata_enabled) { 276 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 277 ahci = pci_create_simple_multifunction(host_bus, 278 PCI_DEVFN(ICH9_SATA1_DEV, 279 ICH9_SATA1_FUNC), 280 true, "ich9-ahci"); 281 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 282 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 283 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 284 ide_drive_get(hd, ahci_get_num_ports(ahci)); 285 ahci_ide_create_devs(ahci, hd); 286 } else { 287 idebus[0] = idebus[1] = NULL; 288 } 289 290 if (machine_usb(machine)) { 291 /* Should we create 6 UHCI according to ich9 spec? */ 292 ehci_create_ich9_with_companions(host_bus, 0x1d); 293 } 294 295 if (pcms->smbus_enabled) { 296 /* TODO: Populate SPD eeprom data. */ 297 pcms->smbus = ich9_smb_init(host_bus, 298 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 299 0xb100); 300 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 301 } 302 303 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 304 305 /* the rest devices to which pci devfn is automatically assigned */ 306 pc_vga_init(isa_bus, host_bus); 307 pc_nic_init(pcmc, isa_bus, host_bus); 308 309 if (machine->nvdimms_state->is_enabled) { 310 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 311 x86_nvdimm_acpi_dsmio, 312 x86ms->fw_cfg, OBJECT(pcms)); 313 } 314 } 315 316 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 317 static void pc_init_##suffix(MachineState *machine) \ 318 { \ 319 void (*compat)(MachineState *m) = (compatfn); \ 320 if (compat) { \ 321 compat(machine); \ 322 } \ 323 pc_q35_init(machine); \ 324 } \ 325 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 326 327 328 static void pc_q35_machine_options(MachineClass *m) 329 { 330 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 331 pcmc->default_nic_model = "e1000e"; 332 333 m->family = "pc_q35"; 334 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 335 m->units_per_default_bus = 1; 336 m->default_machine_opts = "firmware=bios-256k.bin"; 337 m->default_display = "std"; 338 m->default_kernel_irqchip_split = false; 339 m->no_floppy = 1; 340 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 341 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 342 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 343 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 344 m->max_cpus = 288; 345 } 346 347 static void pc_q35_6_0_machine_options(MachineClass *m) 348 { 349 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 350 pc_q35_machine_options(m); 351 m->alias = "q35"; 352 pcmc->default_cpu_version = 1; 353 } 354 355 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 356 pc_q35_6_0_machine_options); 357 358 static void pc_q35_5_2_machine_options(MachineClass *m) 359 { 360 pc_q35_6_0_machine_options(m); 361 m->alias = NULL; 362 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 363 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 364 } 365 366 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 367 pc_q35_5_2_machine_options); 368 369 static void pc_q35_5_1_machine_options(MachineClass *m) 370 { 371 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 372 373 pc_q35_5_2_machine_options(m); 374 m->alias = NULL; 375 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 376 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 377 pcmc->kvmclock_create_always = false; 378 } 379 380 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 381 pc_q35_5_1_machine_options); 382 383 static void pc_q35_5_0_machine_options(MachineClass *m) 384 { 385 pc_q35_5_1_machine_options(m); 386 m->alias = NULL; 387 m->numa_mem_supported = true; 388 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 389 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 390 m->auto_enable_numa_with_memdev = false; 391 } 392 393 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 394 pc_q35_5_0_machine_options); 395 396 static void pc_q35_4_2_machine_options(MachineClass *m) 397 { 398 pc_q35_5_0_machine_options(m); 399 m->alias = NULL; 400 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 401 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 402 } 403 404 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 405 pc_q35_4_2_machine_options); 406 407 static void pc_q35_4_1_machine_options(MachineClass *m) 408 { 409 pc_q35_4_2_machine_options(m); 410 m->alias = NULL; 411 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 412 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 413 } 414 415 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 416 pc_q35_4_1_machine_options); 417 418 static void pc_q35_4_0_1_machine_options(MachineClass *m) 419 { 420 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 421 pc_q35_4_1_machine_options(m); 422 m->alias = NULL; 423 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 424 /* 425 * This is the default machine for the 4.0-stable branch. It is basically 426 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 427 * 4.0 compat props. 428 */ 429 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 430 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 431 } 432 433 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 434 pc_q35_4_0_1_machine_options); 435 436 static void pc_q35_4_0_machine_options(MachineClass *m) 437 { 438 pc_q35_4_0_1_machine_options(m); 439 m->default_kernel_irqchip_split = true; 440 m->alias = NULL; 441 /* Compat props are applied by the 4.0.1 machine */ 442 } 443 444 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 445 pc_q35_4_0_machine_options); 446 447 static void pc_q35_3_1_machine_options(MachineClass *m) 448 { 449 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 450 451 pc_q35_4_0_machine_options(m); 452 m->default_kernel_irqchip_split = false; 453 pcmc->do_not_add_smb_acpi = true; 454 m->smbus_no_migration_support = true; 455 m->alias = NULL; 456 pcmc->pvh_enabled = false; 457 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 458 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 459 } 460 461 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 462 pc_q35_3_1_machine_options); 463 464 static void pc_q35_3_0_machine_options(MachineClass *m) 465 { 466 pc_q35_3_1_machine_options(m); 467 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 468 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 469 } 470 471 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 472 pc_q35_3_0_machine_options); 473 474 static void pc_q35_2_12_machine_options(MachineClass *m) 475 { 476 pc_q35_3_0_machine_options(m); 477 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 478 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 479 } 480 481 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 482 pc_q35_2_12_machine_options); 483 484 static void pc_q35_2_11_machine_options(MachineClass *m) 485 { 486 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 487 488 pc_q35_2_12_machine_options(m); 489 pcmc->default_nic_model = "e1000"; 490 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 491 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 492 } 493 494 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 495 pc_q35_2_11_machine_options); 496 497 static void pc_q35_2_10_machine_options(MachineClass *m) 498 { 499 pc_q35_2_11_machine_options(m); 500 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 501 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 502 m->auto_enable_numa_with_memhp = false; 503 } 504 505 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 506 pc_q35_2_10_machine_options); 507 508 static void pc_q35_2_9_machine_options(MachineClass *m) 509 { 510 pc_q35_2_10_machine_options(m); 511 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 512 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 513 } 514 515 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 516 pc_q35_2_9_machine_options); 517 518 static void pc_q35_2_8_machine_options(MachineClass *m) 519 { 520 pc_q35_2_9_machine_options(m); 521 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 522 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 523 } 524 525 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 526 pc_q35_2_8_machine_options); 527 528 static void pc_q35_2_7_machine_options(MachineClass *m) 529 { 530 pc_q35_2_8_machine_options(m); 531 m->max_cpus = 255; 532 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 533 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 534 } 535 536 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 537 pc_q35_2_7_machine_options); 538 539 static void pc_q35_2_6_machine_options(MachineClass *m) 540 { 541 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 542 543 pc_q35_2_7_machine_options(m); 544 pcmc->legacy_cpu_hotplug = true; 545 pcmc->linuxboot_dma_enabled = false; 546 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 547 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 548 } 549 550 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 551 pc_q35_2_6_machine_options); 552 553 static void pc_q35_2_5_machine_options(MachineClass *m) 554 { 555 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 556 557 pc_q35_2_6_machine_options(m); 558 x86mc->save_tsc_khz = false; 559 m->legacy_fw_cfg_order = 1; 560 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 561 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 562 } 563 564 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 565 pc_q35_2_5_machine_options); 566 567 static void pc_q35_2_4_machine_options(MachineClass *m) 568 { 569 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 570 571 pc_q35_2_5_machine_options(m); 572 m->hw_version = "2.4.0"; 573 pcmc->broken_reserved_end = true; 574 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 575 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 576 } 577 578 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 579 pc_q35_2_4_machine_options); 580