1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/loader.h" 34 #include "sysemu/arch_init.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "hw/pci/pcie_port.h" 41 #include "hw/qdev-properties.h" 42 #include "hw/i386/x86.h" 43 #include "hw/i386/pc.h" 44 #include "hw/i386/ich9.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/firmware/smbios.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci.h" 51 #include "hw/usb.h" 52 #include "qapi/error.h" 53 #include "qemu/error-report.h" 54 #include "sysemu/numa.h" 55 #include "hw/hyperv/vmbus-bridge.h" 56 #include "hw/mem/nvdimm.h" 57 #include "hw/i386/acpi-build.h" 58 59 /* ICH9 AHCI has 6 ports */ 60 #define MAX_SATA_PORTS 6 61 62 struct ehci_companions { 63 const char *name; 64 int func; 65 int port; 66 }; 67 68 static const struct ehci_companions ich9_1d[] = { 69 { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, 70 { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, 71 { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, 72 }; 73 74 static const struct ehci_companions ich9_1a[] = { 75 { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, 76 { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, 77 { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, 78 }; 79 80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 81 { 82 const struct ehci_companions *comp; 83 PCIDevice *ehci, *uhci; 84 BusState *usbbus; 85 const char *name; 86 int i; 87 88 switch (slot) { 89 case 0x1d: 90 name = "ich9-usb-ehci1"; 91 comp = ich9_1d; 92 break; 93 case 0x1a: 94 name = "ich9-usb-ehci2"; 95 comp = ich9_1a; 96 break; 97 default: 98 return -1; 99 } 100 101 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); 102 pci_realize_and_unref(ehci, bus, &error_fatal); 103 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 104 105 for (i = 0; i < 3; i++) { 106 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, 107 comp[i].name); 108 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 109 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 110 pci_realize_and_unref(uhci, bus, &error_fatal); 111 } 112 return 0; 113 } 114 115 /* PC hardware initialisation */ 116 static void pc_q35_init(MachineState *machine) 117 { 118 PCMachineState *pcms = PC_MACHINE(machine); 119 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 120 X86MachineState *x86ms = X86_MACHINE(machine); 121 Q35PCIHost *q35_host; 122 PCIHostState *phb; 123 PCIBus *host_bus; 124 PCIDevice *lpc; 125 DeviceState *lpc_dev; 126 BusState *idebus[MAX_SATA_PORTS]; 127 ISADevice *rtc_state; 128 MemoryRegion *system_io = get_system_io(); 129 MemoryRegion *pci_memory; 130 MemoryRegion *rom_memory; 131 MemoryRegion *ram_memory; 132 GSIState *gsi_state; 133 ISABus *isa_bus; 134 int i; 135 ICH9LPCState *ich9_lpc; 136 PCIDevice *ahci; 137 ram_addr_t lowmem; 138 DriveInfo *hd[MAX_SATA_PORTS]; 139 MachineClass *mc = MACHINE_GET_CLASS(machine); 140 bool acpi_pcihp; 141 142 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 143 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 144 * also known as MMCFG). 145 * If it doesn't, we need to split it in chunks below and above 4G. 146 * In any case, try to make sure that guest addresses aligned at 147 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 148 */ 149 if (machine->ram_size >= 0xb0000000) { 150 lowmem = 0x80000000; 151 } else { 152 lowmem = 0xb0000000; 153 } 154 155 /* Handle the machine opt max-ram-below-4g. It is basically doing 156 * min(qemu limit, user limit). 157 */ 158 if (!pcms->max_ram_below_4g) { 159 pcms->max_ram_below_4g = 4 * GiB; 160 } 161 if (lowmem > pcms->max_ram_below_4g) { 162 lowmem = pcms->max_ram_below_4g; 163 if (machine->ram_size - lowmem > lowmem && 164 lowmem & (1 * GiB - 1)) { 165 warn_report("There is possibly poor performance as the ram size " 166 " (0x%" PRIx64 ") is more then twice the size of" 167 " max-ram-below-4g (%"PRIu64") and" 168 " max-ram-below-4g is not a multiple of 1G.", 169 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 170 } 171 } 172 173 if (machine->ram_size >= lowmem) { 174 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 175 x86ms->below_4g_mem_size = lowmem; 176 } else { 177 x86ms->above_4g_mem_size = 0; 178 x86ms->below_4g_mem_size = machine->ram_size; 179 } 180 181 x86_cpus_init(x86ms, pcmc->default_cpu_version); 182 183 kvmclock_create(pcmc->kvmclock_create_always); 184 185 /* pci enabled */ 186 if (pcmc->pci_enabled) { 187 pci_memory = g_new(MemoryRegion, 1); 188 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 189 rom_memory = pci_memory; 190 } else { 191 pci_memory = NULL; 192 rom_memory = get_system_memory(); 193 } 194 195 pc_guest_info_init(pcms); 196 197 if (pcmc->smbios_defaults) { 198 /* These values are guest ABI, do not change */ 199 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 200 mc->name, pcmc->smbios_legacy_mode, 201 pcmc->smbios_uuid_encoded, 202 SMBIOS_ENTRY_POINT_21); 203 } 204 205 /* allocate ram and load rom/bios */ 206 pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); 207 208 /* create pci host bus */ 209 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 210 211 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 212 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 213 OBJECT(ram_memory), NULL); 214 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 215 OBJECT(pci_memory), NULL); 216 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 217 OBJECT(get_system_memory()), NULL); 218 object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 219 OBJECT(system_io), NULL); 220 object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 221 x86ms->below_4g_mem_size, NULL); 222 object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 223 x86ms->above_4g_mem_size, NULL); 224 /* pci */ 225 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 226 phb = PCI_HOST_BRIDGE(q35_host); 227 host_bus = phb->bus; 228 /* create ISA bus */ 229 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 230 ICH9_LPC_FUNC), true, 231 TYPE_ICH9_LPC_DEVICE); 232 233 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 234 TYPE_HOTPLUG_HANDLER, 235 (Object **)&x86ms->acpi_dev, 236 object_property_allow_set_link, 237 OBJ_PROP_LINK_STRONG); 238 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 239 OBJECT(lpc), &error_abort); 240 241 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 242 "acpi-pci-hotplug-with-bridge-support", 243 NULL); 244 245 if (acpi_pcihp) { 246 object_register_sugar_prop(TYPE_PCIE_SLOT, "native-hotplug", 247 "false", true); 248 } 249 250 /* irq lines */ 251 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 252 253 ich9_lpc = ICH9_LPC_DEVICE(lpc); 254 lpc_dev = DEVICE(lpc); 255 for (i = 0; i < GSI_NUM_PINS; i++) { 256 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 257 } 258 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 259 ICH9_LPC_NB_PIRQS); 260 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 261 isa_bus = ich9_lpc->isa_bus; 262 263 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 264 265 if (pcmc->pci_enabled) { 266 ioapic_init_gsi(gsi_state, "q35"); 267 } 268 269 if (tcg_enabled()) { 270 x86_register_ferr_irq(x86ms->gsi[13]); 271 } 272 273 assert(pcms->vmport != ON_OFF_AUTO__MAX); 274 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 275 pcms->vmport = ON_OFF_AUTO_ON; 276 } 277 278 /* init basic PC hardware */ 279 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, 280 0xff0104); 281 282 /* connect pm stuff to lpc */ 283 ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms)); 284 285 if (pcms->sata_enabled) { 286 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 287 ahci = pci_create_simple_multifunction(host_bus, 288 PCI_DEVFN(ICH9_SATA1_DEV, 289 ICH9_SATA1_FUNC), 290 true, "ich9-ahci"); 291 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 292 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 293 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 294 ide_drive_get(hd, ahci_get_num_ports(ahci)); 295 ahci_ide_create_devs(ahci, hd); 296 } else { 297 idebus[0] = idebus[1] = NULL; 298 } 299 300 if (machine_usb(machine)) { 301 /* Should we create 6 UHCI according to ich9 spec? */ 302 ehci_create_ich9_with_companions(host_bus, 0x1d); 303 } 304 305 if (pcms->smbus_enabled) { 306 /* TODO: Populate SPD eeprom data. */ 307 pcms->smbus = ich9_smb_init(host_bus, 308 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 309 0xb100); 310 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 311 } 312 313 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 314 315 /* the rest devices to which pci devfn is automatically assigned */ 316 pc_vga_init(isa_bus, host_bus); 317 pc_nic_init(pcmc, isa_bus, host_bus); 318 319 if (machine->nvdimms_state->is_enabled) { 320 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 321 x86_nvdimm_acpi_dsmio, 322 x86ms->fw_cfg, OBJECT(pcms)); 323 } 324 } 325 326 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 327 static void pc_init_##suffix(MachineState *machine) \ 328 { \ 329 void (*compat)(MachineState *m) = (compatfn); \ 330 if (compat) { \ 331 compat(machine); \ 332 } \ 333 pc_q35_init(machine); \ 334 } \ 335 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 336 337 338 static void pc_q35_machine_options(MachineClass *m) 339 { 340 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 341 pcmc->default_nic_model = "e1000e"; 342 pcmc->pci_root_uid = 0; 343 344 m->family = "pc_q35"; 345 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 346 m->units_per_default_bus = 1; 347 m->default_machine_opts = "firmware=bios-256k.bin"; 348 m->default_display = "std"; 349 m->default_kernel_irqchip_split = false; 350 m->no_floppy = 1; 351 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 352 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 353 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 354 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 355 m->max_cpus = 288; 356 } 357 358 static void pc_q35_6_1_machine_options(MachineClass *m) 359 { 360 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 361 pc_q35_machine_options(m); 362 m->alias = "q35"; 363 pcmc->default_cpu_version = 1; 364 } 365 366 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 367 pc_q35_6_1_machine_options); 368 369 static void pc_q35_6_0_machine_options(MachineClass *m) 370 { 371 pc_q35_6_1_machine_options(m); 372 m->alias = NULL; 373 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 374 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 375 } 376 377 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 378 pc_q35_6_0_machine_options); 379 380 static void pc_q35_5_2_machine_options(MachineClass *m) 381 { 382 pc_q35_6_0_machine_options(m); 383 m->alias = NULL; 384 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 385 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 386 } 387 388 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 389 pc_q35_5_2_machine_options); 390 391 static void pc_q35_5_1_machine_options(MachineClass *m) 392 { 393 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 394 395 pc_q35_5_2_machine_options(m); 396 m->alias = NULL; 397 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 398 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 399 pcmc->kvmclock_create_always = false; 400 pcmc->pci_root_uid = 1; 401 } 402 403 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 404 pc_q35_5_1_machine_options); 405 406 static void pc_q35_5_0_machine_options(MachineClass *m) 407 { 408 pc_q35_5_1_machine_options(m); 409 m->alias = NULL; 410 m->numa_mem_supported = true; 411 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 412 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 413 m->auto_enable_numa_with_memdev = false; 414 } 415 416 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 417 pc_q35_5_0_machine_options); 418 419 static void pc_q35_4_2_machine_options(MachineClass *m) 420 { 421 pc_q35_5_0_machine_options(m); 422 m->alias = NULL; 423 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 424 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 425 } 426 427 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 428 pc_q35_4_2_machine_options); 429 430 static void pc_q35_4_1_machine_options(MachineClass *m) 431 { 432 pc_q35_4_2_machine_options(m); 433 m->alias = NULL; 434 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 435 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 436 } 437 438 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 439 pc_q35_4_1_machine_options); 440 441 static void pc_q35_4_0_1_machine_options(MachineClass *m) 442 { 443 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 444 pc_q35_4_1_machine_options(m); 445 m->alias = NULL; 446 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 447 /* 448 * This is the default machine for the 4.0-stable branch. It is basically 449 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 450 * 4.0 compat props. 451 */ 452 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 453 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 454 } 455 456 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 457 pc_q35_4_0_1_machine_options); 458 459 static void pc_q35_4_0_machine_options(MachineClass *m) 460 { 461 pc_q35_4_0_1_machine_options(m); 462 m->default_kernel_irqchip_split = true; 463 m->alias = NULL; 464 /* Compat props are applied by the 4.0.1 machine */ 465 } 466 467 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 468 pc_q35_4_0_machine_options); 469 470 static void pc_q35_3_1_machine_options(MachineClass *m) 471 { 472 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 473 474 pc_q35_4_0_machine_options(m); 475 m->default_kernel_irqchip_split = false; 476 pcmc->do_not_add_smb_acpi = true; 477 m->smbus_no_migration_support = true; 478 m->alias = NULL; 479 pcmc->pvh_enabled = false; 480 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 481 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 482 } 483 484 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 485 pc_q35_3_1_machine_options); 486 487 static void pc_q35_3_0_machine_options(MachineClass *m) 488 { 489 pc_q35_3_1_machine_options(m); 490 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 491 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 492 } 493 494 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 495 pc_q35_3_0_machine_options); 496 497 static void pc_q35_2_12_machine_options(MachineClass *m) 498 { 499 pc_q35_3_0_machine_options(m); 500 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 501 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 502 } 503 504 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 505 pc_q35_2_12_machine_options); 506 507 static void pc_q35_2_11_machine_options(MachineClass *m) 508 { 509 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 510 511 pc_q35_2_12_machine_options(m); 512 pcmc->default_nic_model = "e1000"; 513 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 514 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 515 } 516 517 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 518 pc_q35_2_11_machine_options); 519 520 static void pc_q35_2_10_machine_options(MachineClass *m) 521 { 522 pc_q35_2_11_machine_options(m); 523 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 524 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 525 m->auto_enable_numa_with_memhp = false; 526 } 527 528 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 529 pc_q35_2_10_machine_options); 530 531 static void pc_q35_2_9_machine_options(MachineClass *m) 532 { 533 pc_q35_2_10_machine_options(m); 534 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 535 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 536 } 537 538 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 539 pc_q35_2_9_machine_options); 540 541 static void pc_q35_2_8_machine_options(MachineClass *m) 542 { 543 pc_q35_2_9_machine_options(m); 544 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 545 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 546 } 547 548 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 549 pc_q35_2_8_machine_options); 550 551 static void pc_q35_2_7_machine_options(MachineClass *m) 552 { 553 pc_q35_2_8_machine_options(m); 554 m->max_cpus = 255; 555 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 556 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 557 } 558 559 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 560 pc_q35_2_7_machine_options); 561 562 static void pc_q35_2_6_machine_options(MachineClass *m) 563 { 564 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 565 566 pc_q35_2_7_machine_options(m); 567 pcmc->legacy_cpu_hotplug = true; 568 pcmc->linuxboot_dma_enabled = false; 569 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 570 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 571 } 572 573 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 574 pc_q35_2_6_machine_options); 575 576 static void pc_q35_2_5_machine_options(MachineClass *m) 577 { 578 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 579 580 pc_q35_2_6_machine_options(m); 581 x86mc->save_tsc_khz = false; 582 m->legacy_fw_cfg_order = 1; 583 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 584 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 585 } 586 587 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 588 pc_q35_2_5_machine_options); 589 590 static void pc_q35_2_4_machine_options(MachineClass *m) 591 { 592 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 593 594 pc_q35_2_5_machine_options(m); 595 m->hw_version = "2.4.0"; 596 pcmc->broken_reserved_end = true; 597 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 598 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 599 } 600 601 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 602 pc_q35_2_4_machine_options); 603