1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/ide/pci.h" 43 #include "hw/ide/ahci.h" 44 #include "hw/usb.h" 45 #include "hw/cpu/icc_bus.h" 46 47 /* ICH9 AHCI has 6 ports */ 48 #define MAX_SATA_PORTS 6 49 50 static bool has_pvpanic; 51 static bool has_pci_info; 52 static bool has_acpi_build = true; 53 54 /* PC hardware initialisation */ 55 static void pc_q35_init(QEMUMachineInitArgs *args) 56 { 57 ram_addr_t below_4g_mem_size, above_4g_mem_size; 58 Q35PCIHost *q35_host; 59 PCIHostState *phb; 60 PCIBus *host_bus; 61 PCIDevice *lpc; 62 BusState *idebus[MAX_SATA_PORTS]; 63 ISADevice *rtc_state; 64 ISADevice *floppy; 65 MemoryRegion *pci_memory; 66 MemoryRegion *rom_memory; 67 MemoryRegion *ram_memory; 68 GSIState *gsi_state; 69 ISABus *isa_bus; 70 int pci_enabled = 1; 71 qemu_irq *cpu_irq; 72 qemu_irq *gsi; 73 qemu_irq *i8259; 74 int i; 75 ICH9LPCState *ich9_lpc; 76 PCIDevice *ahci; 77 DeviceState *icc_bridge; 78 PcGuestInfo *guest_info; 79 80 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 81 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 82 exit(1); 83 } 84 85 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 86 object_property_add_child(qdev_get_machine(), "icc-bridge", 87 OBJECT(icc_bridge), NULL); 88 89 pc_cpus_init(args->cpu_model, icc_bridge); 90 pc_acpi_init("q35-acpi-dsdt.aml"); 91 92 kvmclock_create(); 93 94 if (args->ram_size >= 0xb0000000) { 95 above_4g_mem_size = args->ram_size - 0xb0000000; 96 below_4g_mem_size = 0xb0000000; 97 } else { 98 above_4g_mem_size = 0; 99 below_4g_mem_size = args->ram_size; 100 } 101 102 /* pci enabled */ 103 if (pci_enabled) { 104 pci_memory = g_new(MemoryRegion, 1); 105 memory_region_init(pci_memory, NULL, "pci", INT64_MAX); 106 rom_memory = pci_memory; 107 } else { 108 pci_memory = NULL; 109 rom_memory = get_system_memory(); 110 } 111 112 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 113 guest_info->has_pci_info = has_pci_info; 114 guest_info->isapc_ram_fw = false; 115 guest_info->has_acpi_build = has_acpi_build; 116 117 /* allocate ram and load rom/bios */ 118 if (!xen_enabled()) { 119 pc_memory_init(get_system_memory(), 120 args->kernel_filename, args->kernel_cmdline, 121 args->initrd_filename, 122 below_4g_mem_size, above_4g_mem_size, 123 rom_memory, &ram_memory, guest_info); 124 } 125 126 /* irq lines */ 127 gsi_state = g_malloc0(sizeof(*gsi_state)); 128 if (kvm_irqchip_in_kernel()) { 129 kvm_pc_setup_irq_routing(pci_enabled); 130 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 131 GSI_NUM_PINS); 132 } else { 133 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 134 } 135 136 /* create pci host bus */ 137 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 138 139 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 140 q35_host->mch.ram_memory = ram_memory; 141 q35_host->mch.pci_address_space = pci_memory; 142 q35_host->mch.system_memory = get_system_memory(); 143 q35_host->mch.address_space_io = get_system_io(); 144 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 145 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 146 q35_host->mch.guest_info = guest_info; 147 /* pci */ 148 qdev_init_nofail(DEVICE(q35_host)); 149 phb = PCI_HOST_BRIDGE(q35_host); 150 host_bus = phb->bus; 151 /* create ISA bus */ 152 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 153 ICH9_LPC_FUNC), true, 154 TYPE_ICH9_LPC_DEVICE); 155 ich9_lpc = ICH9_LPC_DEVICE(lpc); 156 ich9_lpc->pic = gsi; 157 ich9_lpc->ioapic = gsi_state->ioapic_irq; 158 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 159 ICH9_LPC_NB_PIRQS); 160 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 161 isa_bus = ich9_lpc->isa_bus; 162 163 /*end early*/ 164 isa_bus_irqs(isa_bus, gsi); 165 166 if (kvm_irqchip_in_kernel()) { 167 i8259 = kvm_i8259_init(isa_bus); 168 } else if (xen_enabled()) { 169 i8259 = xen_interrupt_controller_init(); 170 } else { 171 cpu_irq = pc_allocate_cpu_irq(); 172 i8259 = i8259_init(isa_bus, cpu_irq[0]); 173 } 174 175 for (i = 0; i < ISA_NUM_IRQS; i++) { 176 gsi_state->i8259_irq[i] = i8259[i]; 177 } 178 if (pci_enabled) { 179 ioapic_init_gsi(gsi_state, NULL); 180 } 181 qdev_init_nofail(icc_bridge); 182 183 pc_register_ferr_irq(gsi[13]); 184 185 /* init basic PC hardware */ 186 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false); 187 188 /* connect pm stuff to lpc */ 189 ich9_lpc_pm_init(lpc); 190 191 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 192 ahci = pci_create_simple_multifunction(host_bus, 193 PCI_DEVFN(ICH9_SATA1_DEV, 194 ICH9_SATA1_FUNC), 195 true, "ich9-ahci"); 196 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 197 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 198 199 if (usb_enabled(false)) { 200 /* Should we create 6 UHCI according to ich9 spec? */ 201 ehci_create_ich9_with_companions(host_bus, 0x1d); 202 } 203 204 /* TODO: Populate SPD eeprom data. */ 205 smbus_eeprom_init(ich9_smb_init(host_bus, 206 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 207 0xb100), 208 8, NULL, 0); 209 210 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, args->boot_order, 211 floppy, idebus[0], idebus[1], rtc_state); 212 213 /* the rest devices to which pci devfn is automatically assigned */ 214 pc_vga_init(isa_bus, host_bus); 215 pc_nic_init(isa_bus, host_bus); 216 if (pci_enabled) { 217 pc_pci_device_init(host_bus); 218 } 219 220 if (has_pvpanic) { 221 pvpanic_init(isa_bus); 222 } 223 } 224 225 static void pc_compat_1_6(QEMUMachineInitArgs *args) 226 { 227 has_pci_info = false; 228 rom_file_in_ram = false; 229 has_acpi_build = false; 230 } 231 232 static void pc_compat_1_5(QEMUMachineInitArgs *args) 233 { 234 pc_compat_1_6(args); 235 has_pvpanic = true; 236 } 237 238 static void pc_compat_1_4(QEMUMachineInitArgs *args) 239 { 240 pc_compat_1_5(args); 241 has_pvpanic = false; 242 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 243 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 244 } 245 246 static void pc_q35_init_1_6(QEMUMachineInitArgs *args) 247 { 248 pc_compat_1_6(args); 249 pc_q35_init(args); 250 } 251 252 static void pc_q35_init_1_5(QEMUMachineInitArgs *args) 253 { 254 pc_compat_1_5(args); 255 pc_q35_init(args); 256 } 257 258 static void pc_q35_init_1_4(QEMUMachineInitArgs *args) 259 { 260 pc_compat_1_4(args); 261 pc_q35_init(args); 262 } 263 264 #define PC_Q35_MACHINE_OPTIONS \ 265 PC_DEFAULT_MACHINE_OPTIONS, \ 266 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 267 .hot_add_cpu = pc_hot_add_cpu 268 269 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 270 271 static QEMUMachine pc_q35_machine_v1_7 = { 272 PC_Q35_1_7_MACHINE_OPTIONS, 273 .name = "pc-q35-1.7", 274 .alias = "q35", 275 .init = pc_q35_init, 276 }; 277 278 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 279 280 static QEMUMachine pc_q35_machine_v1_6 = { 281 PC_Q35_1_6_MACHINE_OPTIONS, 282 .name = "pc-q35-1.6", 283 .init = pc_q35_init_1_6, 284 .compat_props = (GlobalProperty[]) { 285 PC_COMPAT_1_6, 286 { /* end of list */ } 287 }, 288 }; 289 290 static QEMUMachine pc_q35_machine_v1_5 = { 291 PC_Q35_1_6_MACHINE_OPTIONS, 292 .name = "pc-q35-1.5", 293 .init = pc_q35_init_1_5, 294 .compat_props = (GlobalProperty[]) { 295 PC_COMPAT_1_5, 296 { /* end of list */ } 297 }, 298 }; 299 300 #define PC_Q35_1_4_MACHINE_OPTIONS \ 301 PC_Q35_1_6_MACHINE_OPTIONS, \ 302 .hot_add_cpu = NULL 303 304 static QEMUMachine pc_q35_machine_v1_4 = { 305 PC_Q35_1_4_MACHINE_OPTIONS, 306 .name = "pc-q35-1.4", 307 .init = pc_q35_init_1_4, 308 .compat_props = (GlobalProperty[]) { 309 PC_COMPAT_1_4, 310 { /* end of list */ } 311 }, 312 }; 313 314 static void pc_q35_machine_init(void) 315 { 316 qemu_register_machine(&pc_q35_machine_v1_7); 317 qemu_register_machine(&pc_q35_machine_v1_6); 318 qemu_register_machine(&pc_q35_machine_v1_5); 319 qemu_register_machine(&pc_q35_machine_v1_4); 320 } 321 322 machine_init(pc_q35_machine_init); 323