1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 #include "qemu/error-report.h" 48 49 /* ICH9 AHCI has 6 ports */ 50 #define MAX_SATA_PORTS 6 51 52 static bool has_pci_info; 53 static bool has_acpi_build = true; 54 static bool smbios_defaults = true; 55 static bool smbios_legacy_mode; 56 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 57 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 58 * pages in the host. 59 */ 60 static bool gigabyte_align = true; 61 static bool has_reserved_memory = true; 62 63 /* PC hardware initialisation */ 64 static void pc_q35_init(MachineState *machine) 65 { 66 PCMachineState *pc_machine = PC_MACHINE(machine); 67 ram_addr_t below_4g_mem_size, above_4g_mem_size; 68 Q35PCIHost *q35_host; 69 PCIHostState *phb; 70 PCIBus *host_bus; 71 PCIDevice *lpc; 72 BusState *idebus[MAX_SATA_PORTS]; 73 ISADevice *rtc_state; 74 ISADevice *floppy; 75 MemoryRegion *pci_memory; 76 MemoryRegion *rom_memory; 77 MemoryRegion *ram_memory; 78 GSIState *gsi_state; 79 ISABus *isa_bus; 80 int pci_enabled = 1; 81 qemu_irq *cpu_irq; 82 qemu_irq *gsi; 83 qemu_irq *i8259; 84 int i; 85 ICH9LPCState *ich9_lpc; 86 PCIDevice *ahci; 87 DeviceState *icc_bridge; 88 PcGuestInfo *guest_info; 89 ram_addr_t lowmem; 90 91 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 92 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 93 * also known as MMCFG). 94 * If it doesn't, we need to split it in chunks below and above 4G. 95 * In any case, try to make sure that guest addresses aligned at 96 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 97 * For old machine types, use whatever split we used historically to avoid 98 * breaking migration. 99 */ 100 if (machine->ram_size >= 0xb0000000) { 101 lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 102 } else { 103 lowmem = 0xb0000000; 104 } 105 106 /* Handle the machine opt max-ram-below-4g. It is basicly doing 107 * min(qemu limit, user limit). 108 */ 109 if (lowmem > pc_machine->max_ram_below_4g) { 110 lowmem = pc_machine->max_ram_below_4g; 111 if (machine->ram_size - lowmem > lowmem && 112 lowmem & ((1ULL << 30) - 1)) { 113 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64 114 ") not a multiple of 1G; possible bad performance.", 115 pc_machine->max_ram_below_4g); 116 } 117 } 118 119 if (machine->ram_size >= lowmem) { 120 above_4g_mem_size = machine->ram_size - lowmem; 121 below_4g_mem_size = lowmem; 122 } else { 123 above_4g_mem_size = 0; 124 below_4g_mem_size = machine->ram_size; 125 } 126 127 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size, 128 &ram_memory) != 0) { 129 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 130 exit(1); 131 } 132 133 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 134 object_property_add_child(qdev_get_machine(), "icc-bridge", 135 OBJECT(icc_bridge), NULL); 136 137 pc_cpus_init(machine->cpu_model, icc_bridge); 138 pc_acpi_init("q35-acpi-dsdt.aml"); 139 140 kvmclock_create(); 141 142 /* pci enabled */ 143 if (pci_enabled) { 144 pci_memory = g_new(MemoryRegion, 1); 145 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 146 rom_memory = pci_memory; 147 } else { 148 pci_memory = NULL; 149 rom_memory = get_system_memory(); 150 } 151 152 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 153 guest_info->has_pci_info = has_pci_info; 154 guest_info->isapc_ram_fw = false; 155 guest_info->has_acpi_build = has_acpi_build; 156 guest_info->has_reserved_memory = has_reserved_memory; 157 158 if (smbios_defaults) { 159 MachineClass *mc = MACHINE_GET_CLASS(machine); 160 /* These values are guest ABI, do not change */ 161 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 162 mc->name, smbios_legacy_mode); 163 } 164 165 /* allocate ram and load rom/bios */ 166 if (!xen_enabled()) { 167 pc_memory_init(machine, get_system_memory(), 168 below_4g_mem_size, above_4g_mem_size, 169 rom_memory, &ram_memory, guest_info); 170 } 171 172 /* irq lines */ 173 gsi_state = g_malloc0(sizeof(*gsi_state)); 174 if (kvm_irqchip_in_kernel()) { 175 kvm_pc_setup_irq_routing(pci_enabled); 176 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 177 GSI_NUM_PINS); 178 } else { 179 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 180 } 181 182 /* create pci host bus */ 183 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 184 185 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 186 q35_host->mch.ram_memory = ram_memory; 187 q35_host->mch.pci_address_space = pci_memory; 188 q35_host->mch.system_memory = get_system_memory(); 189 q35_host->mch.address_space_io = get_system_io(); 190 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 191 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 192 q35_host->mch.guest_info = guest_info; 193 /* pci */ 194 qdev_init_nofail(DEVICE(q35_host)); 195 phb = PCI_HOST_BRIDGE(q35_host); 196 host_bus = phb->bus; 197 /* create ISA bus */ 198 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 199 ICH9_LPC_FUNC), true, 200 TYPE_ICH9_LPC_DEVICE); 201 202 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 203 TYPE_HOTPLUG_HANDLER, 204 (Object **)&pc_machine->acpi_dev, 205 object_property_allow_set_link, 206 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 207 object_property_set_link(OBJECT(machine), OBJECT(lpc), 208 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 209 210 ich9_lpc = ICH9_LPC_DEVICE(lpc); 211 ich9_lpc->pic = gsi; 212 ich9_lpc->ioapic = gsi_state->ioapic_irq; 213 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 214 ICH9_LPC_NB_PIRQS); 215 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 216 isa_bus = ich9_lpc->isa_bus; 217 218 /*end early*/ 219 isa_bus_irqs(isa_bus, gsi); 220 221 if (kvm_irqchip_in_kernel()) { 222 i8259 = kvm_i8259_init(isa_bus); 223 } else if (xen_enabled()) { 224 i8259 = xen_interrupt_controller_init(); 225 } else { 226 cpu_irq = pc_allocate_cpu_irq(); 227 i8259 = i8259_init(isa_bus, cpu_irq[0]); 228 } 229 230 for (i = 0; i < ISA_NUM_IRQS; i++) { 231 gsi_state->i8259_irq[i] = i8259[i]; 232 } 233 if (pci_enabled) { 234 ioapic_init_gsi(gsi_state, NULL); 235 } 236 qdev_init_nofail(icc_bridge); 237 238 pc_register_ferr_irq(gsi[13]); 239 240 /* init basic PC hardware */ 241 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104); 242 243 /* connect pm stuff to lpc */ 244 ich9_lpc_pm_init(lpc); 245 246 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 247 ahci = pci_create_simple_multifunction(host_bus, 248 PCI_DEVFN(ICH9_SATA1_DEV, 249 ICH9_SATA1_FUNC), 250 true, "ich9-ahci"); 251 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 252 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 253 254 if (usb_enabled(false)) { 255 /* Should we create 6 UHCI according to ich9 spec? */ 256 ehci_create_ich9_with_companions(host_bus, 0x1d); 257 } 258 259 /* TODO: Populate SPD eeprom data. */ 260 smbus_eeprom_init(ich9_smb_init(host_bus, 261 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 262 0xb100), 263 8, NULL, 0); 264 265 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 266 floppy, idebus[0], idebus[1], rtc_state); 267 268 /* the rest devices to which pci devfn is automatically assigned */ 269 pc_vga_init(isa_bus, host_bus); 270 pc_nic_init(isa_bus, host_bus); 271 if (pci_enabled) { 272 pc_pci_device_init(host_bus); 273 } 274 } 275 276 static void pc_compat_2_0(MachineState *machine) 277 { 278 smbios_legacy_mode = true; 279 has_reserved_memory = false; 280 } 281 282 static void pc_compat_1_7(MachineState *machine) 283 { 284 pc_compat_2_0(machine); 285 smbios_defaults = false; 286 gigabyte_align = false; 287 option_rom_has_mr = true; 288 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); 289 } 290 291 static void pc_compat_1_6(MachineState *machine) 292 { 293 pc_compat_1_7(machine); 294 has_pci_info = false; 295 rom_file_has_mr = false; 296 has_acpi_build = false; 297 } 298 299 static void pc_compat_1_5(MachineState *machine) 300 { 301 pc_compat_1_6(machine); 302 } 303 304 static void pc_compat_1_4(MachineState *machine) 305 { 306 pc_compat_1_5(machine); 307 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 308 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 309 } 310 311 static void pc_q35_init_2_0(MachineState *machine) 312 { 313 pc_compat_2_0(machine); 314 pc_q35_init(machine); 315 } 316 317 static void pc_q35_init_1_7(MachineState *machine) 318 { 319 pc_compat_1_7(machine); 320 pc_q35_init(machine); 321 } 322 323 static void pc_q35_init_1_6(MachineState *machine) 324 { 325 pc_compat_1_6(machine); 326 pc_q35_init(machine); 327 } 328 329 static void pc_q35_init_1_5(MachineState *machine) 330 { 331 pc_compat_1_5(machine); 332 pc_q35_init(machine); 333 } 334 335 static void pc_q35_init_1_4(MachineState *machine) 336 { 337 pc_compat_1_4(machine); 338 pc_q35_init(machine); 339 } 340 341 #define PC_Q35_MACHINE_OPTIONS \ 342 PC_DEFAULT_MACHINE_OPTIONS, \ 343 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 344 .hot_add_cpu = pc_hot_add_cpu 345 346 #define PC_Q35_2_1_MACHINE_OPTIONS \ 347 PC_Q35_MACHINE_OPTIONS, \ 348 .default_machine_opts = "firmware=bios-256k.bin" 349 350 static QEMUMachine pc_q35_machine_v2_1 = { 351 PC_Q35_2_1_MACHINE_OPTIONS, 352 .name = "pc-q35-2.1", 353 .alias = "q35", 354 .init = pc_q35_init, 355 }; 356 357 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS 358 359 static QEMUMachine pc_q35_machine_v2_0 = { 360 PC_Q35_2_0_MACHINE_OPTIONS, 361 .name = "pc-q35-2.0", 362 .init = pc_q35_init_2_0, 363 .compat_props = (GlobalProperty[]) { 364 PC_Q35_COMPAT_2_0, 365 { /* end of list */ } 366 }, 367 }; 368 369 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 370 371 static QEMUMachine pc_q35_machine_v1_7 = { 372 PC_Q35_1_7_MACHINE_OPTIONS, 373 .name = "pc-q35-1.7", 374 .init = pc_q35_init_1_7, 375 .compat_props = (GlobalProperty[]) { 376 PC_Q35_COMPAT_1_7, 377 { /* end of list */ } 378 }, 379 }; 380 381 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 382 383 static QEMUMachine pc_q35_machine_v1_6 = { 384 PC_Q35_1_6_MACHINE_OPTIONS, 385 .name = "pc-q35-1.6", 386 .init = pc_q35_init_1_6, 387 .compat_props = (GlobalProperty[]) { 388 PC_Q35_COMPAT_1_6, 389 { /* end of list */ } 390 }, 391 }; 392 393 static QEMUMachine pc_q35_machine_v1_5 = { 394 PC_Q35_1_6_MACHINE_OPTIONS, 395 .name = "pc-q35-1.5", 396 .init = pc_q35_init_1_5, 397 .compat_props = (GlobalProperty[]) { 398 PC_Q35_COMPAT_1_5, 399 { /* end of list */ } 400 }, 401 }; 402 403 #define PC_Q35_1_4_MACHINE_OPTIONS \ 404 PC_Q35_1_6_MACHINE_OPTIONS, \ 405 .hot_add_cpu = NULL 406 407 static QEMUMachine pc_q35_machine_v1_4 = { 408 PC_Q35_1_4_MACHINE_OPTIONS, 409 .name = "pc-q35-1.4", 410 .init = pc_q35_init_1_4, 411 .compat_props = (GlobalProperty[]) { 412 PC_Q35_COMPAT_1_4, 413 { /* end of list */ } 414 }, 415 }; 416 417 static void pc_q35_machine_init(void) 418 { 419 qemu_register_pc_machine(&pc_q35_machine_v2_1); 420 qemu_register_pc_machine(&pc_q35_machine_v2_0); 421 qemu_register_pc_machine(&pc_q35_machine_v1_7); 422 qemu_register_pc_machine(&pc_q35_machine_v1_6); 423 qemu_register_pc_machine(&pc_q35_machine_v1_5); 424 qemu_register_pc_machine(&pc_q35_machine_v1_4); 425 } 426 427 machine_init(pc_q35_machine_init); 428