1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/loader.h" 32 #include "sysemu/arch_init.h" 33 #include "hw/i2c/smbus.h" 34 #include "hw/boards.h" 35 #include "hw/timer/mc146818rtc.h" 36 #include "hw/xen/xen.h" 37 #include "sysemu/kvm.h" 38 #include "hw/kvm/clock.h" 39 #include "hw/pci-host/q35.h" 40 #include "exec/address-spaces.h" 41 #include "hw/i386/ich9.h" 42 #include "hw/i386/smbios.h" 43 #include "hw/ide/pci.h" 44 #include "hw/ide/ahci.h" 45 #include "hw/usb.h" 46 #include "hw/cpu/icc_bus.h" 47 48 /* ICH9 AHCI has 6 ports */ 49 #define MAX_SATA_PORTS 6 50 51 static bool has_pci_info; 52 static bool has_acpi_build = true; 53 static bool smbios_defaults = true; 54 static bool smbios_legacy_mode; 55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to 56 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte 57 * pages in the host. 58 */ 59 static bool gigabyte_align = true; 60 static bool has_reserved_memory = true; 61 62 /* PC hardware initialisation */ 63 static void pc_q35_init(MachineState *machine) 64 { 65 PCMachineState *pc_machine = PC_MACHINE(machine); 66 ram_addr_t below_4g_mem_size, above_4g_mem_size; 67 Q35PCIHost *q35_host; 68 PCIHostState *phb; 69 PCIBus *host_bus; 70 PCIDevice *lpc; 71 BusState *idebus[MAX_SATA_PORTS]; 72 ISADevice *rtc_state; 73 ISADevice *floppy; 74 MemoryRegion *pci_memory; 75 MemoryRegion *rom_memory; 76 MemoryRegion *ram_memory; 77 GSIState *gsi_state; 78 ISABus *isa_bus; 79 int pci_enabled = 1; 80 qemu_irq *cpu_irq; 81 qemu_irq *gsi; 82 qemu_irq *i8259; 83 int i; 84 ICH9LPCState *ich9_lpc; 85 PCIDevice *ahci; 86 DeviceState *icc_bridge; 87 PcGuestInfo *guest_info; 88 89 if (xen_enabled() && xen_hvm_init(&ram_memory) != 0) { 90 fprintf(stderr, "xen hardware virtual machine initialisation failed\n"); 91 exit(1); 92 } 93 94 icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); 95 object_property_add_child(qdev_get_machine(), "icc-bridge", 96 OBJECT(icc_bridge), NULL); 97 98 pc_cpus_init(machine->cpu_model, icc_bridge); 99 pc_acpi_init("q35-acpi-dsdt.aml"); 100 101 kvmclock_create(); 102 103 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 104 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 105 * also known as MMCFG). 106 * If it doesn't, we need to split it in chunks below and above 4G. 107 * In any case, try to make sure that guest addresses aligned at 108 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 109 * For old machine types, use whatever split we used historically to avoid 110 * breaking migration. 111 */ 112 if (machine->ram_size >= 0xb0000000) { 113 ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000; 114 above_4g_mem_size = machine->ram_size - lowmem; 115 below_4g_mem_size = lowmem; 116 } else { 117 above_4g_mem_size = 0; 118 below_4g_mem_size = machine->ram_size; 119 } 120 121 /* pci enabled */ 122 if (pci_enabled) { 123 pci_memory = g_new(MemoryRegion, 1); 124 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 125 rom_memory = pci_memory; 126 } else { 127 pci_memory = NULL; 128 rom_memory = get_system_memory(); 129 } 130 131 guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); 132 guest_info->has_pci_info = has_pci_info; 133 guest_info->isapc_ram_fw = false; 134 guest_info->has_acpi_build = has_acpi_build; 135 guest_info->has_reserved_memory = has_reserved_memory; 136 137 if (smbios_defaults) { 138 MachineClass *mc = MACHINE_GET_CLASS(machine); 139 /* These values are guest ABI, do not change */ 140 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)", 141 mc->name, smbios_legacy_mode); 142 } 143 144 /* allocate ram and load rom/bios */ 145 if (!xen_enabled()) { 146 pc_memory_init(get_system_memory(), 147 machine->kernel_filename, machine->kernel_cmdline, 148 machine->initrd_filename, 149 below_4g_mem_size, above_4g_mem_size, 150 rom_memory, &ram_memory, guest_info); 151 } 152 153 /* irq lines */ 154 gsi_state = g_malloc0(sizeof(*gsi_state)); 155 if (kvm_irqchip_in_kernel()) { 156 kvm_pc_setup_irq_routing(pci_enabled); 157 gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state, 158 GSI_NUM_PINS); 159 } else { 160 gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); 161 } 162 163 /* create pci host bus */ 164 q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 165 166 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL); 167 q35_host->mch.ram_memory = ram_memory; 168 q35_host->mch.pci_address_space = pci_memory; 169 q35_host->mch.system_memory = get_system_memory(); 170 q35_host->mch.address_space_io = get_system_io(); 171 q35_host->mch.below_4g_mem_size = below_4g_mem_size; 172 q35_host->mch.above_4g_mem_size = above_4g_mem_size; 173 q35_host->mch.guest_info = guest_info; 174 /* pci */ 175 qdev_init_nofail(DEVICE(q35_host)); 176 phb = PCI_HOST_BRIDGE(q35_host); 177 host_bus = phb->bus; 178 /* create ISA bus */ 179 lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, 180 ICH9_LPC_FUNC), true, 181 TYPE_ICH9_LPC_DEVICE); 182 183 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 184 TYPE_HOTPLUG_HANDLER, 185 (Object **)&pc_machine->acpi_dev, 186 object_property_allow_set_link, 187 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 188 object_property_set_link(OBJECT(machine), OBJECT(lpc), 189 PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 190 191 ich9_lpc = ICH9_LPC_DEVICE(lpc); 192 ich9_lpc->pic = gsi; 193 ich9_lpc->ioapic = gsi_state->ioapic_irq; 194 pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc, 195 ICH9_LPC_NB_PIRQS); 196 pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); 197 isa_bus = ich9_lpc->isa_bus; 198 199 /*end early*/ 200 isa_bus_irqs(isa_bus, gsi); 201 202 if (kvm_irqchip_in_kernel()) { 203 i8259 = kvm_i8259_init(isa_bus); 204 } else if (xen_enabled()) { 205 i8259 = xen_interrupt_controller_init(); 206 } else { 207 cpu_irq = pc_allocate_cpu_irq(); 208 i8259 = i8259_init(isa_bus, cpu_irq[0]); 209 } 210 211 for (i = 0; i < ISA_NUM_IRQS; i++) { 212 gsi_state->i8259_irq[i] = i8259[i]; 213 } 214 if (pci_enabled) { 215 ioapic_init_gsi(gsi_state, NULL); 216 } 217 qdev_init_nofail(icc_bridge); 218 219 pc_register_ferr_irq(gsi[13]); 220 221 /* init basic PC hardware */ 222 pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false, 0xff0104); 223 224 /* connect pm stuff to lpc */ 225 ich9_lpc_pm_init(lpc); 226 227 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 228 ahci = pci_create_simple_multifunction(host_bus, 229 PCI_DEVFN(ICH9_SATA1_DEV, 230 ICH9_SATA1_FUNC), 231 true, "ich9-ahci"); 232 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 233 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 234 235 if (usb_enabled(false)) { 236 /* Should we create 6 UHCI according to ich9 spec? */ 237 ehci_create_ich9_with_companions(host_bus, 0x1d); 238 } 239 240 /* TODO: Populate SPD eeprom data. */ 241 smbus_eeprom_init(ich9_smb_init(host_bus, 242 PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), 243 0xb100), 244 8, NULL, 0); 245 246 pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, 247 floppy, idebus[0], idebus[1], rtc_state); 248 249 /* the rest devices to which pci devfn is automatically assigned */ 250 pc_vga_init(isa_bus, host_bus); 251 pc_nic_init(isa_bus, host_bus); 252 if (pci_enabled) { 253 pc_pci_device_init(host_bus); 254 } 255 } 256 257 static void pc_compat_2_0(MachineState *machine) 258 { 259 smbios_legacy_mode = true; 260 has_reserved_memory = false; 261 } 262 263 static void pc_compat_1_7(MachineState *machine) 264 { 265 pc_compat_2_0(machine); 266 smbios_defaults = false; 267 gigabyte_align = false; 268 option_rom_has_mr = true; 269 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); 270 } 271 272 static void pc_compat_1_6(MachineState *machine) 273 { 274 pc_compat_1_7(machine); 275 has_pci_info = false; 276 rom_file_has_mr = false; 277 has_acpi_build = false; 278 } 279 280 static void pc_compat_1_5(MachineState *machine) 281 { 282 pc_compat_1_6(machine); 283 } 284 285 static void pc_compat_1_4(MachineState *machine) 286 { 287 pc_compat_1_5(machine); 288 x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); 289 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); 290 } 291 292 static void pc_q35_init_2_0(MachineState *machine) 293 { 294 pc_compat_2_0(machine); 295 pc_q35_init(machine); 296 } 297 298 static void pc_q35_init_1_7(MachineState *machine) 299 { 300 pc_compat_1_7(machine); 301 pc_q35_init(machine); 302 } 303 304 static void pc_q35_init_1_6(MachineState *machine) 305 { 306 pc_compat_1_6(machine); 307 pc_q35_init(machine); 308 } 309 310 static void pc_q35_init_1_5(MachineState *machine) 311 { 312 pc_compat_1_5(machine); 313 pc_q35_init(machine); 314 } 315 316 static void pc_q35_init_1_4(MachineState *machine) 317 { 318 pc_compat_1_4(machine); 319 pc_q35_init(machine); 320 } 321 322 #define PC_Q35_MACHINE_OPTIONS \ 323 PC_DEFAULT_MACHINE_OPTIONS, \ 324 .desc = "Standard PC (Q35 + ICH9, 2009)", \ 325 .hot_add_cpu = pc_hot_add_cpu 326 327 #define PC_Q35_2_1_MACHINE_OPTIONS \ 328 PC_Q35_MACHINE_OPTIONS, \ 329 .default_machine_opts = "firmware=bios-256k.bin" 330 331 static QEMUMachine pc_q35_machine_v2_1 = { 332 PC_Q35_2_1_MACHINE_OPTIONS, 333 .name = "pc-q35-2.1", 334 .alias = "q35", 335 .init = pc_q35_init, 336 }; 337 338 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS 339 340 static QEMUMachine pc_q35_machine_v2_0 = { 341 PC_Q35_2_0_MACHINE_OPTIONS, 342 .name = "pc-q35-2.0", 343 .init = pc_q35_init_2_0, 344 .compat_props = (GlobalProperty[]) { 345 PC_Q35_COMPAT_2_0, 346 { /* end of list */ } 347 }, 348 }; 349 350 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 351 352 static QEMUMachine pc_q35_machine_v1_7 = { 353 PC_Q35_1_7_MACHINE_OPTIONS, 354 .name = "pc-q35-1.7", 355 .init = pc_q35_init_1_7, 356 .compat_props = (GlobalProperty[]) { 357 PC_Q35_COMPAT_1_7, 358 { /* end of list */ } 359 }, 360 }; 361 362 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS 363 364 static QEMUMachine pc_q35_machine_v1_6 = { 365 PC_Q35_1_6_MACHINE_OPTIONS, 366 .name = "pc-q35-1.6", 367 .init = pc_q35_init_1_6, 368 .compat_props = (GlobalProperty[]) { 369 PC_Q35_COMPAT_1_6, 370 { /* end of list */ } 371 }, 372 }; 373 374 static QEMUMachine pc_q35_machine_v1_5 = { 375 PC_Q35_1_6_MACHINE_OPTIONS, 376 .name = "pc-q35-1.5", 377 .init = pc_q35_init_1_5, 378 .compat_props = (GlobalProperty[]) { 379 PC_Q35_COMPAT_1_5, 380 { /* end of list */ } 381 }, 382 }; 383 384 #define PC_Q35_1_4_MACHINE_OPTIONS \ 385 PC_Q35_1_6_MACHINE_OPTIONS, \ 386 .hot_add_cpu = NULL 387 388 static QEMUMachine pc_q35_machine_v1_4 = { 389 PC_Q35_1_4_MACHINE_OPTIONS, 390 .name = "pc-q35-1.4", 391 .init = pc_q35_init_1_4, 392 .compat_props = (GlobalProperty[]) { 393 PC_COMPAT_1_4, 394 { /* end of list */ } 395 }, 396 }; 397 398 static void pc_q35_machine_init(void) 399 { 400 qemu_register_pc_machine(&pc_q35_machine_v2_1); 401 qemu_register_pc_machine(&pc_q35_machine_v2_0); 402 qemu_register_pc_machine(&pc_q35_machine_v1_7); 403 qemu_register_pc_machine(&pc_q35_machine_v1_6); 404 qemu_register_pc_machine(&pc_q35_machine_v1_5); 405 qemu_register_pc_machine(&pc_q35_machine_v1_4); 406 } 407 408 machine_init(pc_q35_machine_init); 409