1 /* 2 * Q35 chipset based pc system emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2009, 2010 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on pc.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/units.h" 33 #include "hw/char/parallel-isa.h" 34 #include "hw/loader.h" 35 #include "hw/i2c/smbus_eeprom.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/kvm.h" 39 #include "hw/i386/kvm/clock.h" 40 #include "hw/pci-host/q35.h" 41 #include "hw/pci/pcie_port.h" 42 #include "hw/qdev-properties.h" 43 #include "hw/i386/x86.h" 44 #include "hw/i386/pc.h" 45 #include "hw/i386/amd_iommu.h" 46 #include "hw/i386/intel_iommu.h" 47 #include "hw/display/ramfb.h" 48 #include "hw/firmware/smbios.h" 49 #include "hw/ide/pci.h" 50 #include "hw/ide/ahci.h" 51 #include "hw/intc/ioapic.h" 52 #include "hw/southbridge/ich9.h" 53 #include "hw/usb.h" 54 #include "hw/usb/hcd-uhci.h" 55 #include "qapi/error.h" 56 #include "qemu/error-report.h" 57 #include "sysemu/numa.h" 58 #include "hw/hyperv/vmbus-bridge.h" 59 #include "hw/mem/nvdimm.h" 60 #include "hw/i386/acpi-build.h" 61 #include "target/i386/cpu.h" 62 63 /* ICH9 AHCI has 6 ports */ 64 #define MAX_SATA_PORTS 6 65 66 struct ehci_companions { 67 const char *name; 68 int func; 69 int port; 70 }; 71 72 static const struct ehci_companions ich9_1d[] = { 73 { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 }, 74 { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 }, 75 { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 }, 76 }; 77 78 static const struct ehci_companions ich9_1a[] = { 79 { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 }, 80 { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 }, 81 { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 }, 82 }; 83 84 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) 85 { 86 const struct ehci_companions *comp; 87 PCIDevice *ehci, *uhci; 88 BusState *usbbus; 89 const char *name; 90 int i; 91 92 switch (slot) { 93 case 0x1d: 94 name = "ich9-usb-ehci1"; 95 comp = ich9_1d; 96 break; 97 case 0x1a: 98 name = "ich9-usb-ehci2"; 99 comp = ich9_1a; 100 break; 101 default: 102 return -1; 103 } 104 105 ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name); 106 pci_realize_and_unref(ehci, bus, &error_fatal); 107 usbbus = QLIST_FIRST(&ehci->qdev.child_bus); 108 109 for (i = 0; i < 3; i++) { 110 uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), 111 comp[i].name); 112 qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); 113 qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); 114 pci_realize_and_unref(uhci, bus, &error_fatal); 115 } 116 return 0; 117 } 118 119 /* PC hardware initialisation */ 120 static void pc_q35_init(MachineState *machine) 121 { 122 PCMachineState *pcms = PC_MACHINE(machine); 123 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 124 X86MachineState *x86ms = X86_MACHINE(machine); 125 Object *phb; 126 PCIBus *host_bus; 127 PCIDevice *lpc; 128 DeviceState *lpc_dev; 129 BusState *idebus[MAX_SATA_PORTS]; 130 ISADevice *rtc_state; 131 MemoryRegion *system_memory = get_system_memory(); 132 MemoryRegion *system_io = get_system_io(); 133 MemoryRegion *pci_memory; 134 MemoryRegion *rom_memory; 135 GSIState *gsi_state; 136 ISABus *isa_bus; 137 int i; 138 PCIDevice *ahci; 139 ram_addr_t lowmem; 140 DriveInfo *hd[MAX_SATA_PORTS]; 141 MachineClass *mc = MACHINE_GET_CLASS(machine); 142 bool acpi_pcihp; 143 bool keep_pci_slot_hpc; 144 uint64_t pci_hole64_size = 0; 145 146 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory 147 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping 148 * also known as MMCFG). 149 * If it doesn't, we need to split it in chunks below and above 4G. 150 * In any case, try to make sure that guest addresses aligned at 151 * 1G boundaries get mapped to host addresses aligned at 1G boundaries. 152 */ 153 if (machine->ram_size >= 0xb0000000) { 154 lowmem = 0x80000000; 155 } else { 156 lowmem = 0xb0000000; 157 } 158 159 /* Handle the machine opt max-ram-below-4g. It is basically doing 160 * min(qemu limit, user limit). 161 */ 162 if (!pcms->max_ram_below_4g) { 163 pcms->max_ram_below_4g = 4 * GiB; 164 } 165 if (lowmem > pcms->max_ram_below_4g) { 166 lowmem = pcms->max_ram_below_4g; 167 if (machine->ram_size - lowmem > lowmem && 168 lowmem & (1 * GiB - 1)) { 169 warn_report("There is possibly poor performance as the ram size " 170 " (0x%" PRIx64 ") is more then twice the size of" 171 " max-ram-below-4g (%"PRIu64") and" 172 " max-ram-below-4g is not a multiple of 1G.", 173 (uint64_t)machine->ram_size, pcms->max_ram_below_4g); 174 } 175 } 176 177 if (machine->ram_size >= lowmem) { 178 x86ms->above_4g_mem_size = machine->ram_size - lowmem; 179 x86ms->below_4g_mem_size = lowmem; 180 } else { 181 x86ms->above_4g_mem_size = 0; 182 x86ms->below_4g_mem_size = machine->ram_size; 183 } 184 185 pc_machine_init_sgx_epc(pcms); 186 x86_cpus_init(x86ms, pcmc->default_cpu_version); 187 188 if (kvm_enabled()) { 189 kvmclock_create(pcmc->kvmclock_create_always); 190 } 191 192 /* pci enabled */ 193 if (pcmc->pci_enabled) { 194 pci_memory = g_new(MemoryRegion, 1); 195 memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); 196 rom_memory = pci_memory; 197 } else { 198 pci_memory = NULL; 199 rom_memory = system_memory; 200 } 201 202 pc_guest_info_init(pcms); 203 204 if (pcmc->smbios_defaults) { 205 /* These values are guest ABI, do not change */ 206 smbios_set_defaults("QEMU", mc->desc, 207 mc->name, pcmc->smbios_legacy_mode, 208 pcmc->smbios_uuid_encoded, 209 pcms->smbios_entry_point_type); 210 } 211 212 /* create pci host bus */ 213 phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); 214 215 if (pcmc->pci_enabled) { 216 pci_hole64_size = object_property_get_uint(phb, 217 PCI_HOST_PROP_PCI_HOLE64_SIZE, 218 &error_abort); 219 } 220 221 /* allocate ram and load rom/bios */ 222 pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); 223 224 object_property_add_child(OBJECT(machine), "q35", phb); 225 object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, 226 OBJECT(machine->ram), NULL); 227 object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, 228 OBJECT(pci_memory), NULL); 229 object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, 230 OBJECT(system_memory), NULL); 231 object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, 232 OBJECT(system_io), NULL); 233 object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, 234 x86ms->below_4g_mem_size, NULL); 235 object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, 236 x86ms->above_4g_mem_size, NULL); 237 object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU, 238 pcms->default_bus_bypass_iommu, NULL); 239 sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); 240 241 /* pci */ 242 host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); 243 pcms->bus = host_bus; 244 245 /* irq lines */ 246 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); 247 248 /* create ISA bus */ 249 lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), 250 TYPE_ICH9_LPC_DEVICE); 251 qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", 252 x86_machine_is_smm_enabled(x86ms)); 253 lpc_dev = DEVICE(lpc); 254 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 255 qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]); 256 } 257 pci_realize_and_unref(lpc, host_bus, &error_fatal); 258 259 rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); 260 261 object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 262 TYPE_HOTPLUG_HANDLER, 263 (Object **)&x86ms->acpi_dev, 264 object_property_allow_set_link, 265 OBJ_PROP_LINK_STRONG); 266 object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 267 OBJECT(lpc), &error_abort); 268 269 acpi_pcihp = object_property_get_bool(OBJECT(lpc), 270 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, 271 NULL); 272 273 keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc), 274 "x-keep-pci-slot-hpc", 275 NULL); 276 277 if (!keep_pci_slot_hpc && acpi_pcihp) { 278 object_register_sugar_prop(TYPE_PCIE_SLOT, 279 "x-do-not-expose-native-hotplug-cap", 280 "true", true); 281 } 282 283 isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0")); 284 285 if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { 286 pc_i8259_create(isa_bus, gsi_state->i8259_irq); 287 } 288 289 if (pcmc->pci_enabled) { 290 ioapic_init_gsi(gsi_state, "q35"); 291 } 292 293 if (tcg_enabled()) { 294 x86_register_ferr_irq(x86ms->gsi[13]); 295 } 296 297 assert(pcms->vmport != ON_OFF_AUTO__MAX); 298 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 299 pcms->vmport = ON_OFF_AUTO_ON; 300 } 301 302 /* init basic PC hardware */ 303 pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 304 0xff0104); 305 306 if (pcms->sata_enabled) { 307 /* ahci and SATA device, for q35 1 ahci controller is built-in */ 308 ahci = pci_create_simple_multifunction(host_bus, 309 PCI_DEVFN(ICH9_SATA1_DEV, 310 ICH9_SATA1_FUNC), 311 "ich9-ahci"); 312 idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0"); 313 idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1"); 314 g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci)); 315 ide_drive_get(hd, ahci_get_num_ports(ahci)); 316 ahci_ide_create_devs(ahci, hd); 317 } else { 318 idebus[0] = idebus[1] = NULL; 319 } 320 321 if (machine_usb(machine)) { 322 /* Should we create 6 UHCI according to ich9 spec? */ 323 ehci_create_ich9_with_companions(host_bus, 0x1d); 324 } 325 326 if (pcms->smbus_enabled) { 327 PCIDevice *smb; 328 329 /* TODO: Populate SPD eeprom data. */ 330 smb = pci_create_simple_multifunction(host_bus, 331 PCI_DEVFN(ICH9_SMB_DEV, 332 ICH9_SMB_FUNC), 333 TYPE_ICH9_SMB_DEVICE); 334 pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); 335 336 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); 337 } 338 339 pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); 340 341 /* the rest devices to which pci devfn is automatically assigned */ 342 pc_vga_init(isa_bus, host_bus); 343 pc_nic_init(pcmc, isa_bus, host_bus, pcms->xenbus); 344 345 if (machine->nvdimms_state->is_enabled) { 346 nvdimm_init_acpi_state(machine->nvdimms_state, system_io, 347 x86_nvdimm_acpi_dsmio, 348 x86ms->fw_cfg, OBJECT(pcms)); 349 } 350 } 351 352 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \ 353 static void pc_init_##suffix(MachineState *machine) \ 354 { \ 355 void (*compat)(MachineState *m) = (compatfn); \ 356 if (compat) { \ 357 compat(machine); \ 358 } \ 359 pc_q35_init(machine); \ 360 } \ 361 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn) 362 363 364 static void pc_q35_machine_options(MachineClass *m) 365 { 366 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 367 pcmc->pci_root_uid = 0; 368 pcmc->default_cpu_version = 1; 369 370 m->family = "pc_q35"; 371 m->desc = "Standard PC (Q35 + ICH9, 2009)"; 372 m->units_per_default_bus = 1; 373 m->default_machine_opts = "firmware=bios-256k.bin"; 374 m->default_display = "std"; 375 m->default_nic = "e1000e"; 376 m->default_kernel_irqchip_split = false; 377 m->no_floppy = 1; 378 m->max_cpus = 1024; 379 m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 380 machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE); 381 machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE); 382 machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); 383 machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE); 384 } 385 386 static void pc_q35_9_0_machine_options(MachineClass *m) 387 { 388 pc_q35_machine_options(m); 389 m->alias = "q35"; 390 } 391 392 DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, 393 pc_q35_9_0_machine_options); 394 395 static void pc_q35_8_2_machine_options(MachineClass *m) 396 { 397 pc_q35_9_0_machine_options(m); 398 m->alias = NULL; 399 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); 400 compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); 401 } 402 403 DEFINE_Q35_MACHINE(v8_2, "pc-q35-8.2", NULL, 404 pc_q35_8_2_machine_options); 405 406 static void pc_q35_8_1_machine_options(MachineClass *m) 407 { 408 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 409 pc_q35_8_2_machine_options(m); 410 m->alias = NULL; 411 pcmc->broken_32bit_mem_addr_check = true; 412 compat_props_add(m->compat_props, hw_compat_8_1, hw_compat_8_1_len); 413 compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len); 414 } 415 416 DEFINE_Q35_MACHINE(v8_1, "pc-q35-8.1", NULL, 417 pc_q35_8_1_machine_options); 418 419 static void pc_q35_8_0_machine_options(MachineClass *m) 420 { 421 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 422 423 pc_q35_8_1_machine_options(m); 424 compat_props_add(m->compat_props, hw_compat_8_0, hw_compat_8_0_len); 425 compat_props_add(m->compat_props, pc_compat_8_0, pc_compat_8_0_len); 426 427 /* For pc-q35-8.0 and older, use SMBIOS 2.8 by default */ 428 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 429 m->max_cpus = 288; 430 } 431 432 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL, 433 pc_q35_8_0_machine_options); 434 435 static void pc_q35_7_2_machine_options(MachineClass *m) 436 { 437 pc_q35_8_0_machine_options(m); 438 compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len); 439 compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len); 440 } 441 442 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL, 443 pc_q35_7_2_machine_options); 444 445 static void pc_q35_7_1_machine_options(MachineClass *m) 446 { 447 pc_q35_7_2_machine_options(m); 448 compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len); 449 compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len); 450 } 451 452 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, 453 pc_q35_7_1_machine_options); 454 455 static void pc_q35_7_0_machine_options(MachineClass *m) 456 { 457 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 458 pc_q35_7_1_machine_options(m); 459 pcmc->enforce_amd_1tb_hole = false; 460 compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); 461 compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); 462 } 463 464 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL, 465 pc_q35_7_0_machine_options); 466 467 static void pc_q35_6_2_machine_options(MachineClass *m) 468 { 469 pc_q35_7_0_machine_options(m); 470 compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len); 471 compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len); 472 } 473 474 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL, 475 pc_q35_6_2_machine_options); 476 477 static void pc_q35_6_1_machine_options(MachineClass *m) 478 { 479 pc_q35_6_2_machine_options(m); 480 compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len); 481 compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len); 482 m->smp_props.prefer_sockets = true; 483 } 484 485 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL, 486 pc_q35_6_1_machine_options); 487 488 static void pc_q35_6_0_machine_options(MachineClass *m) 489 { 490 pc_q35_6_1_machine_options(m); 491 compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len); 492 compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len); 493 } 494 495 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL, 496 pc_q35_6_0_machine_options); 497 498 static void pc_q35_5_2_machine_options(MachineClass *m) 499 { 500 pc_q35_6_0_machine_options(m); 501 compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len); 502 compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len); 503 } 504 505 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL, 506 pc_q35_5_2_machine_options); 507 508 static void pc_q35_5_1_machine_options(MachineClass *m) 509 { 510 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 511 512 pc_q35_5_2_machine_options(m); 513 compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len); 514 compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len); 515 pcmc->kvmclock_create_always = false; 516 pcmc->pci_root_uid = 1; 517 } 518 519 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL, 520 pc_q35_5_1_machine_options); 521 522 static void pc_q35_5_0_machine_options(MachineClass *m) 523 { 524 pc_q35_5_1_machine_options(m); 525 m->numa_mem_supported = true; 526 compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); 527 compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); 528 m->auto_enable_numa_with_memdev = false; 529 } 530 531 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, 532 pc_q35_5_0_machine_options); 533 534 static void pc_q35_4_2_machine_options(MachineClass *m) 535 { 536 pc_q35_5_0_machine_options(m); 537 compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); 538 compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); 539 } 540 541 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, 542 pc_q35_4_2_machine_options); 543 544 static void pc_q35_4_1_machine_options(MachineClass *m) 545 { 546 pc_q35_4_2_machine_options(m); 547 compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); 548 compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); 549 } 550 551 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL, 552 pc_q35_4_1_machine_options); 553 554 static void pc_q35_4_0_1_machine_options(MachineClass *m) 555 { 556 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 557 pc_q35_4_1_machine_options(m); 558 pcmc->default_cpu_version = CPU_VERSION_LEGACY; 559 /* 560 * This is the default machine for the 4.0-stable branch. It is basically 561 * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the 562 * 4.0 compat props. 563 */ 564 compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); 565 compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); 566 } 567 568 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, 569 pc_q35_4_0_1_machine_options); 570 571 static void pc_q35_4_0_machine_options(MachineClass *m) 572 { 573 pc_q35_4_0_1_machine_options(m); 574 m->default_kernel_irqchip_split = true; 575 /* Compat props are applied by the 4.0.1 machine */ 576 } 577 578 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, 579 pc_q35_4_0_machine_options); 580 581 static void pc_q35_3_1_machine_options(MachineClass *m) 582 { 583 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 584 585 pc_q35_4_0_machine_options(m); 586 m->default_kernel_irqchip_split = false; 587 m->smbus_no_migration_support = true; 588 pcmc->pvh_enabled = false; 589 compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); 590 compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); 591 } 592 593 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, 594 pc_q35_3_1_machine_options); 595 596 static void pc_q35_3_0_machine_options(MachineClass *m) 597 { 598 pc_q35_3_1_machine_options(m); 599 compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); 600 compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); 601 } 602 603 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, 604 pc_q35_3_0_machine_options); 605 606 static void pc_q35_2_12_machine_options(MachineClass *m) 607 { 608 pc_q35_3_0_machine_options(m); 609 compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); 610 compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); 611 } 612 613 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, 614 pc_q35_2_12_machine_options); 615 616 static void pc_q35_2_11_machine_options(MachineClass *m) 617 { 618 pc_q35_2_12_machine_options(m); 619 m->default_nic = "e1000"; 620 compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); 621 compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); 622 } 623 624 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, 625 pc_q35_2_11_machine_options); 626 627 static void pc_q35_2_10_machine_options(MachineClass *m) 628 { 629 pc_q35_2_11_machine_options(m); 630 compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); 631 compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); 632 m->auto_enable_numa_with_memhp = false; 633 } 634 635 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, 636 pc_q35_2_10_machine_options); 637 638 static void pc_q35_2_9_machine_options(MachineClass *m) 639 { 640 pc_q35_2_10_machine_options(m); 641 compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); 642 compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); 643 } 644 645 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, 646 pc_q35_2_9_machine_options); 647 648 static void pc_q35_2_8_machine_options(MachineClass *m) 649 { 650 pc_q35_2_9_machine_options(m); 651 compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); 652 compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); 653 } 654 655 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, 656 pc_q35_2_8_machine_options); 657 658 static void pc_q35_2_7_machine_options(MachineClass *m) 659 { 660 pc_q35_2_8_machine_options(m); 661 m->max_cpus = 255; 662 compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); 663 compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); 664 } 665 666 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, 667 pc_q35_2_7_machine_options); 668 669 static void pc_q35_2_6_machine_options(MachineClass *m) 670 { 671 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 672 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 673 674 pc_q35_2_7_machine_options(m); 675 pcmc->legacy_cpu_hotplug = true; 676 x86mc->fwcfg_dma_enabled = false; 677 compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); 678 compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); 679 } 680 681 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, 682 pc_q35_2_6_machine_options); 683 684 static void pc_q35_2_5_machine_options(MachineClass *m) 685 { 686 X86MachineClass *x86mc = X86_MACHINE_CLASS(m); 687 688 pc_q35_2_6_machine_options(m); 689 x86mc->save_tsc_khz = false; 690 m->legacy_fw_cfg_order = 1; 691 compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); 692 compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); 693 } 694 695 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, 696 pc_q35_2_5_machine_options); 697 698 static void pc_q35_2_4_machine_options(MachineClass *m) 699 { 700 PCMachineClass *pcmc = PC_MACHINE_CLASS(m); 701 702 pc_q35_2_5_machine_options(m); 703 m->hw_version = "2.4.0"; 704 pcmc->broken_reserved_end = true; 705 compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); 706 compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); 707 } 708 709 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, 710 pc_q35_2_4_machine_options); 711