1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "migration/vmstate.h" 45 #include "multiboot.h" 46 #include "hw/rtc/mc146818rtc.h" 47 #include "hw/dma/i8257.h" 48 #include "hw/timer/i8254.h" 49 #include "hw/input/i8042.h" 50 #include "hw/irq.h" 51 #include "hw/audio/pcspk.h" 52 #include "hw/pci/msi.h" 53 #include "hw/sysbus.h" 54 #include "sysemu/sysemu.h" 55 #include "sysemu/tcg.h" 56 #include "sysemu/numa.h" 57 #include "sysemu/kvm.h" 58 #include "sysemu/qtest.h" 59 #include "sysemu/reset.h" 60 #include "sysemu/runstate.h" 61 #include "kvm_i386.h" 62 #include "hw/xen/xen.h" 63 #include "hw/xen/start_info.h" 64 #include "ui/qemu-spice.h" 65 #include "exec/memory.h" 66 #include "exec/address-spaces.h" 67 #include "sysemu/arch_init.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "hw/boards.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/visitor.h" 81 #include "hw/core/cpu.h" 82 #include "hw/usb.h" 83 #include "hw/i386/intel_iommu.h" 84 #include "hw/net/ne2000-isa.h" 85 #include "standard-headers/asm-x86/bootparam.h" 86 #include "hw/virtio/virtio-pmem-pci.h" 87 #include "hw/mem/memory-device.h" 88 #include "sysemu/replay.h" 89 #include "qapi/qmp/qerror.h" 90 #include "config-devices.h" 91 #include "e820_memory_layout.h" 92 #include "fw_cfg.h" 93 94 /* debug PC/ISA interrupts */ 95 //#define DEBUG_IRQ 96 97 #ifdef DEBUG_IRQ 98 #define DPRINTF(fmt, ...) \ 99 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 100 #else 101 #define DPRINTF(fmt, ...) 102 #endif 103 104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 105 106 GlobalProperty pc_compat_4_2[] = {}; 107 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 108 109 GlobalProperty pc_compat_4_1[] = {}; 110 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 111 112 GlobalProperty pc_compat_4_0[] = {}; 113 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 114 115 GlobalProperty pc_compat_3_1[] = { 116 { "intel-iommu", "dma-drain", "off" }, 117 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 118 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 119 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 120 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 121 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 122 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 123 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 124 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 125 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 126 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 127 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 128 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 129 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 130 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 131 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 136 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 137 }; 138 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 139 140 GlobalProperty pc_compat_3_0[] = { 141 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 142 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 143 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 144 }; 145 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 146 147 GlobalProperty pc_compat_2_12[] = { 148 { TYPE_X86_CPU, "legacy-cache", "on" }, 149 { TYPE_X86_CPU, "topoext", "off" }, 150 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 151 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 152 }; 153 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 154 155 GlobalProperty pc_compat_2_11[] = { 156 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 157 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 158 }; 159 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 160 161 GlobalProperty pc_compat_2_10[] = { 162 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 163 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 164 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 165 }; 166 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 167 168 GlobalProperty pc_compat_2_9[] = { 169 { "mch", "extended-tseg-mbytes", "0" }, 170 }; 171 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 172 173 GlobalProperty pc_compat_2_8[] = { 174 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 175 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 176 { "ICH9-LPC", "x-smi-broadcast", "off" }, 177 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 178 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 179 }; 180 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 181 182 GlobalProperty pc_compat_2_7[] = { 183 { TYPE_X86_CPU, "l3-cache", "off" }, 184 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 185 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 186 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 187 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 188 { "isa-pcspk", "migrate", "off" }, 189 }; 190 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 191 192 GlobalProperty pc_compat_2_6[] = { 193 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 194 { "vmxnet3", "romfile", "" }, 195 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 196 { "apic-common", "legacy-instance-id", "on", } 197 }; 198 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 199 200 GlobalProperty pc_compat_2_5[] = {}; 201 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 202 203 GlobalProperty pc_compat_2_4[] = { 204 PC_CPU_MODEL_IDS("2.4.0") 205 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 206 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 207 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 208 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 209 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 210 { TYPE_X86_CPU, "check", "off" }, 211 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 212 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 213 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 214 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 215 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 216 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 217 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 218 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 219 }; 220 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 221 222 GlobalProperty pc_compat_2_3[] = { 223 PC_CPU_MODEL_IDS("2.3.0") 224 { TYPE_X86_CPU, "arat", "off" }, 225 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 226 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 227 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 228 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 229 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 230 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 231 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 232 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 233 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 234 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 235 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 244 }; 245 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 246 247 GlobalProperty pc_compat_2_2[] = { 248 PC_CPU_MODEL_IDS("2.2.0") 249 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 250 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 251 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 264 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 265 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 266 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 267 }; 268 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 269 270 GlobalProperty pc_compat_2_1[] = { 271 PC_CPU_MODEL_IDS("2.1.0") 272 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 273 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 274 }; 275 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 276 277 GlobalProperty pc_compat_2_0[] = { 278 PC_CPU_MODEL_IDS("2.0.0") 279 { "virtio-scsi-pci", "any_layout", "off" }, 280 { "PIIX4_PM", "memory-hotplug-support", "off" }, 281 { "apic", "version", "0x11" }, 282 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 283 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 284 { "pci-serial", "prog_if", "0" }, 285 { "pci-serial-2x", "prog_if", "0" }, 286 { "pci-serial-4x", "prog_if", "0" }, 287 { "virtio-net-pci", "guest_announce", "off" }, 288 { "ICH9-LPC", "memory-hotplug-support", "off" }, 289 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 290 { "ioh3420", COMPAT_PROP_PCP, "off" }, 291 }; 292 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 293 294 GlobalProperty pc_compat_1_7[] = { 295 PC_CPU_MODEL_IDS("1.7.0") 296 { TYPE_USB_DEVICE, "msos-desc", "no" }, 297 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 298 { "hpet", HPET_INTCAP, "4" }, 299 }; 300 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 301 302 GlobalProperty pc_compat_1_6[] = { 303 PC_CPU_MODEL_IDS("1.6.0") 304 { "e1000", "mitigation", "off" }, 305 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 306 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 307 { "i440FX-pcihost", "short_root_bus", "1" }, 308 { "q35-pcihost", "short_root_bus", "1" }, 309 }; 310 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 311 312 GlobalProperty pc_compat_1_5[] = { 313 PC_CPU_MODEL_IDS("1.5.0") 314 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 315 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 316 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 317 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 318 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 319 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 320 { "virtio-net-pci", "any_layout", "off" }, 321 { TYPE_X86_CPU, "pmu", "on" }, 322 { "i440FX-pcihost", "short_root_bus", "0" }, 323 { "q35-pcihost", "short_root_bus", "0" }, 324 }; 325 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 326 327 GlobalProperty pc_compat_1_4[] = { 328 PC_CPU_MODEL_IDS("1.4.0") 329 { "scsi-hd", "discard_granularity", "0" }, 330 { "scsi-cd", "discard_granularity", "0" }, 331 { "scsi-disk", "discard_granularity", "0" }, 332 { "ide-hd", "discard_granularity", "0" }, 333 { "ide-cd", "discard_granularity", "0" }, 334 { "ide-drive", "discard_granularity", "0" }, 335 { "virtio-blk-pci", "discard_granularity", "0" }, 336 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 337 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 338 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 339 { "e1000", "romfile", "pxe-e1000.rom" }, 340 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 341 { "pcnet", "romfile", "pxe-pcnet.rom" }, 342 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 343 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 344 { "486-" TYPE_X86_CPU, "model", "0" }, 345 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 346 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 347 }; 348 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 349 350 void gsi_handler(void *opaque, int n, int level) 351 { 352 GSIState *s = opaque; 353 354 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 355 if (n < ISA_NUM_IRQS) { 356 qemu_set_irq(s->i8259_irq[n], level); 357 } 358 qemu_set_irq(s->ioapic_irq[n], level); 359 } 360 361 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 362 { 363 GSIState *s; 364 365 s = g_new0(GSIState, 1); 366 if (kvm_ioapic_in_kernel()) { 367 kvm_pc_setup_irq_routing(pci_enabled); 368 *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS); 369 } else { 370 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 371 } 372 373 return s; 374 } 375 376 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 377 unsigned size) 378 { 379 } 380 381 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 382 { 383 return 0xffffffffffffffffULL; 384 } 385 386 /* MSDOS compatibility mode FPU exception support */ 387 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 388 unsigned size) 389 { 390 if (tcg_enabled()) { 391 cpu_set_ignne(); 392 } 393 } 394 395 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 396 { 397 return 0xffffffffffffffffULL; 398 } 399 400 /* TSC handling */ 401 uint64_t cpu_get_tsc(CPUX86State *env) 402 { 403 return cpu_get_ticks(); 404 } 405 406 /* IRQ handling */ 407 int cpu_get_pic_interrupt(CPUX86State *env) 408 { 409 X86CPU *cpu = env_archcpu(env); 410 int intno; 411 412 if (!kvm_irqchip_in_kernel()) { 413 intno = apic_get_interrupt(cpu->apic_state); 414 if (intno >= 0) { 415 return intno; 416 } 417 /* read the irq from the PIC */ 418 if (!apic_accept_pic_intr(cpu->apic_state)) { 419 return -1; 420 } 421 } 422 423 intno = pic_read_irq(isa_pic); 424 return intno; 425 } 426 427 static void pic_irq_request(void *opaque, int irq, int level) 428 { 429 CPUState *cs = first_cpu; 430 X86CPU *cpu = X86_CPU(cs); 431 432 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 433 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 434 CPU_FOREACH(cs) { 435 cpu = X86_CPU(cs); 436 if (apic_accept_pic_intr(cpu->apic_state)) { 437 apic_deliver_pic_intr(cpu->apic_state, level); 438 } 439 } 440 } else { 441 if (level) { 442 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 443 } else { 444 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 445 } 446 } 447 } 448 449 /* PC cmos mappings */ 450 451 #define REG_EQUIPMENT_BYTE 0x14 452 453 int cmos_get_fd_drive_type(FloppyDriveType fd0) 454 { 455 int val; 456 457 switch (fd0) { 458 case FLOPPY_DRIVE_TYPE_144: 459 /* 1.44 Mb 3"5 drive */ 460 val = 4; 461 break; 462 case FLOPPY_DRIVE_TYPE_288: 463 /* 2.88 Mb 3"5 drive */ 464 val = 5; 465 break; 466 case FLOPPY_DRIVE_TYPE_120: 467 /* 1.2 Mb 5"5 drive */ 468 val = 2; 469 break; 470 case FLOPPY_DRIVE_TYPE_NONE: 471 default: 472 val = 0; 473 break; 474 } 475 return val; 476 } 477 478 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 479 int16_t cylinders, int8_t heads, int8_t sectors) 480 { 481 rtc_set_memory(s, type_ofs, 47); 482 rtc_set_memory(s, info_ofs, cylinders); 483 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 484 rtc_set_memory(s, info_ofs + 2, heads); 485 rtc_set_memory(s, info_ofs + 3, 0xff); 486 rtc_set_memory(s, info_ofs + 4, 0xff); 487 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 488 rtc_set_memory(s, info_ofs + 6, cylinders); 489 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 490 rtc_set_memory(s, info_ofs + 8, sectors); 491 } 492 493 /* convert boot_device letter to something recognizable by the bios */ 494 static int boot_device2nibble(char boot_device) 495 { 496 switch(boot_device) { 497 case 'a': 498 case 'b': 499 return 0x01; /* floppy boot */ 500 case 'c': 501 return 0x02; /* hard drive boot */ 502 case 'd': 503 return 0x03; /* CD-ROM boot */ 504 case 'n': 505 return 0x04; /* Network boot */ 506 } 507 return 0; 508 } 509 510 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 511 { 512 #define PC_MAX_BOOT_DEVICES 3 513 int nbds, bds[3] = { 0, }; 514 int i; 515 516 nbds = strlen(boot_device); 517 if (nbds > PC_MAX_BOOT_DEVICES) { 518 error_setg(errp, "Too many boot devices for PC"); 519 return; 520 } 521 for (i = 0; i < nbds; i++) { 522 bds[i] = boot_device2nibble(boot_device[i]); 523 if (bds[i] == 0) { 524 error_setg(errp, "Invalid boot device for PC: '%c'", 525 boot_device[i]); 526 return; 527 } 528 } 529 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 530 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 531 } 532 533 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 534 { 535 set_boot_dev(opaque, boot_device, errp); 536 } 537 538 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 539 { 540 int val, nb, i; 541 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 542 FLOPPY_DRIVE_TYPE_NONE }; 543 544 /* floppy type */ 545 if (floppy) { 546 for (i = 0; i < 2; i++) { 547 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 548 } 549 } 550 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 551 cmos_get_fd_drive_type(fd_type[1]); 552 rtc_set_memory(rtc_state, 0x10, val); 553 554 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 555 nb = 0; 556 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 557 nb++; 558 } 559 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 560 nb++; 561 } 562 switch (nb) { 563 case 0: 564 break; 565 case 1: 566 val |= 0x01; /* 1 drive, ready for boot */ 567 break; 568 case 2: 569 val |= 0x41; /* 2 drives, ready for boot */ 570 break; 571 } 572 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 573 } 574 575 typedef struct pc_cmos_init_late_arg { 576 ISADevice *rtc_state; 577 BusState *idebus[2]; 578 } pc_cmos_init_late_arg; 579 580 typedef struct check_fdc_state { 581 ISADevice *floppy; 582 bool multiple; 583 } CheckFdcState; 584 585 static int check_fdc(Object *obj, void *opaque) 586 { 587 CheckFdcState *state = opaque; 588 Object *fdc; 589 uint32_t iobase; 590 Error *local_err = NULL; 591 592 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 593 if (!fdc) { 594 return 0; 595 } 596 597 iobase = object_property_get_uint(obj, "iobase", &local_err); 598 if (local_err || iobase != 0x3f0) { 599 error_free(local_err); 600 return 0; 601 } 602 603 if (state->floppy) { 604 state->multiple = true; 605 } else { 606 state->floppy = ISA_DEVICE(obj); 607 } 608 return 0; 609 } 610 611 static const char * const fdc_container_path[] = { 612 "/unattached", "/peripheral", "/peripheral-anon" 613 }; 614 615 /* 616 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 617 * and ACPI objects. 618 */ 619 ISADevice *pc_find_fdc0(void) 620 { 621 int i; 622 Object *container; 623 CheckFdcState state = { 0 }; 624 625 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 626 container = container_get(qdev_get_machine(), fdc_container_path[i]); 627 object_child_foreach(container, check_fdc, &state); 628 } 629 630 if (state.multiple) { 631 warn_report("multiple floppy disk controllers with " 632 "iobase=0x3f0 have been found"); 633 error_printf("the one being picked for CMOS setup might not reflect " 634 "your intent"); 635 } 636 637 return state.floppy; 638 } 639 640 static void pc_cmos_init_late(void *opaque) 641 { 642 pc_cmos_init_late_arg *arg = opaque; 643 ISADevice *s = arg->rtc_state; 644 int16_t cylinders; 645 int8_t heads, sectors; 646 int val; 647 int i, trans; 648 649 val = 0; 650 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 651 &cylinders, &heads, §ors) >= 0) { 652 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 653 val |= 0xf0; 654 } 655 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 656 &cylinders, &heads, §ors) >= 0) { 657 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 658 val |= 0x0f; 659 } 660 rtc_set_memory(s, 0x12, val); 661 662 val = 0; 663 for (i = 0; i < 4; i++) { 664 /* NOTE: ide_get_geometry() returns the physical 665 geometry. It is always such that: 1 <= sects <= 63, 1 666 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 667 geometry can be different if a translation is done. */ 668 if (arg->idebus[i / 2] && 669 ide_get_geometry(arg->idebus[i / 2], i % 2, 670 &cylinders, &heads, §ors) >= 0) { 671 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 672 assert((trans & ~3) == 0); 673 val |= trans << (i * 2); 674 } 675 } 676 rtc_set_memory(s, 0x39, val); 677 678 pc_cmos_init_floppy(s, pc_find_fdc0()); 679 680 qemu_unregister_reset(pc_cmos_init_late, opaque); 681 } 682 683 void pc_cmos_init(PCMachineState *pcms, 684 BusState *idebus0, BusState *idebus1, 685 ISADevice *s) 686 { 687 int val; 688 static pc_cmos_init_late_arg arg; 689 X86MachineState *x86ms = X86_MACHINE(pcms); 690 691 /* various important CMOS locations needed by PC/Bochs bios */ 692 693 /* memory size */ 694 /* base memory (first MiB) */ 695 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 696 rtc_set_memory(s, 0x15, val); 697 rtc_set_memory(s, 0x16, val >> 8); 698 /* extended memory (next 64MiB) */ 699 if (x86ms->below_4g_mem_size > 1 * MiB) { 700 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 701 } else { 702 val = 0; 703 } 704 if (val > 65535) 705 val = 65535; 706 rtc_set_memory(s, 0x17, val); 707 rtc_set_memory(s, 0x18, val >> 8); 708 rtc_set_memory(s, 0x30, val); 709 rtc_set_memory(s, 0x31, val >> 8); 710 /* memory between 16MiB and 4GiB */ 711 if (x86ms->below_4g_mem_size > 16 * MiB) { 712 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 713 } else { 714 val = 0; 715 } 716 if (val > 65535) 717 val = 65535; 718 rtc_set_memory(s, 0x34, val); 719 rtc_set_memory(s, 0x35, val >> 8); 720 /* memory above 4GiB */ 721 val = x86ms->above_4g_mem_size / 65536; 722 rtc_set_memory(s, 0x5b, val); 723 rtc_set_memory(s, 0x5c, val >> 8); 724 rtc_set_memory(s, 0x5d, val >> 16); 725 726 object_property_add_link(OBJECT(pcms), "rtc_state", 727 TYPE_ISA_DEVICE, 728 (Object **)&x86ms->rtc, 729 object_property_allow_set_link, 730 OBJ_PROP_LINK_STRONG, &error_abort); 731 object_property_set_link(OBJECT(pcms), OBJECT(s), 732 "rtc_state", &error_abort); 733 734 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 735 736 val = 0; 737 val |= 0x02; /* FPU is there */ 738 val |= 0x04; /* PS/2 mouse installed */ 739 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 740 741 /* hard drives and FDC */ 742 arg.rtc_state = s; 743 arg.idebus[0] = idebus0; 744 arg.idebus[1] = idebus1; 745 qemu_register_reset(pc_cmos_init_late, &arg); 746 } 747 748 #define TYPE_PORT92 "port92" 749 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 750 751 /* port 92 stuff: could be split off */ 752 typedef struct Port92State { 753 ISADevice parent_obj; 754 755 MemoryRegion io; 756 uint8_t outport; 757 qemu_irq a20_out; 758 } Port92State; 759 760 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 761 unsigned size) 762 { 763 Port92State *s = opaque; 764 int oldval = s->outport; 765 766 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 767 s->outport = val; 768 qemu_set_irq(s->a20_out, (val >> 1) & 1); 769 if ((val & 1) && !(oldval & 1)) { 770 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 771 } 772 } 773 774 static uint64_t port92_read(void *opaque, hwaddr addr, 775 unsigned size) 776 { 777 Port92State *s = opaque; 778 uint32_t ret; 779 780 ret = s->outport; 781 DPRINTF("port92: read 0x%02x\n", ret); 782 return ret; 783 } 784 785 static void port92_init(ISADevice *dev, qemu_irq a20_out) 786 { 787 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 788 } 789 790 static const VMStateDescription vmstate_port92_isa = { 791 .name = "port92", 792 .version_id = 1, 793 .minimum_version_id = 1, 794 .fields = (VMStateField[]) { 795 VMSTATE_UINT8(outport, Port92State), 796 VMSTATE_END_OF_LIST() 797 } 798 }; 799 800 static void port92_reset(DeviceState *d) 801 { 802 Port92State *s = PORT92(d); 803 804 s->outport &= ~1; 805 } 806 807 static const MemoryRegionOps port92_ops = { 808 .read = port92_read, 809 .write = port92_write, 810 .impl = { 811 .min_access_size = 1, 812 .max_access_size = 1, 813 }, 814 .endianness = DEVICE_LITTLE_ENDIAN, 815 }; 816 817 static void port92_initfn(Object *obj) 818 { 819 Port92State *s = PORT92(obj); 820 821 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 822 823 s->outport = 0; 824 825 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 826 } 827 828 static void port92_realizefn(DeviceState *dev, Error **errp) 829 { 830 ISADevice *isadev = ISA_DEVICE(dev); 831 Port92State *s = PORT92(dev); 832 833 isa_register_ioport(isadev, &s->io, 0x92); 834 } 835 836 static void port92_class_initfn(ObjectClass *klass, void *data) 837 { 838 DeviceClass *dc = DEVICE_CLASS(klass); 839 840 dc->realize = port92_realizefn; 841 dc->reset = port92_reset; 842 dc->vmsd = &vmstate_port92_isa; 843 /* 844 * Reason: unlike ordinary ISA devices, this one needs additional 845 * wiring: its A20 output line needs to be wired up by 846 * port92_init(). 847 */ 848 dc->user_creatable = false; 849 } 850 851 static const TypeInfo port92_info = { 852 .name = TYPE_PORT92, 853 .parent = TYPE_ISA_DEVICE, 854 .instance_size = sizeof(Port92State), 855 .instance_init = port92_initfn, 856 .class_init = port92_class_initfn, 857 }; 858 859 static void port92_register_types(void) 860 { 861 type_register_static(&port92_info); 862 } 863 864 type_init(port92_register_types) 865 866 static void handle_a20_line_change(void *opaque, int irq, int level) 867 { 868 X86CPU *cpu = opaque; 869 870 /* XXX: send to all CPUs ? */ 871 /* XXX: add logic to handle multiple A20 line sources */ 872 x86_cpu_set_a20(cpu, level); 873 } 874 875 #define NE2000_NB_MAX 6 876 877 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 878 0x280, 0x380 }; 879 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 880 881 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 882 { 883 static int nb_ne2k = 0; 884 885 if (nb_ne2k == NE2000_NB_MAX) 886 return; 887 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 888 ne2000_irq[nb_ne2k], nd); 889 nb_ne2k++; 890 } 891 892 DeviceState *cpu_get_current_apic(void) 893 { 894 if (current_cpu) { 895 X86CPU *cpu = X86_CPU(current_cpu); 896 return cpu->apic_state; 897 } else { 898 return NULL; 899 } 900 } 901 902 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 903 { 904 X86CPU *cpu = opaque; 905 906 if (level) { 907 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 908 } 909 } 910 911 /* 912 * This function is very similar to smp_parse() 913 * in hw/core/machine.c but includes CPU die support. 914 */ 915 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 916 { 917 X86MachineState *x86ms = X86_MACHINE(ms); 918 919 if (opts) { 920 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 921 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 922 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 923 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 924 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 925 926 /* compute missing values, prefer sockets over cores over threads */ 927 if (cpus == 0 || sockets == 0) { 928 cores = cores > 0 ? cores : 1; 929 threads = threads > 0 ? threads : 1; 930 if (cpus == 0) { 931 sockets = sockets > 0 ? sockets : 1; 932 cpus = cores * threads * dies * sockets; 933 } else { 934 ms->smp.max_cpus = 935 qemu_opt_get_number(opts, "maxcpus", cpus); 936 sockets = ms->smp.max_cpus / (cores * threads * dies); 937 } 938 } else if (cores == 0) { 939 threads = threads > 0 ? threads : 1; 940 cores = cpus / (sockets * dies * threads); 941 cores = cores > 0 ? cores : 1; 942 } else if (threads == 0) { 943 threads = cpus / (cores * dies * sockets); 944 threads = threads > 0 ? threads : 1; 945 } else if (sockets * dies * cores * threads < cpus) { 946 error_report("cpu topology: " 947 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 948 "smp_cpus (%u)", 949 sockets, dies, cores, threads, cpus); 950 exit(1); 951 } 952 953 ms->smp.max_cpus = 954 qemu_opt_get_number(opts, "maxcpus", cpus); 955 956 if (ms->smp.max_cpus < cpus) { 957 error_report("maxcpus must be equal to or greater than smp"); 958 exit(1); 959 } 960 961 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 962 error_report("cpu topology: " 963 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 964 "maxcpus (%u)", 965 sockets, dies, cores, threads, 966 ms->smp.max_cpus); 967 exit(1); 968 } 969 970 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 971 warn_report("Invalid CPU topology deprecated: " 972 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 973 "!= maxcpus (%u)", 974 sockets, dies, cores, threads, 975 ms->smp.max_cpus); 976 } 977 978 ms->smp.cpus = cpus; 979 ms->smp.cores = cores; 980 ms->smp.threads = threads; 981 x86ms->smp_dies = dies; 982 } 983 984 if (ms->smp.cpus > 1) { 985 Error *blocker = NULL; 986 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 987 replay_add_blocker(blocker); 988 } 989 } 990 991 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 992 { 993 X86MachineState *x86ms = X86_MACHINE(ms); 994 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); 995 Error *local_err = NULL; 996 997 if (id < 0) { 998 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 999 return; 1000 } 1001 1002 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1003 error_setg(errp, "Unable to add CPU: %" PRIi64 1004 ", resulting APIC ID (%" PRIi64 ") is too large", 1005 id, apic_id); 1006 return; 1007 } 1008 1009 1010 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); 1011 if (local_err) { 1012 error_propagate(errp, local_err); 1013 return; 1014 } 1015 } 1016 1017 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1018 { 1019 if (cpus_count > 0xff) { 1020 /* If the number of CPUs can't be represented in 8 bits, the 1021 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1022 * to make old BIOSes fail more predictably. 1023 */ 1024 rtc_set_memory(rtc, 0x5f, 0); 1025 } else { 1026 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1027 } 1028 } 1029 1030 static 1031 void pc_machine_done(Notifier *notifier, void *data) 1032 { 1033 PCMachineState *pcms = container_of(notifier, 1034 PCMachineState, machine_done); 1035 X86MachineState *x86ms = X86_MACHINE(pcms); 1036 PCIBus *bus = pcms->bus; 1037 1038 /* set the number of CPUs */ 1039 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1040 1041 if (bus) { 1042 int extra_hosts = 0; 1043 1044 QLIST_FOREACH(bus, &bus->child, sibling) { 1045 /* look for expander root buses */ 1046 if (pci_bus_is_root(bus)) { 1047 extra_hosts++; 1048 } 1049 } 1050 if (extra_hosts && x86ms->fw_cfg) { 1051 uint64_t *val = g_malloc(sizeof(*val)); 1052 *val = cpu_to_le64(extra_hosts); 1053 fw_cfg_add_file(x86ms->fw_cfg, 1054 "etc/extra-pci-roots", val, sizeof(*val)); 1055 } 1056 } 1057 1058 acpi_setup(); 1059 if (x86ms->fw_cfg) { 1060 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 1061 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 1062 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1063 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1064 } 1065 1066 if (x86ms->apic_id_limit > 255 && !xen_enabled()) { 1067 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1068 1069 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1070 iommu->intr_eim != ON_OFF_AUTO_ON) { 1071 error_report("current -smp configuration requires " 1072 "Extended Interrupt Mode enabled. " 1073 "You can add an IOMMU using: " 1074 "-device intel-iommu,intremap=on,eim=on"); 1075 exit(EXIT_FAILURE); 1076 } 1077 } 1078 } 1079 1080 void pc_guest_info_init(PCMachineState *pcms) 1081 { 1082 int i; 1083 MachineState *ms = MACHINE(pcms); 1084 X86MachineState *x86ms = X86_MACHINE(pcms); 1085 1086 x86ms->apic_xrupt_override = kvm_allows_irq0_override(); 1087 pcms->numa_nodes = ms->numa_state->num_nodes; 1088 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1089 sizeof *pcms->node_mem); 1090 for (i = 0; i < ms->numa_state->num_nodes; i++) { 1091 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 1092 } 1093 1094 pcms->machine_done.notify = pc_machine_done; 1095 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1096 } 1097 1098 /* setup pci memory address space mapping into system address space */ 1099 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1100 MemoryRegion *pci_address_space) 1101 { 1102 /* Set to lower priority than RAM */ 1103 memory_region_add_subregion_overlap(system_memory, 0x0, 1104 pci_address_space, -1); 1105 } 1106 1107 void xen_load_linux(PCMachineState *pcms) 1108 { 1109 int i; 1110 FWCfgState *fw_cfg; 1111 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1112 X86MachineState *x86ms = X86_MACHINE(pcms); 1113 1114 assert(MACHINE(pcms)->kernel_filename != NULL); 1115 1116 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1117 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1118 rom_set_fw(fw_cfg); 1119 1120 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1121 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 1122 for (i = 0; i < nb_option_roms; i++) { 1123 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1124 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1125 !strcmp(option_rom[i].name, "pvh.bin") || 1126 !strcmp(option_rom[i].name, "multiboot.bin")); 1127 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1128 } 1129 x86ms->fw_cfg = fw_cfg; 1130 } 1131 1132 void pc_memory_init(PCMachineState *pcms, 1133 MemoryRegion *system_memory, 1134 MemoryRegion *rom_memory, 1135 MemoryRegion **ram_memory) 1136 { 1137 int linux_boot, i; 1138 MemoryRegion *ram, *option_rom_mr; 1139 MemoryRegion *ram_below_4g, *ram_above_4g; 1140 FWCfgState *fw_cfg; 1141 MachineState *machine = MACHINE(pcms); 1142 MachineClass *mc = MACHINE_GET_CLASS(machine); 1143 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1144 X86MachineState *x86ms = X86_MACHINE(pcms); 1145 1146 assert(machine->ram_size == x86ms->below_4g_mem_size + 1147 x86ms->above_4g_mem_size); 1148 1149 linux_boot = (machine->kernel_filename != NULL); 1150 1151 /* Allocate RAM. We allocate it as a single memory region and use 1152 * aliases to address portions of it, mostly for backwards compatibility 1153 * with older qemus that used qemu_ram_alloc(). 1154 */ 1155 ram = g_malloc(sizeof(*ram)); 1156 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1157 machine->ram_size); 1158 *ram_memory = ram; 1159 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1160 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1161 0, x86ms->below_4g_mem_size); 1162 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1163 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1164 if (x86ms->above_4g_mem_size > 0) { 1165 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1166 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1167 x86ms->below_4g_mem_size, 1168 x86ms->above_4g_mem_size); 1169 memory_region_add_subregion(system_memory, 0x100000000ULL, 1170 ram_above_4g); 1171 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 1172 } 1173 1174 if (!pcmc->has_reserved_memory && 1175 (machine->ram_slots || 1176 (machine->maxram_size > machine->ram_size))) { 1177 1178 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1179 mc->name); 1180 exit(EXIT_FAILURE); 1181 } 1182 1183 /* always allocate the device memory information */ 1184 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1185 1186 /* initialize device memory address space */ 1187 if (pcmc->has_reserved_memory && 1188 (machine->ram_size < machine->maxram_size)) { 1189 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1190 1191 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1192 error_report("unsupported amount of memory slots: %"PRIu64, 1193 machine->ram_slots); 1194 exit(EXIT_FAILURE); 1195 } 1196 1197 if (QEMU_ALIGN_UP(machine->maxram_size, 1198 TARGET_PAGE_SIZE) != machine->maxram_size) { 1199 error_report("maximum memory size must by aligned to multiple of " 1200 "%d bytes", TARGET_PAGE_SIZE); 1201 exit(EXIT_FAILURE); 1202 } 1203 1204 machine->device_memory->base = 1205 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 1206 1207 if (pcmc->enforce_aligned_dimm) { 1208 /* size device region assuming 1G page max alignment per slot */ 1209 device_mem_size += (1 * GiB) * machine->ram_slots; 1210 } 1211 1212 if ((machine->device_memory->base + device_mem_size) < 1213 device_mem_size) { 1214 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1215 machine->maxram_size); 1216 exit(EXIT_FAILURE); 1217 } 1218 1219 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1220 "device-memory", device_mem_size); 1221 memory_region_add_subregion(system_memory, machine->device_memory->base, 1222 &machine->device_memory->mr); 1223 } 1224 1225 /* Initialize PC system firmware */ 1226 pc_system_firmware_init(pcms, rom_memory); 1227 1228 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1229 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1230 &error_fatal); 1231 if (pcmc->pci_enabled) { 1232 memory_region_set_readonly(option_rom_mr, true); 1233 } 1234 memory_region_add_subregion_overlap(rom_memory, 1235 PC_ROM_MIN_VGA, 1236 option_rom_mr, 1237 1); 1238 1239 fw_cfg = fw_cfg_arch_create(machine, 1240 x86ms->boot_cpus, x86ms->apic_id_limit); 1241 1242 rom_set_fw(fw_cfg); 1243 1244 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1245 uint64_t *val = g_malloc(sizeof(*val)); 1246 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1247 uint64_t res_mem_end = machine->device_memory->base; 1248 1249 if (!pcmc->broken_reserved_end) { 1250 res_mem_end += memory_region_size(&machine->device_memory->mr); 1251 } 1252 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1253 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1254 } 1255 1256 if (linux_boot) { 1257 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1258 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 1259 } 1260 1261 for (i = 0; i < nb_option_roms; i++) { 1262 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1263 } 1264 x86ms->fw_cfg = fw_cfg; 1265 1266 /* Init default IOAPIC address space */ 1267 x86ms->ioapic_as = &address_space_memory; 1268 1269 /* Init ACPI memory hotplug IO base address */ 1270 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1271 } 1272 1273 /* 1274 * The 64bit pci hole starts after "above 4G RAM" and 1275 * potentially the space reserved for memory hotplug. 1276 */ 1277 uint64_t pc_pci_hole64_start(void) 1278 { 1279 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1280 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1281 MachineState *ms = MACHINE(pcms); 1282 X86MachineState *x86ms = X86_MACHINE(pcms); 1283 uint64_t hole64_start = 0; 1284 1285 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1286 hole64_start = ms->device_memory->base; 1287 if (!pcmc->broken_reserved_end) { 1288 hole64_start += memory_region_size(&ms->device_memory->mr); 1289 } 1290 } else { 1291 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1292 } 1293 1294 return ROUND_UP(hole64_start, 1 * GiB); 1295 } 1296 1297 qemu_irq pc_allocate_cpu_irq(void) 1298 { 1299 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1300 } 1301 1302 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1303 { 1304 DeviceState *dev = NULL; 1305 1306 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1307 if (pci_bus) { 1308 PCIDevice *pcidev = pci_vga_init(pci_bus); 1309 dev = pcidev ? &pcidev->qdev : NULL; 1310 } else if (isa_bus) { 1311 ISADevice *isadev = isa_vga_init(isa_bus); 1312 dev = isadev ? DEVICE(isadev) : NULL; 1313 } 1314 rom_reset_order_override(); 1315 return dev; 1316 } 1317 1318 static const MemoryRegionOps ioport80_io_ops = { 1319 .write = ioport80_write, 1320 .read = ioport80_read, 1321 .endianness = DEVICE_NATIVE_ENDIAN, 1322 .impl = { 1323 .min_access_size = 1, 1324 .max_access_size = 1, 1325 }, 1326 }; 1327 1328 static const MemoryRegionOps ioportF0_io_ops = { 1329 .write = ioportF0_write, 1330 .read = ioportF0_read, 1331 .endianness = DEVICE_NATIVE_ENDIAN, 1332 .impl = { 1333 .min_access_size = 1, 1334 .max_access_size = 1, 1335 }, 1336 }; 1337 1338 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1339 { 1340 int i; 1341 DriveInfo *fd[MAX_FD]; 1342 qemu_irq *a20_line; 1343 ISADevice *i8042, *port92, *vmmouse; 1344 1345 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1346 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1347 1348 for (i = 0; i < MAX_FD; i++) { 1349 fd[i] = drive_get(IF_FLOPPY, 0, i); 1350 create_fdctrl |= !!fd[i]; 1351 } 1352 if (create_fdctrl) { 1353 fdctrl_init_isa(isa_bus, fd); 1354 } 1355 1356 i8042 = isa_create_simple(isa_bus, "i8042"); 1357 if (!no_vmport) { 1358 vmport_init(isa_bus); 1359 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1360 } else { 1361 vmmouse = NULL; 1362 } 1363 if (vmmouse) { 1364 DeviceState *dev = DEVICE(vmmouse); 1365 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1366 qdev_init_nofail(dev); 1367 } 1368 port92 = isa_create_simple(isa_bus, "port92"); 1369 1370 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1371 i8042_setup_a20_line(i8042, a20_line[0]); 1372 port92_init(port92, a20_line[1]); 1373 g_free(a20_line); 1374 } 1375 1376 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1377 ISADevice **rtc_state, 1378 bool create_fdctrl, 1379 bool no_vmport, 1380 bool has_pit, 1381 uint32_t hpet_irqs) 1382 { 1383 int i; 1384 DeviceState *hpet = NULL; 1385 int pit_isa_irq = 0; 1386 qemu_irq pit_alt_irq = NULL; 1387 qemu_irq rtc_irq = NULL; 1388 ISADevice *pit = NULL; 1389 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1390 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1391 1392 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1393 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1394 1395 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1396 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1397 1398 /* 1399 * Check if an HPET shall be created. 1400 * 1401 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1402 * when the HPET wants to take over. Thus we have to disable the latter. 1403 */ 1404 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1405 /* In order to set property, here not using sysbus_try_create_simple */ 1406 hpet = qdev_try_create(NULL, TYPE_HPET); 1407 if (hpet) { 1408 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1409 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1410 * IRQ8 and IRQ2. 1411 */ 1412 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1413 HPET_INTCAP, NULL); 1414 if (!compat) { 1415 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1416 } 1417 qdev_init_nofail(hpet); 1418 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1419 1420 for (i = 0; i < GSI_NUM_PINS; i++) { 1421 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1422 } 1423 pit_isa_irq = -1; 1424 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1425 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1426 } 1427 } 1428 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1429 1430 qemu_register_boot_set(pc_boot_set, *rtc_state); 1431 1432 if (!xen_enabled() && has_pit) { 1433 if (kvm_pit_in_kernel()) { 1434 pit = kvm_pit_init(isa_bus, 0x40); 1435 } else { 1436 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1437 } 1438 if (hpet) { 1439 /* connect PIT to output control line of the HPET */ 1440 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1441 } 1442 pcspk_init(isa_bus, pit); 1443 } 1444 1445 i8257_dma_init(isa_bus, 0); 1446 1447 /* Super I/O */ 1448 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1449 } 1450 1451 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1452 { 1453 int i; 1454 1455 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1456 for (i = 0; i < nb_nics; i++) { 1457 NICInfo *nd = &nd_table[i]; 1458 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1459 1460 if (g_str_equal(model, "ne2k_isa")) { 1461 pc_init_ne2k_isa(isa_bus, nd); 1462 } else { 1463 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1464 } 1465 } 1466 rom_reset_order_override(); 1467 } 1468 1469 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1470 { 1471 qemu_irq *i8259; 1472 1473 if (kvm_pic_in_kernel()) { 1474 i8259 = kvm_i8259_init(isa_bus); 1475 } else if (xen_enabled()) { 1476 i8259 = xen_interrupt_controller_init(); 1477 } else { 1478 i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq()); 1479 } 1480 1481 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1482 i8259_irqs[i] = i8259[i]; 1483 } 1484 1485 g_free(i8259); 1486 } 1487 1488 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1489 { 1490 DeviceState *dev; 1491 SysBusDevice *d; 1492 unsigned int i; 1493 1494 if (kvm_ioapic_in_kernel()) { 1495 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 1496 } else { 1497 dev = qdev_create(NULL, TYPE_IOAPIC); 1498 } 1499 if (parent_name) { 1500 object_property_add_child(object_resolve_path(parent_name, NULL), 1501 "ioapic", OBJECT(dev), NULL); 1502 } 1503 qdev_init_nofail(dev); 1504 d = SYS_BUS_DEVICE(dev); 1505 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1506 1507 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1508 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1509 } 1510 } 1511 1512 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1513 Error **errp) 1514 { 1515 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1516 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1517 const MachineState *ms = MACHINE(hotplug_dev); 1518 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1519 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1520 Error *local_err = NULL; 1521 1522 /* 1523 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1524 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1525 * addition to cover this case. 1526 */ 1527 if (!pcms->acpi_dev || !acpi_enabled) { 1528 error_setg(errp, 1529 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1530 return; 1531 } 1532 1533 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1534 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1535 return; 1536 } 1537 1538 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 1539 if (local_err) { 1540 error_propagate(errp, local_err); 1541 return; 1542 } 1543 1544 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1545 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1546 } 1547 1548 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1549 DeviceState *dev, Error **errp) 1550 { 1551 Error *local_err = NULL; 1552 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1553 MachineState *ms = MACHINE(hotplug_dev); 1554 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1555 1556 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 1557 if (local_err) { 1558 goto out; 1559 } 1560 1561 if (is_nvdimm) { 1562 nvdimm_plug(ms->nvdimms_state); 1563 } 1564 1565 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1566 out: 1567 error_propagate(errp, local_err); 1568 } 1569 1570 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1571 DeviceState *dev, Error **errp) 1572 { 1573 Error *local_err = NULL; 1574 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1575 1576 /* 1577 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1578 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1579 * addition to cover this case. 1580 */ 1581 if (!pcms->acpi_dev || !acpi_enabled) { 1582 error_setg(&local_err, 1583 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1584 goto out; 1585 } 1586 1587 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1588 error_setg(&local_err, 1589 "nvdimm device hot unplug is not supported yet."); 1590 goto out; 1591 } 1592 1593 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1594 &local_err); 1595 out: 1596 error_propagate(errp, local_err); 1597 } 1598 1599 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1600 DeviceState *dev, Error **errp) 1601 { 1602 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1603 Error *local_err = NULL; 1604 1605 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1606 if (local_err) { 1607 goto out; 1608 } 1609 1610 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1611 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1612 out: 1613 error_propagate(errp, local_err); 1614 } 1615 1616 static int pc_apic_cmp(const void *a, const void *b) 1617 { 1618 CPUArchId *apic_a = (CPUArchId *)a; 1619 CPUArchId *apic_b = (CPUArchId *)b; 1620 1621 return apic_a->arch_id - apic_b->arch_id; 1622 } 1623 1624 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1625 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 1626 * entry corresponding to CPU's apic_id returns NULL. 1627 */ 1628 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1629 { 1630 CPUArchId apic_id, *found_cpu; 1631 1632 apic_id.arch_id = id; 1633 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 1634 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 1635 pc_apic_cmp); 1636 if (found_cpu && idx) { 1637 *idx = found_cpu - ms->possible_cpus->cpus; 1638 } 1639 return found_cpu; 1640 } 1641 1642 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1643 DeviceState *dev, Error **errp) 1644 { 1645 CPUArchId *found_cpu; 1646 Error *local_err = NULL; 1647 X86CPU *cpu = X86_CPU(dev); 1648 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1649 X86MachineState *x86ms = X86_MACHINE(pcms); 1650 1651 if (pcms->acpi_dev) { 1652 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1653 if (local_err) { 1654 goto out; 1655 } 1656 } 1657 1658 /* increment the number of CPUs */ 1659 x86ms->boot_cpus++; 1660 if (x86ms->rtc) { 1661 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1662 } 1663 if (x86ms->fw_cfg) { 1664 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1665 } 1666 1667 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1668 found_cpu->cpu = OBJECT(dev); 1669 out: 1670 error_propagate(errp, local_err); 1671 } 1672 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1673 DeviceState *dev, Error **errp) 1674 { 1675 int idx = -1; 1676 Error *local_err = NULL; 1677 X86CPU *cpu = X86_CPU(dev); 1678 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1679 1680 if (!pcms->acpi_dev) { 1681 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 1682 goto out; 1683 } 1684 1685 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1686 assert(idx != -1); 1687 if (idx == 0) { 1688 error_setg(&local_err, "Boot CPU is unpluggable"); 1689 goto out; 1690 } 1691 1692 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1693 &local_err); 1694 if (local_err) { 1695 goto out; 1696 } 1697 1698 out: 1699 error_propagate(errp, local_err); 1700 1701 } 1702 1703 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1704 DeviceState *dev, Error **errp) 1705 { 1706 CPUArchId *found_cpu; 1707 Error *local_err = NULL; 1708 X86CPU *cpu = X86_CPU(dev); 1709 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1710 X86MachineState *x86ms = X86_MACHINE(pcms); 1711 1712 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1713 if (local_err) { 1714 goto out; 1715 } 1716 1717 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1718 found_cpu->cpu = NULL; 1719 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1720 1721 /* decrement the number of CPUs */ 1722 x86ms->boot_cpus--; 1723 /* Update the number of CPUs in CMOS */ 1724 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1725 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1726 out: 1727 error_propagate(errp, local_err); 1728 } 1729 1730 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1731 DeviceState *dev, Error **errp) 1732 { 1733 int idx; 1734 CPUState *cs; 1735 CPUArchId *cpu_slot; 1736 X86CPUTopoInfo topo; 1737 X86CPU *cpu = X86_CPU(dev); 1738 CPUX86State *env = &cpu->env; 1739 MachineState *ms = MACHINE(hotplug_dev); 1740 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1741 X86MachineState *x86ms = X86_MACHINE(pcms); 1742 unsigned int smp_cores = ms->smp.cores; 1743 unsigned int smp_threads = ms->smp.threads; 1744 1745 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 1746 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 1747 ms->cpu_type); 1748 return; 1749 } 1750 1751 env->nr_dies = x86ms->smp_dies; 1752 1753 /* 1754 * If APIC ID is not set, 1755 * set it based on socket/die/core/thread properties. 1756 */ 1757 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1758 int max_socket = (ms->smp.max_cpus - 1) / 1759 smp_threads / smp_cores / x86ms->smp_dies; 1760 1761 /* 1762 * die-id was optional in QEMU 4.0 and older, so keep it optional 1763 * if there's only one die per socket. 1764 */ 1765 if (cpu->die_id < 0 && x86ms->smp_dies == 1) { 1766 cpu->die_id = 0; 1767 } 1768 1769 if (cpu->socket_id < 0) { 1770 error_setg(errp, "CPU socket-id is not set"); 1771 return; 1772 } else if (cpu->socket_id > max_socket) { 1773 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1774 cpu->socket_id, max_socket); 1775 return; 1776 } 1777 if (cpu->die_id < 0) { 1778 error_setg(errp, "CPU die-id is not set"); 1779 return; 1780 } else if (cpu->die_id > x86ms->smp_dies - 1) { 1781 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 1782 cpu->die_id, x86ms->smp_dies - 1); 1783 return; 1784 } 1785 if (cpu->core_id < 0) { 1786 error_setg(errp, "CPU core-id is not set"); 1787 return; 1788 } else if (cpu->core_id > (smp_cores - 1)) { 1789 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1790 cpu->core_id, smp_cores - 1); 1791 return; 1792 } 1793 if (cpu->thread_id < 0) { 1794 error_setg(errp, "CPU thread-id is not set"); 1795 return; 1796 } else if (cpu->thread_id > (smp_threads - 1)) { 1797 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1798 cpu->thread_id, smp_threads - 1); 1799 return; 1800 } 1801 1802 topo.pkg_id = cpu->socket_id; 1803 topo.die_id = cpu->die_id; 1804 topo.core_id = cpu->core_id; 1805 topo.smt_id = cpu->thread_id; 1806 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, 1807 smp_threads, &topo); 1808 } 1809 1810 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1811 if (!cpu_slot) { 1812 MachineState *ms = MACHINE(pcms); 1813 1814 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1815 smp_cores, smp_threads, &topo); 1816 error_setg(errp, 1817 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 1818 " APIC ID %" PRIu32 ", valid index range 0:%d", 1819 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 1820 cpu->apic_id, ms->possible_cpus->len - 1); 1821 return; 1822 } 1823 1824 if (cpu_slot->cpu) { 1825 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1826 idx, cpu->apic_id); 1827 return; 1828 } 1829 1830 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1831 * so that machine_query_hotpluggable_cpus would show correct values 1832 */ 1833 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1834 * once -smp refactoring is complete and there will be CPU private 1835 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1836 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1837 smp_cores, smp_threads, &topo); 1838 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1839 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1840 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1841 return; 1842 } 1843 cpu->socket_id = topo.pkg_id; 1844 1845 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 1846 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 1847 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 1848 return; 1849 } 1850 cpu->die_id = topo.die_id; 1851 1852 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1853 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1854 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1855 return; 1856 } 1857 cpu->core_id = topo.core_id; 1858 1859 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1860 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1861 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1862 return; 1863 } 1864 cpu->thread_id = topo.smt_id; 1865 1866 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 1867 !kvm_hv_vpindex_settable()) { 1868 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 1869 return; 1870 } 1871 1872 cs = CPU(cpu); 1873 cs->cpu_index = idx; 1874 1875 numa_cpu_pre_plug(cpu_slot, dev, errp); 1876 } 1877 1878 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 1879 DeviceState *dev, Error **errp) 1880 { 1881 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1882 Error *local_err = NULL; 1883 1884 if (!hotplug_dev2) { 1885 /* 1886 * Without a bus hotplug handler, we cannot control the plug/unplug 1887 * order. This should never be the case on x86, however better add 1888 * a safety net. 1889 */ 1890 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 1891 return; 1892 } 1893 /* 1894 * First, see if we can plug this memory device at all. If that 1895 * succeeds, branch of to the actual hotplug handler. 1896 */ 1897 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1898 &local_err); 1899 if (!local_err) { 1900 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1901 } 1902 error_propagate(errp, local_err); 1903 } 1904 1905 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 1906 DeviceState *dev, Error **errp) 1907 { 1908 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1909 Error *local_err = NULL; 1910 1911 /* 1912 * Plug the memory device first and then branch off to the actual 1913 * hotplug handler. If that one fails, we can easily undo the memory 1914 * device bits. 1915 */ 1916 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1917 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1918 if (local_err) { 1919 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1920 } 1921 error_propagate(errp, local_err); 1922 } 1923 1924 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 1925 DeviceState *dev, Error **errp) 1926 { 1927 /* We don't support virtio pmem hot unplug */ 1928 error_setg(errp, "virtio pmem device unplug not supported."); 1929 } 1930 1931 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 1932 DeviceState *dev, Error **errp) 1933 { 1934 /* We don't support virtio pmem hot unplug */ 1935 } 1936 1937 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1938 DeviceState *dev, Error **errp) 1939 { 1940 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1941 pc_memory_pre_plug(hotplug_dev, dev, errp); 1942 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1943 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1944 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1945 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 1946 } 1947 } 1948 1949 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1950 DeviceState *dev, Error **errp) 1951 { 1952 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1953 pc_memory_plug(hotplug_dev, dev, errp); 1954 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1955 pc_cpu_plug(hotplug_dev, dev, errp); 1956 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1957 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 1958 } 1959 } 1960 1961 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1962 DeviceState *dev, Error **errp) 1963 { 1964 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1965 pc_memory_unplug_request(hotplug_dev, dev, errp); 1966 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1967 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1968 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1969 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 1970 } else { 1971 error_setg(errp, "acpi: device unplug request for not supported device" 1972 " type: %s", object_get_typename(OBJECT(dev))); 1973 } 1974 } 1975 1976 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1977 DeviceState *dev, Error **errp) 1978 { 1979 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1980 pc_memory_unplug(hotplug_dev, dev, errp); 1981 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1982 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 1983 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1984 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 1985 } else { 1986 error_setg(errp, "acpi: device unplug for not supported device" 1987 " type: %s", object_get_typename(OBJECT(dev))); 1988 } 1989 } 1990 1991 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1992 DeviceState *dev) 1993 { 1994 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1995 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1996 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1997 return HOTPLUG_HANDLER(machine); 1998 } 1999 2000 return NULL; 2001 } 2002 2003 static void 2004 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2005 const char *name, void *opaque, 2006 Error **errp) 2007 { 2008 MachineState *ms = MACHINE(obj); 2009 int64_t value = 0; 2010 2011 if (ms->device_memory) { 2012 value = memory_region_size(&ms->device_memory->mr); 2013 } 2014 2015 visit_type_int(v, name, &value, errp); 2016 } 2017 2018 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2019 void *opaque, Error **errp) 2020 { 2021 PCMachineState *pcms = PC_MACHINE(obj); 2022 OnOffAuto vmport = pcms->vmport; 2023 2024 visit_type_OnOffAuto(v, name, &vmport, errp); 2025 } 2026 2027 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2028 void *opaque, Error **errp) 2029 { 2030 PCMachineState *pcms = PC_MACHINE(obj); 2031 2032 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2033 } 2034 2035 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2036 { 2037 bool smm_available = false; 2038 2039 if (pcms->smm == ON_OFF_AUTO_OFF) { 2040 return false; 2041 } 2042 2043 if (tcg_enabled() || qtest_enabled()) { 2044 smm_available = true; 2045 } else if (kvm_enabled()) { 2046 smm_available = kvm_has_smm(); 2047 } 2048 2049 if (smm_available) { 2050 return true; 2051 } 2052 2053 if (pcms->smm == ON_OFF_AUTO_ON) { 2054 error_report("System Management Mode not supported by this hypervisor."); 2055 exit(1); 2056 } 2057 return false; 2058 } 2059 2060 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2061 void *opaque, Error **errp) 2062 { 2063 PCMachineState *pcms = PC_MACHINE(obj); 2064 OnOffAuto smm = pcms->smm; 2065 2066 visit_type_OnOffAuto(v, name, &smm, errp); 2067 } 2068 2069 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2070 void *opaque, Error **errp) 2071 { 2072 PCMachineState *pcms = PC_MACHINE(obj); 2073 2074 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2075 } 2076 2077 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2078 { 2079 PCMachineState *pcms = PC_MACHINE(obj); 2080 2081 return pcms->smbus_enabled; 2082 } 2083 2084 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2085 { 2086 PCMachineState *pcms = PC_MACHINE(obj); 2087 2088 pcms->smbus_enabled = value; 2089 } 2090 2091 static bool pc_machine_get_sata(Object *obj, Error **errp) 2092 { 2093 PCMachineState *pcms = PC_MACHINE(obj); 2094 2095 return pcms->sata_enabled; 2096 } 2097 2098 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2099 { 2100 PCMachineState *pcms = PC_MACHINE(obj); 2101 2102 pcms->sata_enabled = value; 2103 } 2104 2105 static bool pc_machine_get_pit(Object *obj, Error **errp) 2106 { 2107 PCMachineState *pcms = PC_MACHINE(obj); 2108 2109 return pcms->pit_enabled; 2110 } 2111 2112 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2113 { 2114 PCMachineState *pcms = PC_MACHINE(obj); 2115 2116 pcms->pit_enabled = value; 2117 } 2118 2119 static void pc_machine_initfn(Object *obj) 2120 { 2121 PCMachineState *pcms = PC_MACHINE(obj); 2122 2123 pcms->smm = ON_OFF_AUTO_AUTO; 2124 #ifdef CONFIG_VMPORT 2125 pcms->vmport = ON_OFF_AUTO_AUTO; 2126 #else 2127 pcms->vmport = ON_OFF_AUTO_OFF; 2128 #endif /* CONFIG_VMPORT */ 2129 /* acpi build is enabled by default if machine supports it */ 2130 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2131 pcms->smbus_enabled = true; 2132 pcms->sata_enabled = true; 2133 pcms->pit_enabled = true; 2134 2135 pc_system_flash_create(pcms); 2136 } 2137 2138 static void pc_machine_reset(MachineState *machine) 2139 { 2140 CPUState *cs; 2141 X86CPU *cpu; 2142 2143 qemu_devices_reset(); 2144 2145 /* Reset APIC after devices have been reset to cancel 2146 * any changes that qemu_devices_reset() might have done. 2147 */ 2148 CPU_FOREACH(cs) { 2149 cpu = X86_CPU(cs); 2150 2151 if (cpu->apic_state) { 2152 device_reset(cpu->apic_state); 2153 } 2154 } 2155 } 2156 2157 static void pc_machine_wakeup(MachineState *machine) 2158 { 2159 cpu_synchronize_all_states(); 2160 pc_machine_reset(machine); 2161 cpu_synchronize_all_post_reset(); 2162 } 2163 2164 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 2165 { 2166 X86IOMMUState *iommu = x86_iommu_get_default(); 2167 IntelIOMMUState *intel_iommu; 2168 2169 if (iommu && 2170 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 2171 object_dynamic_cast((Object *)dev, "vfio-pci")) { 2172 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2173 if (!intel_iommu->caching_mode) { 2174 error_setg(errp, "Device assignment is not allowed without " 2175 "enabling caching-mode=on for Intel IOMMU."); 2176 return false; 2177 } 2178 } 2179 2180 return true; 2181 } 2182 2183 static void pc_machine_class_init(ObjectClass *oc, void *data) 2184 { 2185 MachineClass *mc = MACHINE_CLASS(oc); 2186 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2187 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2188 2189 pcmc->pci_enabled = true; 2190 pcmc->has_acpi_build = true; 2191 pcmc->rsdp_in_ram = true; 2192 pcmc->smbios_defaults = true; 2193 pcmc->smbios_uuid_encoded = true; 2194 pcmc->gigabyte_align = true; 2195 pcmc->has_reserved_memory = true; 2196 pcmc->kvmclock_enabled = true; 2197 pcmc->enforce_aligned_dimm = true; 2198 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2199 * to be used at the moment, 32K should be enough for a while. */ 2200 pcmc->acpi_data_size = 0x20000 + 0x8000; 2201 pcmc->linuxboot_dma_enabled = true; 2202 pcmc->pvh_enabled = true; 2203 assert(!mc->get_hotplug_handler); 2204 mc->get_hotplug_handler = pc_get_hotplug_handler; 2205 mc->hotplug_allowed = pc_hotplug_allowed; 2206 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 2207 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 2208 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 2209 mc->auto_enable_numa_with_memhp = true; 2210 mc->has_hotpluggable_cpus = true; 2211 mc->default_boot_order = "cad"; 2212 mc->hot_add_cpu = pc_hot_add_cpu; 2213 mc->smp_parse = pc_smp_parse; 2214 mc->block_default_type = IF_IDE; 2215 mc->max_cpus = 255; 2216 mc->reset = pc_machine_reset; 2217 mc->wakeup = pc_machine_wakeup; 2218 hc->pre_plug = pc_machine_device_pre_plug_cb; 2219 hc->plug = pc_machine_device_plug_cb; 2220 hc->unplug_request = pc_machine_device_unplug_request_cb; 2221 hc->unplug = pc_machine_device_unplug_cb; 2222 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2223 mc->nvdimm_supported = true; 2224 mc->numa_mem_supported = true; 2225 2226 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2227 pc_machine_get_device_memory_region_size, NULL, 2228 NULL, NULL, &error_abort); 2229 2230 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2231 pc_machine_get_smm, pc_machine_set_smm, 2232 NULL, NULL, &error_abort); 2233 object_class_property_set_description(oc, PC_MACHINE_SMM, 2234 "Enable SMM (pc & q35)", &error_abort); 2235 2236 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2237 pc_machine_get_vmport, pc_machine_set_vmport, 2238 NULL, NULL, &error_abort); 2239 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2240 "Enable vmport (pc & q35)", &error_abort); 2241 2242 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2243 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2244 2245 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2246 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2247 2248 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2249 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2250 } 2251 2252 static const TypeInfo pc_machine_info = { 2253 .name = TYPE_PC_MACHINE, 2254 .parent = TYPE_X86_MACHINE, 2255 .abstract = true, 2256 .instance_size = sizeof(PCMachineState), 2257 .instance_init = pc_machine_initfn, 2258 .class_size = sizeof(PCMachineClass), 2259 .class_init = pc_machine_class_init, 2260 .interfaces = (InterfaceInfo[]) { 2261 { TYPE_HOTPLUG_HANDLER }, 2262 { } 2263 }, 2264 }; 2265 2266 static void pc_machine_register_types(void) 2267 { 2268 type_register_static(&pc_machine_info); 2269 } 2270 2271 type_init(pc_machine_register_types) 2272